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Jim, I knew it. I knew it! If I didn't put it in, someone would ask. I put it in, and then took it out. All right, your correct: the ESD is rated at >500 V. But once it is soldered in, there is the circuit that we suggest to go with the battery, which includes two diode drops from the lithium coin cell, and a 0.1uF cap. The 0.1uF cap alone will limit the strike to much much less energy that it would be without the 0.1uF cap. The diodes will not help at all, but they might provide another path for discharge, rather than to the device. (Thanks for keeping me honest), Austin Jim Granville wrote: > Austin Lesea wrote: > >> All, >> >> The question is: what to do with Vbatt if not used? >> >> If it is not used, then it really is a 'don't care'. You could float >> it, connect it to ground, or connect it to a Vcco. >> >> But if you let it float, it is a very low leakage pin (obviously, as >> you do not want to let the battery die from leakage). >> >> A very low leakage pin is also a very sensitive pin to ESD damage. >> >> So when we tested it for ESD, we decided to change the documentation >> to say to ground it if not used. >> >> If it gets zapped by an ESD discharge, it will have bad leakage. It >> is most unlikely to cause any other problems, but why take the risk? >> >> So, you are correct, in that we are correcting a problem. It is a >> very small, and very unlikely problem (customer removes part where >> Vbatt was left floating, Vbatt was zapped with an ESD discharge, and >> then uses it in an application where Vbatt is used, and the battery >> ends up running down in less than 25 years). > > > .. and field replacement of a battery, where the Vbatt is much more > physically exposed, is OK, or is High Risk ? - ie just what is the > ESD rating of the Vbatt pin ? > -jg >Article: 76351
Hi chaps, Many thanks for the replies. (snip) > For some designs it is easier to count total transitions than to > count rising or falling transitions. Otherwise, yes, it doesn't > matter as long as the 2 and 1/2 are in the right place. So, if 'a' is counting 0 to 1 only, then: P = aCV^2F is correct. If 'a' is counting 0 to 1 and 1 to 0 then P = 0.5aCV^2F is correct. Correct? :-) In the 2nd case we use 0.5 because the 1 to 0 transitions dissipate energy already drawn on the 0 to 1 transitions and we do not want to count it twice? I have seen the 2nd equation quoted often also with 'a' being referred to as the transition density at the node (which I assume means 0 to 1 and 1 to 0). I have also seen the 1st equation quoted with the same definition for 'a'. They can't both use the same definition for 'a' and be right.... Cheers, KenArticle: 76352
Ken wrote: > Hi chaps, > > Many thanks for the replies. > > (snip) > > >>For some designs it is easier to count total transitions than to >>count rising or falling transitions. Otherwise, yes, it doesn't >>matter as long as the 2 and 1/2 are in the right place. > > > So, if 'a' is counting 0 to 1 only, then: > > P = aCV^2F > > is correct. > > If 'a' is counting 0 to 1 and 1 to 0 then > > P = 0.5aCV^2F > > is correct. > > Correct? :-) > > In the 2nd case we use 0.5 because the 1 to 0 transitions dissipate energy > already drawn on the 0 to 1 transitions and we do not want to count it > twice? > > I have seen the 2nd equation quoted often also with 'a' being referred to as > the transition density at the node (which I assume means 0 to 1 and 1 to 0). > I have also seen the 1st equation quoted with the same definition for 'a'. > They can't both use the same definition for 'a' and be right.... They can if they adjust C :) If you are in a physics class, you have know C, ( and so 1 / 0/5 matters) but inside the devices, there are many C's and many drivers, so you choose an _effective_ C to match a point on the Power/Freq curve. If you want F to be edges, or F to be Clock that's up to you. The above eqn gives a feel for the physics, but is not the whole story. In data sheets, you will see a series of Power Dissipation Capacitance [effective] values quoted, to give the best fit for operating conditions. [ and of course, none of this factors in device leakage ] -jgArticle: 76353
Ken wrote: (snip regarding energy dissipation in CMOS) > So, if 'a' is counting 0 to 1 only, then: > P = aCV^2F > is correct. > If 'a' is counting 0 to 1 and 1 to 0 then > P = 0.5aCV^2F > is correct. > Correct? :-) > In the 2nd case we use 0.5 because the 1 to 0 transitions dissipate energy > already drawn on the 0 to 1 transitions and we do not want to count it > twice? The 1/2 comes from the integral of V dV, which is 0.5*V**2, or, as you said earlier, half ends up in the capacitor and half in the resistor. Stored energy in a capacitor is always 0.5*C*V**2. -- glenArticle: 76354
Jon Elson wrote: (someone wrote) >>> add a dummy buffer to split the wire before connecting to iopad/marker >> I had thought of that but i was not on that would not have perverse >> effects (i debute with FPGA). > It will have no effect. The synthesis just gets rid of anything that > doesn't affect the final outputs of the logic. Quartus has a logic device that looks like a buffer, but is called a wire. It separtes markers so one can connect wires with different names. But yes, for FPGA synthesis you will find that even inverters disappear into the input of the next CLB, or the output of the previous one. A chain of inverters cannot be used for delay without special indication for the software not to optimize them away. -- glenArticle: 76355
Thanks for the reply. I contacted our IT department, and they said that we do not have access to NNTPserver, and NNTP access may leave your computer exposed to viruses. In a word, they would not setup it for me. However, I still want to read it in my Outlook Newsreader. Does anybody know a NNTP server for "public" so I can log on? I know Microsoft provides "public" server for their own news groups, but I do not know who can provide a NNTP server for comp.* groups. Thanks in advance. Johnson "John_H" <johnhandwork@mail.com> wrote in message news:<45Mqd.2$8%.765@news-west.eli.net>... > "Johnson" <gpsabove@yahoo.com> wrote in message > news:b1ac2406.0411291241.43e1f524@posting.google.com... > > Hi there, > > > > I am a newbie and I do not know how to subscribe to the newsgroup > > listed in the following website. Could anybody let me know what is the > > server name for the newsgroup? I need it to fill the "Server > > Information" of my "Microsoft Outlook Newsreader"? > > > > http://jupiter.sun.csd.unb.ca/usenet/comp.html > > > > Thanks. > > > > Johnson > > Your server information comes from your Internet Service Provider and is not > a general internet value. If your ISP's webside doesn't contain a simple > link to setting up the news server, call your tech support line. > > If you can't get the information or don't want to set up within Outlook's > Newsreader, consider groups.google.com or - perhaps -groups.yahoo.com (you > have a yahoo email account but I can't reach groups.yahoo.com from work).Article: 76356
Thanks a lot, guys, I really got lots of information and insight. JohnsonArticle: 76357
Pete, Check your chirp generator. Does it do something funny every 1500 samples? If you've done the CIC filter properly, as I'm sure you know, it'll be the same as cascaded boxcar filters. You could compare your design's output with that of 4 cascaded boxcars to see if the glitch is still there. CICs work fine for me! Good luck mate, Syms. "pete dudley" <padudle@sandia.gov> wrote in message news:41acfba9$1_3@news3.es.net... > Hello All > > I'm doing a Digital DownConverter application with an overall sampling rate > reduction of 640. We want to use a so called CIC or Hogenauer filter for the > first decimate by 10 then follow with five decimate-by-2 halfband filters to > get 640. We are using a Xilinx VirtexII XC2V6000 to implement the hardware. > > We planned on using the Xilinx Coregen core for the Cascade Integrator Comb > CIC filter but I am finding peculiar glitches in its output. The parameters > for the filter are R=decimation=10, N=stages=4, M=difference delay=1, > Bin=input width=15. > > I wrote a simulation testbench that sweeps a linear FM chirp accross the > entire input Nyquist range and records the output data to a file. Every 1500 > output samples there is a notable glitch of magnitude -30dB with respect to > the filter full scale output. I keep input amplitude less than half what the > input port should be able to handle (+-8192 into 15 bit port) > > Thinking that the core was bad I wrote my own CIC filter from the Hogenauer > filter and it has exactly the same characteristics. With my own filter I can > look at the internal integrators and differentiators and the glitches occur > where there are general direction changes in the stage registers but with > all that accumulator overflow going on its hard to analyze. > > Has anyone else encountered this general glitching with CIC filters? Can you > see a systematic way to analyze such a problem? > > If interested I can share my filter design and testbench. > > Regards, > > Pete Dudley > >Article: 76358
SystemACE is a controller that streams data from a Compact Flash memory
to a daisy chain devices using the boundary-scan TAP. iMPACT can be
used to format bitstream files to be programmed onto the Compact Flash
for utilization with the controller. The compact flash can be
programmed using you PC and an appropriate cable provided by your
compact flash supplier.
The up/downstream connectors on the AFX board allow you to create a
longer boundary-scan chain of devices and is basically just serially
connects the 4 pins of the TAP on one board to the next.
I don't think SystemACE solves your problem in any meaningful way. You
should simply connect the boards in a serial daisy chain using the
boundary-scan signals and then use any Xilinx cable (Parallel Cable IV,
for instance) to program all your devices. Unless I misunderstood your
intentions...
Michael Dales wrote:
> Hi there,
>
> We have a bunch of Virtex-II Pro AFX boards we're using to build a
> single larger system. Currently we have a Parallel Cable IV
> programmer, and thus have to program each board individually. What
> we'd like to do is be able to program all the boards at the same time.
>
> The AFX boards all have upstream and downstream System ACE ports, and
> this seems to be a suitable interface to use, but I'm a bit confused
> as to what programmer and cabling I need to take advantage of this
> interface.
>
> Looking at the programmer on the Xilinx web site, the one that would
> appear to fit is the MultiPRO Desktop Tool:
>
> http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&key=HW-MULTIPRO
>
> This lists System ACE support in the data sheet, but doesn't explain
> how to actually do that. The 20 pin port on the side of the MiltiPRO
> device would appear to be similar to the System ACE interface pin out
> on the AFX board, but the descriptions don't match perfectly.
>
> Is it possible to use this device with a set of suitable ribbon cables
> to hook up a set of AFX boards and program all the V2P devices at
> once?
>
> Any information greatly appreciated!
>
> Cheers,
>
--
*CAUTION:* Shameless self-promotion follows...
Article: 76359
Check to make sure the integrator widths are correct (the gain is |N*R|^M). The
integrators need to be wide enough to accommodate the gain. I suspect your
widths are OK since you get the same result as the coregen macro, but check
anyway. Check the input signal to make sure the glitches are not being
introduced there. Make sure the input is 2's complement, not thermometer code.
pete dudley wrote:
> Hello All
>
> I'm doing a Digital DownConverter application with an overall sampling rate
> reduction of 640. We want to use a so called CIC or Hogenauer filter for the
> first decimate by 10 then follow with five decimate-by-2 halfband filters to
> get 640. We are using a Xilinx VirtexII XC2V6000 to implement the hardware.
>
> We planned on using the Xilinx Coregen core for the Cascade Integrator Comb
> CIC filter but I am finding peculiar glitches in its output. The parameters
> for the filter are R=decimation=10, N=stages=4, M=difference delay=1,
> Bin=input width=15.
>
> I wrote a simulation testbench that sweeps a linear FM chirp accross the
> entire input Nyquist range and records the output data to a file. Every 1500
> output samples there is a notable glitch of magnitude -30dB with respect to
> the filter full scale output. I keep input amplitude less than half what the
> input port should be able to handle (+-8192 into 15 bit port)
>
> Thinking that the core was bad I wrote my own CIC filter from the Hogenauer
> filter and it has exactly the same characteristics. With my own filter I can
> look at the internal integrators and differentiators and the glitches occur
> where there are general direction changes in the stage registers but with
> all that accumulator overflow going on its hard to analyze.
>
> Has anyone else encountered this general glitching with CIC filters? Can you
> see a systematic way to analyze such a problem?
>
> If interested I can share my filter design and testbench.
>
> Regards,
>
> Pete Dudley
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76360
Well, if you must use a tree (more on that in a minute), then your best bet
is to include RLOCs for the adders. You get reasonable performance by
placing the first level in every other slice column and then placing the
next levels in every other vacant column until you reach the root.
"Reasonable" depends on the depth of the tree and your clock speed of
course. It starts losing performance at 3 levels or so, because of the
progressively longer routes. You can make up the speed by adding pipeline
registers at the cost of real-estate.
In the case of an FIR filter, however, you don't need a tree. Instead, push
part or all of the tap delay through the coefficient multiplies so that you
can connect the adders in a linear array (ie daisy chained), absorbing the
delays into the adder registers. That gives you all nearest neighbor
connections, and if you do it right, the latency is actually less than a
tree. The cost is if you need to clock enable it, your control task is much
more complicated.
Kevin Neilson wrote:
> I'm trying to figure out the best way to floorplan registered adder
> trees, such as those used in FIR filters. The (Xilinx) placer seems to
> have very little idea what to do with these. Even when I use an area
> constraint around the whole tree, the individual adders are not
> optimally placed, so the result is that my critical path is always
> between adders, and not the adder carry chain itself. I always have to
> manually place each adder in the tree to get good results. My questions
> are:
> 1. Is there a way to get adder trees to work without manual placement?
> 2. Is the best placement for an adder tree a tree structure (wide at
> one end and narrow at the other) or some more rectangular arrangement?
> -Kevin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76361nweaver@soda.csua.berkeley.edu (Nicholas Weaver) wrote in message news:<coif35$vs4$1@agate.berkeley.edu>... > In article <313t6uF37n91nU1@uni-berlin.de>, > Symon <symon_brewer@hotmail.com> wrote: > >"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message > >news:coibq8$up9$1@agate.berkeley.edu... > >> Running at high utilization is a LOT easier if a large amount of the > >> logic is floorplanned/placed, it makes both placement easier and > >> routing easier. > >Spot on, Nicholas. One further point; often the time you spend on > >Floorplanning is more than recovered in P&R times, certainly for repeatedly > >used RPMs. > > And don't forget the performance win. I have a deliberately dinky 3 > pipeline stage encryption core: placing just PART of the core allows > the 125 MHz timing to be met easily, with a vast fraction of the tool > time. > > RLOC is your friend. There is another reason to consider hand placement even if you don't need the perf. When you build up a floorplan its as likely to go slower as faster so it it has to be done incrementally keeping only the better placement decisions. As the plan fills out you get a much better feel for what area different logic funcs take up. Its all very time consuming though! Worth doing for datapaths, but only for control logic if timing really forces it. For instance dualport LUT rams, srl16s, mux4s usually take 2 LUT sites and have to be paired with a related FF and leave 1 FF site unused. Apart from those, its almost possible to use up 99% of the FFs in a datapath as long as say the reg width are even and related registers are controlled by same signals. With that in mind, it then becomes possible to adjust the logic design so that more datapath logic will fall nicely into the unused LUT columns where there might be a row of plain FFs. This brings up 1 little gripe with XST mapper. When a ck en has large fanout and drives many different regs of different widths, the FF driving the enables will be split into clones (good part) but often the branches will enable groups of FFs that is less optimal and cuts across a slice pair. In my cpu project, with some 20 regular 16b regs on 1 enable I get told to remove 1 FF from the middle of a few of these regs because of this odd splitting which is tiresome. Its too early to manually split such enables. Are there any switches to force grouping of replicated FF signals to stay within pairs? Timing driven placement seemed to help, as well as not placing the ck enable FFs. My other gripe about floorplanning is the LUT structures/names are liable to change on me even if the logic that created it doesn't so I try not to place those since they tend to get placed/pulled near the connected FFs that I did place. Still lots to learn:-) regards johnjakson_usa_comArticle: 76362
Guenter Dannoritzer <dan_nospam_noritzer@web.de> wrote in message news:<coggir$g8a$00$1@news.t-online.com>...
> Hi,
>
> I have a design where a Spartan XL was replaced by a Spartan 3. The FPGA
> is configured by an ATmega MCU which loads the configuration file into
> the FPGA. This procedure works fine with the old board and the Spartan
> XL, but with the Spartan 3 I have the trouble that I never get the DONE
> signal, after the configuration is done.
>
> I see data going over the DIN line into the Spartan 3 and an active
> clock signal. As I did not change anything on the ATmega software this
> should be fine.
>
> I generated the binary for the Spartan 3 and enabled the setting for
> "Drive DONE Pin High", to have the DONE signal being driven.
>
> As the ATmega uses 3.3V the Spartan is used in the 3.3V compatibility
> mode for configuration. I am just not sure about the VCCO_4 signal, as
> the data sheet is for my understanding a bit confusing. In the design
> that I am using it is tied to 3.3V. Is that correct or does it need to
> be connected to 2.5V during configuration?
>
> Is there anything else I need to consider with the serial slave mode
> when switching from Spartan XL to Spartan 3?
>
> Thanks for the help.
>
> Guenter
When you find out the answer please post a reply to the group. I
am facing the same problem. I am trying to configure the digilent
spartan-3 board using slave serial mode using a USB controller. The
same setup works for a spartan-II
but not for spartan-3. I already tried adding extra clocks. That did
not help.
Sumit
sumit_nospam@nojunk.c-nit.net
Article: 76363"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message news:41acf0aa$0$66396$14726298@news.sunsite.dk... >> It depends on your timing budget. There is a thing called a DLL that >> phase locks the clock input to the destination synchronous clock input. >> It can also double the frequency. It has the ability to adjust the phase >> of the clock to null out the estimated first order delay of the IOB (note >> use of FDDRCPE) and PCB transport delay. > > I have used the DLL's but the FDDRCPE is not something I know anything > about? I did a quick search at www.xilinx.com keyword clock forward There are a lot of hits. I think you would be better off reading thru them. > > >> If more precision is needed for temperature / voltage compensation, then >> maybe the feedback approach is better. > > How do I make the feedback approach out of the IC? > > Do I just send out the clock to the IO-pin and then back to some other > IO-pin after having been "around" the A/D? Or any special pins for this > purpose? I did a quick search at www.xilinx.com keyword dcm feedback http://support.xilinx.com/xlnx/xil_ans_display.jspiLanguageID=1&iCountryID=1&getPagePath=14425 I got this link. There are a lot of hits. I think you would be better off reading thru them. > Which means that I should add a "clock-line" on the PCB from the > output-pin to the A/D. And from the same output just "draw" a line exactly > as long as the line to the A/D, but know to a pin on the FPGA (feedback)? I believe there are timing optimized feedback pins that you use. Please search Xilinx web for specifics. > > How should the clock be terminated on the board-layout (I must say - i > never made a PCB design - this will be my first - sounds silly, but we are > educated using already made development boards) You are in a sense lucky that you get a crack at fabbing a board while in school. It was a long time before I got involved with PCB's. After you are out of school for a while, people expect success even if you have not done something like it before. I no longer do PCB's, essentially because I have been able to get away with just doing the internals of the FPGA's :) > > I somehow don't see how these attempts make sure that the outside clock is > different from the same signal just inside the IC. > I guess that somehow you will need two clock-lines (one to the internal > and one for the external). I think it is better that you read the Xilinx app-notes on the subject rather than rely on my memory about them. > > > If you have time for making a simple "point-to-point" example of the > clock-net circuit (on the board that I should produce), please feel free > to do so. I haven't got much time up to christmas and I'm very new to this > High speed era of electronics, and somehow my bachelor starts tomorrow, so > the PCB should be finished quite soon so I can start on my project. There are a lot of issues like decoupling, via hole size, cross talk, PCB layer stack-up, board impedence, trace width, describing critical routes, etc. People claim that board simulation should be done with IBIS models, with back-annotated board parasitics nowadays. I do not have access to such tools, and feel reluctant to give you advice in this area. I had good success doing PCB's, but it was perhaps due to making the PCB very simple to place and route. I don't know what type of A/D you are using, but care should be used to keep the area "quiet" if you expect the LSB weights of the digitized outputs not to be flapping in the breeze "e.g. toggling with a DC signal as a reference". You really need to read the A/D applications notes to get a handle on this. My take on the clock is to convince yourself that the FDDRCPE approach will do the job. If so inclined, layout the board using the feedback approach with a series resistor in each clock leg as close to the source as possible. Make it symetrical, and if you have problems, you can depopulate the feedback resistor, and use the FDDRCPE approach. The trace stub to the depopulated resistor should be very short to minimize reflections. Maybe it will work. A back annotated board simulation would be nice for a confidence builder, but I am not the one to give advice on the particulars. My response on the above is guarded, because I have never seen what I just described as a recommended practice in any Xilinx document. The formula for the source-termination resistors is Rs = Zo - Rdrive*N Where : Rs = source termination resistor Zo = driven line impedence Rdrive = effective output resistance of driver N = number of driven lines > > >> I've never used the feedback method, but I suspect that I would research >> "Source Termination of Multiple Clock Lines" section 11.5 "High-Speed >> Digital Design A Handbook Of Black Magic" by Howard Johnson and Martin >> Graham where there is a short segment from the output clock pin to two >> series resistors (what I called the "T") to two lines of equal length and >> the loads at each end are balanced. > > Thanks (but the money as a student is very small, so maybe the library can > be used - i'll try so).. > > > > Thanks for all your help, and very sorry about my very bad english! Your English is pretty good! Good-Luck, -Newman > > > / PrebenArticle: 76364
For quite long i am coming across the concept of dynamic configuration. On papers it seems very attractive but i have never used it in my designs or i never felt the need of this feature. IMO it is just a theoritical concept or its a totaly gray area for me and i am not the right person to comment on it :-) rickman <spamgoeshere4@yahoo.com> wrote in message news:<41ACAFEF.D9E16284@yahoo.com>... > Andreas Schallenberg wrote: > > > > Hello! > > > > From the Virtex 4 documentation (Configuration Guide, > > Users Guide) I learned that this family can be > > configured during runtime in the granularity of single > > frames. The frames which have a fixed size for all > > members of this family. > > Additionally the documents state that there is a tiled > > placement of those frames. > > > > For Virtex II the frames started at the topmost CLB > > and ended at the bottom of the FPGA. This does not > > seem to be the case with Virtex 4 devices. > > > > This brings me to the question if it is now possible > > to configure a part of the FPGA which looks like > > e.g. a rectangle consisting of whole frames. > > Having neighbour frames at all four sides of > > that rectangle which are operating during that > > reconfiguration process. > > > > I'm having a picture of a matrix-style arrangement > > of all the frames in mind where I can select a set > > of them which are to be reconfigured. > > Unfortunately I didn't find any figure in the docs > > which gives me a hint on that. > > > > Could anyone comment on this? > > I expect you are opening a serious can of worms. The concept is great, > but the hard part is not the hardware, but the design software. Xilinx > has supported modular design for partial reconfiguration (MDPR) for > quite a while. But they have never represented that it works well and > in fact caution users to tread carefully and to not get too ambitious. > With the frame oriented MDPR being new, I would not expect it to be a > simple thing to use for quite a while. > > I am still waiting for MDPR support for the Spartan 3, even without the > rest of the chip running (which the Spartan 3 won't do). I just want to > make my designs truely modular at configuration time to match the > hardware configuration rather than to have to produce thousands of > different configurations. I am now being told they will get right on > that *after* they have done the Virtex 4 MDPR. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76365
untill and unless you are able to meet your design constraints (speed, power etc) with acceptable software/manual efforts, you should really not worry about the device utilization. I always try to fit the design in the smallest possible device. Sometimes i am able to use more than 90% LUT and sometimes quite lesser. everything depends on your design constraints "Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message news:<coi7rq$nce$1@sunnews.cern.ch>... > Should we ever get to that ? > I know typically A and X bother recommend 80-85% resource usage and so do a > lot of others > But besides having no provision for expansion of design and probably > extremely long p&r times, what are the other dangers of such a high resource > utilisation, if our clock is only 40 MHz. > Also what if we are using all 8 Rocket IOs in a device ?Article: 76366
> When you find out the answer please post a reply to the group. I >am facing the same problem. I am trying to configure the digilent >spartan-3 board using slave serial mode using a USB controller. The >same setup works for a spartan-II >but not for spartan-3. I already tried adding extra clocks. That did >not help. One trick in this area... If the chip you are trying to program is daisy chained to another chip, you can program the pair of them from one serial data stream. The first chip will eat the bits it needs, then pass the others. So set things up to pretend there is a chip down there. Program it too, and see if any bits come out. Compare when they start coming out with when you expect them to... I haven't had to do any work in this area for many years. In the old days, the data book description was all there after you had read it a few times. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76367
>I'm doing a pretty complex state machine, which is perfect for in >memory (blockRAM based) encoding. > >Before I go through and build my own state machine compiler out of >python hack-scripts or Excel macros, does someone already have such a >compiler available? There really should be a couple of good examples out there someplace, if nothing else, for times like this. I know of two general ways to do it: One is to think like a state machine. Write a program that iterates through each address, unpacks the address into current-state and input signals, sets up default output conditions... Then the body of the loop acts like the state machine - big case statement, inspecting the input flags, setting up next-state and output bits... Then the tail of the program packs up the output and writes out the ROM data. The other way is to think like microcode. For that, you want an assembler. This is basically encoding the current-state in the PC. The assembler can be really really simple, but it sure helps to have one to copy from. Branching is usually done by ORing/MUXing bits into the PC. I'm likely to get a hack-attack sometime. What's a good sample state machine that will run on the Spartan 3 starter kit? (Maybe blink LEDs or something) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76368
glen herrmannsfeldt wrote: > > rickman wrote: > > (snip of (1/2) C V**2 discussion) > > > This is a bit misleading and irrelevant. The fact that power is only > > dissipated in the resistance has nothing to do with the total amount of > > energy expended in charging and discharging a capacitor. Regardless of > > what value resistance, even if it is not constant, the energy drawn from > > the supply is the same as long as the capacitor is charged to the same > > voltage. The energy may be dissipated in the transistor or in the poly > > track or a metal track or the bond wire or the external pin or even in > > the wire from the power supply to the board. But add them all up and > > you will get the same value each time you charge a capacitor to a given > > voltage. > > > So the amount of power consumed is related to the frequency of > > transitions and the size of the capacitance. Whether you calculate it > > from the rate of the rising edges or both edges is not relevant, that > > just changes the constant that you use by a factor of 2. As the OP > > said, when you charge the cap from 0 volts to Vcc, half goes into the > > cap and half is wasted. But the total always comes from the PSU and is > > always the same amount. > > > You can't have a 0 to 1 transition without a 1 to 0 transition, so why > > is this even an issue? > > The issue is where the factor of two goes. > > As previously said, when charging half is dissipated, and half goes > into the capacitor. When discharging the rest is dissipated. > > For some designs it is easier to count total transitions than to > count rising or falling transitions. Otherwise, yes, it doesn't > matter as long as the 2 and 1/2 are in the right place. I don't know of any chip power calculations that require you to come up with the constant yourself. If the chip vendor gives you a constant and tells you to multiply by 1/2 or multiply by 2 or to just use the constant as is, then where is the problem? I think the OP was just confused about the variations in the formulae. It is just a matter of how you figure the constant. Normally the constant is measured rather than calculated, so you just need to use the formulae that you are given with the constant. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76369
Guenter Dannoritzer wrote: > > Krzysztof Szczepanski wrote: > > [snip] > > > > > > see if CCLK is present when the last byte was sent to fpga. > > > > krzysiek > > > > > > Do I have to add some CCLK cycles after I have sent the last data? I > recognized there are a bunch of new settings in the ISE6.3 in comparison > to the 4.1 which I used for the Spartan XL. > > The ATmega code applies the data, creates a rising edge for the CCLK and > in the next loop toggles the CCLK. > > I have to check whether there is a falling edge after the last data bit > is applied, at least it has a rising edge. > > The same code worked fine with the Spartan XL. Is there a differenc with > the Spartan 3? Have you monitored the INIT line? I belive it will go low if there is an error during configuration. If not, and DONE is not high, then likely you have not sent enough data or clocks or both. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76370
The CS8900 is a rather slow chip. I am running several applications at 60MHz
at which the chip does not operate well. Edit the class.ptf file and
increase the wait states and setup/hold times. Then add the component and
recompile.
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Uses_Tri_State_Data_Bus = "1";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "5"; ******* increase ?
Write_Wait_States = "5"; ******* increase ?
Setup_Time = "1"; ******* increase ?
Hold_Time = "1"; ******* increase ?
Is_Memory_Device = "0";
Date_Modified = "2001.10.9.10:51:51";
IRQ_Number = "--unknown--";
Base_Address = "--unknown--";
Tri_State_Data_Bus = "--unknown--";
}
Victor Schutte
http://www.zertec.co.za
----------------------------------------------------------------------------
--------------------------------------------------
"vladimir" <vboykov@yandex.ru> wrote in message
news:d6aed45c.0411301115.d80a628@posting.google.com...
> I've made a board with CS8900 for proto of NIOS Development kit board.
> It works very strange, I read internal registers and sometimes they
> was read correctly but in generaly incorrectly. Writing is correctly
> as seem to me.
> I'm using core of SOPC. Maybe someone gives me some advise.
> Thx.
Article: 76371Hal Murray wrote: >>I'm doing a pretty complex state machine, which is perfect for in >>memory (blockRAM based) encoding. >> >>Before I go through and build my own state machine compiler out of >>python hack-scripts or Excel macros, does someone already have such a >>compiler available? > > > There really should be a couple of good examples out there someplace, > if nothing else, for times like this. Or, the tools should support it directly ? :) > > I know of two general ways to do it: > > One is to think like a state machine. Write a program that iterates > through each address, unpacks the address into current-state and > input signals, sets up default output conditions... Then the body > of the loop acts like the state machine - big case statement, > inspecting the input flags, setting up next-state and output bits... > Then the tail of the program packs up the output and writes out > the ROM data. > > The other way is to think like microcode. For that, you want > an assembler. This is basically encoding the current-state in the > PC. The assembler can be really really simple, but it sure helps to have > one to copy from. Branching is usually done by ORing/MUXing bits into > the PC. > > I'm likely to get a hack-attack sometime. What's a good sample > state machine that will run on the Spartan 3 starter kit? (Maybe > blink LEDs or something) Traffic lights is a common one. You can use a Macro Assembler to create new opcodes, and so use the framework of a standard assembler for this task. I'm not sure if the assemblers that Xilinx include are this powerful, but they would be a natural choice. If you want to create your own variant assembler, then this is a good starting point : http://john.ccac.rwth-aachen.de:8000/as/ and I saw this recently, and thought it had to have a use, sometime... Your RAM state engine could be it ? http://www.pascalmacro.com/ The old registered PROMS were often used as state engines, and that's really what you have here, might be some old tools about that support this ? -jgArticle: 76372
Hi Austin, thanks for your quick answer! Since I am involved in an research project covering runtime reconfiguration this was just what I liked to read :) Greetings from northern Germany! AndreasArticle: 76373
Hi Ken et al: Just a couple more points on power equations. As some posters have indicated, the kCV^2f equations give you the right shape, and simple power models are tuned to make it work. One thing that works for the developers of power models is what goes up must come down -- the number of 0->1 and 1->0 transitions are equal. So if we can get one constant that represents the total switching current from supply to ground for a pair of transitions, we can then multiply that by the frequency of transition and the supply voltage to come up with a good stab at dynamic power over a set of transitions. It is worth noting that there are many factors that go into the current drawn during switching. In addition to the charging & discharging of capacitance, you also have the crow-bar or short-circuit current of CMOS logic. This current will depend on whether you have a rising or falling edge due to different rise- and fall-delays (and input slew rates) which depends on the exact ratioing of the logic and upstream drivers. But again, if you measure the power over a rising + falling edge and average it to get power per transition, this will work out. Provided the assumption that switching current is linear in activity holds, you can lump the short-circuit current in with the charge/discharge current. Really you're just making an equation P = kf -- there is no physical capacitance in the equation anymore. One ramification is that such a model for a driver + wire cannot be scaled with wirelength to obtain a power estimate for a different wire -- the short circuit component does not scale the same way as the capacitive component. At some point this P = kf model breaks down since rapidly switching nodes may not fully charge/discharge caps (or equivalently hit full rail-to-rail swing) since there is not enough time to do so. So "k" values obtained at low switching rates will tend to be pessimistic at high frequencies -- but that's probably good enough. You can make things arbitrarily complicated by considering crazy things like as power draw increases so too does voltage droop, so dynamic power per transition can actually drop... but these effects are subtle and the reality is that the biggest source of power error is lack of good estimates of switching activity per node! Another fun part of things is that there must be enough constants k for all the various resources and situations of interest. For example, the switching power of a gate can depend on the logic values seen at the various inputs (beyond just affecting whether the gate toggles). This "state-dependent" dynamic power is a detail that could be ignored by taking an average or representative case and hoping that no design repeatedly hits a corner case, or it can be modeled if it is deemed important. As discussed in some postings, you usually do not care where power is burned provided it is burnt on-chip -- view the circuit as a black box and you get Power = Current Drawn * Voltage. But if you take terminated I/O standards as an example, there is some complication since current supplied by on-chip rails is partially dissipated off chip. If you are designing your power supply, you want to know the current. If you are designing your cooling solution, you want to know the on-chip power dissipation. If you are looking at your system thermal management, total power dissipation is what you want. The bottom line is 1/2CV^2F just begins to scratch the surface of the wonderful world of power! Regards, Paul Leventis Altera Corp.Article: 76374
Hi! rickman wrote: > ... > I expect you are opening a serious can of worms. The concept is great, > but the hard part is not the hardware, but the design software. Xilinx > has supported modular design for partial reconfiguration (MDPR) for > quite a while. But they have never represented that it works well and > in fact caution users to tread carefully and to not get too ambitious. > With the frame oriented MDPR being new, I would not expect it to be a > simple thing to use for quite a while. > ... I am involved in a research project in a related area. The question here is how to design for such a target device, that means, to simplify the task for the designer. Of course we need reliable vendors tools to implement the designs but so far the situation was even worse: There was no device family on the market which 100% met our assumptions. From Austins answer I expect that this has changed now with the Virtex 4. > I am still waiting for MDPR support for the Spartan 3, even without the > rest of the chip running (which the Spartan 3 won't do). I just want to > make my designs truely modular at configuration time to match the > hardware configuration rather than to have to produce thousands of > different configurations. I am now being told they will get right on > that *after* they have done the Virtex 4 MDPR. > This is interesting. What general type of application are you doing? What are the parts you need to exchange? I'm interested in such things since we have a discussion on a somewhat regular basis wether reconfiguration (runtime or not) makes sense for what applications. Andreas
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