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Hi, Although I don't dispute some of the success stories of RocketIO, I would like to point out of the following: 1. The reference clock requirement for RocketIO is very tight (=expensive). Xilinx has been recommending an oscillator from EPSON with very low jitter. 2. If your application is less than or equal to 6.5Gb/s, do not use RocketIO. You will be paying a premium for a 10Gb/s transceiver. Altera and Lattice have better alternatives. 3. Lastly, just to make it clear: V2Pro uses an "old" transceiver, which has poor performance with jitter tolerance and transfer, although it has very good jitter generation V2ProX uses RocketIO 10Gb/s technology for backplanes is here, but there are a lot of challenges. One must utilize new backplane (PCB) material, new connectors, new test/measurement equipment, and be extermely careful with the board design since every little discontinuity will contribute to eye closure. Obviously reference backplanes/boards for 10Gb/s exist today, but the question is whether they are feasible and cost-effective for production. Just my two cents, Zhi Paul Smith <ptsmith@nospam.indiana.edu> wrote in message news:<cnl7em$9q3$1@hood.uits.indiana.edu>... > I'm considering the V2pro series for several projects. > > I've heard from someone with experience that there are problems with the > RocketIO when a lot of other things are happening on the chip. This is > thought to be a problem with the V2pro package. The evaluation boards > only implement the RocketIO without a lot of other things going on in > the part. > > Can anyone provide an example of a successful RocketIO implementation on > a real board that also has a lot of parallel IO and heavy use of > internal block RAM, etc? > > Paul Smith > Indian University PhysicsArticle: 76251
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:41A9EB9C.4194AE0D@yahoo.com... > > At the end, I prefer to instanciate such tings anyway. Much easier, > > predictable, portable. > > Why bother with semi-intelligent synthesis tools? > > I am not sure I understand. Instantiation is not portable at all... Why not? If you move to another target technology (lets say from brand A to X), you simply replace the RAMs and you are done. Especially when you are going to use brand specific features, like DLL, PLL DPS blocks etc. to get max. performance and also make it reasonable portable, you should try to isolate the brand specific blocks as much as possible to make it easier to replace them in another target. Right? > The reason that I prefer to infer logic is to increase portability. I > try to use block rams in ways that will work across vendors. So if I But for now its still a more or less big hassle with the tools, isnt it? Regards FalkArticle: 76252
"Falk Salewski" <salewski@informatik.rwth-aachen.de> schrieb im Newsbeitrag news:31038aF32l671U1@uni-berlin.de... > Hello everybody, > > I want to connect a Xilinx CoolrunnerII (XC2c256) to the CAN-Bus. To make it > easy I would like to use a ready to use CAN-bus driver chip (as much of the > protocol implemented as possible). Any suggestions? How many of the CPLD If you do so, use a uC with integrated CAN controller. But then you dont need a CPLD anymore. I dont see the point of using a CPLD with CAN. You CAN do it ;-) of cource. Regards FalkArticle: 76253
"Falk Salewski" <salewski@informatik.rwth-aachen.de> schrieb im Newsbeitrag news:310ihvF31ii5hU1@uni-berlin.de... > Thanks for the reply! > > I realized four 8bit counters in the CPLD and just want to send this > information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am not > thinking wether this is the optimal solution but if it is possible without > an aditional uC (Project at university) It CAN be doen this way, but -- it is more expensive. -- more complicated Regards FalkArticle: 76254
"Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag news:cofco1$b9n$05$1@news.t-online.com... > KISS > :) > format the MMC card, then copy download.bit to the card! thats it. simple as > that. > if once written can be overwritten without the need to format the card. Nice trick, but Iam afraid the CAN bus protocoll is a LITTLE bit more complex. Regards FalkArticle: 76255
Ben Jackson wrote: > In article <fc23bdfc.0411250242.2446ba92@posting.google.com>, > Nahum Barnea <nahum_barnea@yahoo.com> wrote: >>The problem is that the pullup is very slow (300 ns) and the host interrupt >>service routine is accessed again for nothing. > As someone who has worked on a lot of device drivers I can't say I've > ever seen a card that consistently produces double interrupts. I haven't > gone and measured INTx rise times either. > > The result seems plausible, though. Figure an ~8.2k pullup (that's Rtyp > for pullups in the PCI 2.1 spec, don't have X handy), 3 slots (at about > 5p each) each with a card (allowed 10p each) gives you 45p*8.2k is ~350ns. > OTOH, I've never seen a motherboard that was high-end enough to have > PCI-X 66 that didn't also use an IO APIC that allowed each INTx pin to > be routed individually, though. I remember that PCI's level sensitive interrupts are supposed to be an advantage over ISA's edge triggered interrupts. It might be that someone figured that once the interrupt register was reset it would take long enough to process that more than 300ns would have passed. As machines get faster, that isn't true anymore. -- glenArticle: 76256
Hi everyone, I just bought the Spartan3 starter board from the xilinx webshop (made by digilent). I have now checked the datasheet of the Spartan3, but I don't seem to get what clocks can be used? No information on duty-cycles or other info, is this of no importance? Rise-time/fall-time problems when attaching an A/D-converter to the same clock? I need to have the clock at a speed of up to 100MHz and driving both the A/D-converter and some GCLK input. I would like it programmable, so power-usage goes down when not sampling very fast signals. (Must be programmable "on the fly"). Btw. I'm pretty new to FPGA-development (educating), and I find some things rather strange, what is the CCLK (configuration clock) actually? The datasheet tells rather much about the CCLK, but I only seem to be able to find one clock on the board - the 50MHz GCLK0 attached clock. As far as I seem to understand the CCLK is used under programming from either flash or jtag! Thanks for helping Preben HolmArticle: 76257
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:311ckvF309jd8U8@uni-berlin.de... > > "Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag > news:cofco1$b9n$05$1@news.t-online.com... > > > KISS > > :) > > format the MMC card, then copy download.bit to the card! thats it. simple > as > > that. > > if once written can be overwritten without the need to format the card. > > Nice trick, but Iam afraid the CAN bus protocoll is a LITTLE bit more > complex. > > Regards > Falk LOL, yes just a little :) well only wanted to point out that 256 cells PLDs SHOULD be large enough for register init sequencer to initialize some CAN interface chip like MCP2515 anttiArticle: 76258
Mike Treseler wrote: > > >>>Being able to write to a common RAM from two processes is not > >>>supported in VHDL as far as I am aware. > > Sorry. I didn't read this carefully. > That is correct. Multiple processes can read > a ram signal, but only one can drive it. > My examples had one read-only process > and one read/write. > > See Jim Lewis's posting for the single > process version. I have not tested this, > but I will on Monday. In the single process > case, it should be possible to use a normal > variable for the RAM array. > > Note that design using a dual clock, dual write enable > ram is not complete until 1.synchronization > and 2.arbitration of writes to the same > location is worked out. That is why I > prefer the synchronous fifo approach. Yes, I agree for a FIFO the simpler read port, write port block ram is preferred and is all that is needed for a FIFO. But the OP was asking for a way to infer a dual port block ram with write on both ports. He was not asking about FIFOs. I think the FIFO was mentioned as a way to interface a separately clocked interface to a single clock, dual port block ram. I dug through all this a few weeks ago and both Xilinx and Altera say that there are no means to infer true dual port, dual clock block rams at this time. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76259
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:41A9EB9C.4194AE0D@yahoo.com... > > > > At the end, I prefer to instanciate such tings anyway. Much easier, > > > predictable, portable. > > > Why bother with semi-intelligent synthesis tools? > > > > I am not sure I understand. Instantiation is not portable at all... > > Why not? If you move to another target technology (lets say from brand A to > X), you simply replace the RAMs and you are done. > Especially when you are going to use brand specific features, like DLL, PLL > DPS blocks etc. to get max. performance and also make it reasonable > portable, you should try to isolate the brand specific blocks as much as > possible to make it easier to replace them in another target. Right? I guess we define portability differently. I have not considered that changes to the code are in the realm of "portable", but I guess there are "degrees" rather than it being an absolute. > > The reason that I prefer to infer logic is to increase portability. I > > try to use block rams in ways that will work across vendors. So if I > > But for now its still a more or less big hassle with the tools, isnt it? Only for a few features that are very different across vendors or things like these true dual port memories that are not inferred. I don't instantiate registers or logic even though they are slightly different between vendors. For example, I am optimizing my current design by telling the tool specifically how to map the logic to LUTs. But I am not instantiating any LUTs. I am breaking the logic into 4 input expressions and assigning a "keep" attribute to the signal. I expect that all tools supporting devices with 4 input LUTs will properly infer the LUTs that I want, so this is fully portable without code changes. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76260
>> I use xilinx shematic editor. >> On a wire i trying to place two I/O markers (same name ?), but the editor >> say : "Error : net 'xxx' is already a port with a polarity value 'output' > " >> >> I want do this for wiring facility on the uper level schema. >> >> >> Any solution ? > > think! > (sometimes helps) > > add a dummy buffer to split the wire before connecting to iopad/marker I had thought of that but i was not on that would not have perverse effects (i debute with FPGA). Thanks for your help. usmgnArticle: 76261
Hi there, I am a newbie and I do not know how to subscribe to the newsgroup listed in the following website. Could anybody let me know what is the server name for the newsgroup? I need it to fill the "Server Information" of my "Microsoft Outlook Newsreader"? http://jupiter.sun.csd.unb.ca/usenet/comp.html Thanks. JohnsonArticle: 76262
Falk Salewski wrote: > Thanks for the reply! > > I realized four 8bit counters in the CPLD and just want to send this > information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am not > thinking wether this is the optimal solution but if it is possible without > an aditional uC (Project at university) > I will have a look if I can store enough information in the CPLD for the > initialization of the SJA1000 chip... If you change the SJA1000, to the Microchip MCP25020, that has 8 I/O and on chip config registers so can 'wake up alive'. Simplest scheme to tranfer counter info, from a CPLD, would be a nibble-ram map, where you allocate 4 of the I/O as Address, and 4io as read-back nibble. A Write-Read CAN transaction, then Sends Address, and recovers one firmly identified nibble, and 16 nibbles can map 8 bytes of info. -jgArticle: 76263
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:41A9EA9E.2B26BFB9@yahoo.com... > > > Are you sure this is the output from MAP? My understanding is that it > > Yes, its the MAP report. > > > is the routing tool that will add route-thru LUTs, not the mapper. > > There would be no point to the mapper adding them since it would have no > > idea of where routing is a problem. > > Yes, but XST does some kind of secret/magic look ahead synthesis, so I guess > it does add the route-thru LUTs. I really do not understand why the synthesis tool would be adding route-thru LUTs. The tool can figure an estimated speed for the design by making assumptions about route speeds, but it would be pretty hard for it to make any intelligent estimates of routing congestion since that is very highly dependent on placement. This just makes no sense! > > I am thinking that perhaps your synthesis tool is adding them because of > > some mistaken option. Or maybe your design won't fit anyway!!! I just > > checked and the XC2S50 only has 864 LUTs ignoring the data sheet that > > It has 1536, 4 per CLB. I guess I was looking at the wrong row in the data sheet. But what about the synthesis options or attributes? I am adding "keep" attributes and found the tool added empty LUTs if I added the keep in more than one place in the heirarchy. Have you contacted Xilinx about this? With your speed constraints, I can't understand why the tools would be doing this at all, and certainly it should not be done by the synthesis tool! It may be perfectly routable without any of the route-thrus with your speed constraints. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76264
RobertP <r_p_u_d_l_i_k@poczta.onet.pl> wrote in message news:<coesj1$c50$1@news.onet.pl>... > For Virtex II: > > Vbatt - in some places in the datasheet and user manual it is advised to > leave it open if not used, in other it is advised to connect it to Vaux > or to ground. Maybe someone knows what is the right way to go? > (in previous project I left it open, no problems noticed). I've left these unconnected in multiple designs - no problems. > > DXN, DXP - can these pins be left open if not used? I leave these open with no problems. My understanding is that this is just a loose diode for temperature sensing. I've never checked if there is static voltage accumulated on them when left open. The only other reason to tie a pin off would be if it has an input buffer attached which could float to its threshold region - not the case for these pins.Article: 76265
"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message news:41ab792e$0$66401$14726298@news.sunsite.dk... > Hi everyone, > > I just bought the Spartan3 starter board from the xilinx webshop (made by > digilent). > > I have now checked the datasheet of the Spartan3, but I don't seem to get > what clocks can be used? No information on duty-cycles or other info, is > this of no importance? You can use the Digital Clock Manager (DCM) to adjust duty-cycle, phase and frequency with the 50MHz GCLK0 input you have. > Rise-time/fall-time problems when attaching an A/D-converter to the same > clock? I like point to point routing where possible. You may be able to use a clock forwarding scheme (via an FDDRCPE instance) to achieve this. There are also board deskewing schemes via feedback that may be suitable. I think the feedback scheme necessitates a 'T' in the board routing. > > I need to have the clock at a speed of up to 100MHz and driving both the > A/D-converter and some GCLK input. I would like it programmable, so > power-usage goes down when not sampling very fast signals. > (Must be programmable "on the fly"). Must is a strong word without an estimate of the power saving that are achievable by doing this. I think the MicroBlaze people want to do this, but are worried about handling/preventing transition glitches. I don't have the details off the top of my head. > > Btw. I'm pretty new to FPGA-development (educating), and I find some > things rather strange, what is the CCLK (configuration clock) actually? > The datasheet tells rather much about the CCLK, but I only seem to be able > to find one clock on the board - the 50MHz GCLK0 attached clock. > As far as I seem to understand the CCLK is used under programming from > either flash or jtag! JTAG typically uses the TCLK. CCLK is either an input or output clock depending on the configuration mode selected. Hope this helps. - Newman > > > Thanks for helping > Preben HolmArticle: 76266
"Johnson" <gpsabove@yahoo.com> wrote in message news:b1ac2406.0411291241.43e1f524@posting.google.com... > Hi there, > > I am a newbie and I do not know how to subscribe to the newsgroup > listed in the following website. Could anybody let me know what is the > server name for the newsgroup? I need it to fill the "Server > Information" of my "Microsoft Outlook Newsreader"? > > http://jupiter.sun.csd.unb.ca/usenet/comp.html > > Thanks. > > Johnson Your server information comes from your Internet Service Provider and is not a general internet value. If your ISP's webside doesn't contain a simple link to setting up the news server, call your tech support line. If you can't get the information or don't want to set up within Outlook's Newsreader, consider groups.google.com or - perhaps -groups.yahoo.com (you have a yahoo email account but I can't reach groups.yahoo.com from work).Article: 76267
mrand@my-deja.com (Marc Randolph) wrote in message news:<15881dde.0411290416.c1e473a@posting.google.com>... > rickman <spamgoeshere4@yahoo.com> wrote in message news:<41A9EA9E.2B26BFB9@yahoo.com>... - snip - > This is what peaked my interest in wanting to know more about > route-thru's. Regardless if he has 700+300 or 1000+300 (both of which > easily exceed 864), the route-thru's are over 30% of his design - that > strikes me as a huge percentage. Could this be caused by anything > except a larger number of timing domains that are poorly placed? > > Marc Another obvious question is how many slice Flip-flops are used. This is often the source of route-throughs. If you are making shift registers with slice flip-flops you can often reduce total resources using SRL16's which allows the use of a LUT that would otherwise be a route-through to implement a portion of the shift register chain. Another trick I've used in Virtex is to use TBUF's for mux functions when I run out of slices, but I don't think you have those in the 2e (map should tell you this). Generally, though, if your design uses more than about 70% of the LUTs in the part the mapper will fail to fit it in my experience.Article: 76268
Hi again! >>I just bought the Spartan3 starter board from the xilinx webshop (made by >>digilent). >> >>I have now checked the datasheet of the Spartan3, but I don't seem to get >>what clocks can be used? No information on duty-cycles or other info, is >>this of no importance? > > > You can use the Digital Clock Manager (DCM) to adjust duty-cycle, phase and > frequency with the 50MHz GCLK0 input you have. Yeah, but doesn't this cause delays by routing this to an output-port for driving the A/D? >>Rise-time/fall-time problems when attaching an A/D-converter to the same >>clock? > > > I like point to point routing where possible. You may be able to use a > clock > forwarding scheme (via an FDDRCPE instance) to achieve this. There are > also board deskewing schemes via feedback that may be suitable. I think > the feedback scheme necessitates a 'T' in the board routing. I'm stupid (or maybe I just haven't learned all this stuff yet) so please explain all these terms like "point to point routing", "clock forwarding scheme" and what do you mean by a "board deskewing schemes via feedback" and what is a 'T'? Thanks, PrebenArticle: 76269
"Gabor Szakacs" <gabor@alacron.com> schrieb im Newsbeitrag news:8a436ba2.0411291310.1d7f5e3f@posting.google.com... > Another obvious question is how many slice Flip-flops are used. This Its somewhere 60 %. So the FF/LUT ratio is close to 1. > is often the source of route-throughs. If you are making shift > registers with slice flip-flops you can often reduce total resources > using SRL16's which allows the use of a LUT that would otherwise > be a route-through to implement a portion of the shift register Thanks for the advice but I already had a look at this point. No improvement possible here. > chain. Another trick I've used in Virtex is to use TBUF's for > mux functions when I run out of slices, but I don't think you have > those in the 2e (map should tell you this). I just use a few, als no way to gain some ressources. > Generally, though, if your design uses more than about 70% of the > LUTs in the part the mapper will fail to fit it in my experience. Yep, this is what happens. Regards FalkArticle: 76270
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:41AB8B12.92308856@yahoo.com... > > Yes, but XST does some kind of secret/magic look ahead synthesis, so I guess > > it does add the route-thru LUTs. > > I really do not understand why the synthesis tool would be adding > route-thru LUTs. The tool can figure an estimated speed for the design Because its the Xilinx homemade synthesis tool. Maybe it is trying to avoid routing congestions in a very early stage ?? > by making assumptions about route speeds, but it would be pretty hard > for it to make any intelligent estimates of routing congestion since > that is very highly dependent on placement. > > This just makes no sense! 42. > Have you contacted Xilinx about this? With your speed constraints, I Not really. Since we have to use the 100k part anyway, its not urgent. But I would like to know for future designs. I will contact our FAE in the next days and post the result here. Stay tuned folks. > can't understand why the tools would be doing this at all, and certainly > it should not be done by the synthesis tool! It may be perfectly > routable without any of the route-thrus with your speed constraints. Exactly my point. Regards FalkArticle: 76271
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:41AB889B.C4161B36@yahoo.com... > I guess we define portability differently. I have not considered that > changes to the code are in the realm of "portable", but I guess there > are "degrees" rather than it being an absolute. > > But for now its still a more or less big hassle with the tools, isnt it? > > Only for a few features that are very different across vendors or things > like these true dual port memories that are not inferred. I don't > instantiate registers or logic even though they are slightly different > between vendors. For example, I am optimizing my current design by > telling the tool specifically how to map the logic to LUTs. But I am > not instantiating any LUTs. I am breaking the logic into 4 input > expressions and assigning a "keep" attribute to the signal. I expect > that all tools supporting devices with 4 input LUTs will properly infer > the LUTs that I want, so this is fully portable without code changes. Me too. Regards FalkArticle: 76272
Hi, Without undermining Xilinx's achievements in the 10Gb/s space, I would like to point out that using a 6.25Gb/s tranceiver is better than a 10Gb/s transceiver for a 6.25Gb/s application. There are several reasons: 1. A PLL designed for 622Mb/s to 10Gb/s has a wider tuning range than a PLL designed for up to 6.25Gb/s; hence, the performance (jitter) of a PLL designed up to 6.25Gb/s is better. 2. Using a 10Gb/s transceiver to run at 6.25Gb/s wastes area, power, and the customer has to pay a premium for a turbo-charged transceiver that he/she will not use at full-speed. 3. Moreover, your choice should not only be based on the transceiver. It is just part of the whole solution. FPGA core fabric should also be taken into account. Does the core fabric have enough LEs to process all the data coming in at 6.25Gb/s? A 10Gb/s transceiver may require more LEs, and if not used, will be wasted. These are just a few reasons to choose a 6.25Gb/s transceiver. BTW, there are 15+ FPGA/ASIC/IP/ASSP vendors who have 6.25Gb/s transceivers. This enables industry interoperability at 6.25Gb/s. It will be the sweet spot in the coming years. Aside from these comments, the RocketIO group at Xilinx did an outstanding job on the 10Gb/s transceiver. However, the market crash in 2001 has pushed the standarization of 10Gb/s for many many years. Therefore, it is not unreasonable to say that it was over-engineered and customers will have to pay for this innovation even though they may not need it. Zhi seannstifler69@hotmail.com (Stifler) wrote in message news:<bf780a06.0411221720.4284a56f@posting.google.com>... > I would not even consider using a high-speed I/O part unless I see it > working for real on a board. And with some characterization data to > back it up. That's because engineers have been burned too many times > for claims of serial I/O greatness only to be left without working > silicon when it comes times for the rubber to hit the road. > > Who cares about seeing info under NDA? 6.25 Gbps and above I/O is too > critical to count on some powerpoint presentation that claims great > I/O performance. > > You can get a Xilinx V2 Pro X today and verify for yourself if it > meets your needs in the lab. Real silicon operating at 10 Gbps on a > real board. Case closed with no decision for me unless I can see a > Stratix II running on a real board. > > With Xilinx you don't even need to have all the great equipment > yourself. You can go to a rocket lab and see for yourself. > > Also, I would much prefer to run a 10 Gbps device at 6.25 than a 6.25 > Gbps device at 6.25 Gbps. I'll take all the extra margin any day. > > > Ian & Hilda Dedic <news.nospam@dedics.co.uk> wrote in message news:<3099tbF2te2tsU1@uni-berlin.de>... > > Hi Austin > > > > Obviously there is more margin if you're not pushing the transceiver so > > hard, and being in the IC business I always take "real-soon-now" with a > > large pinch of salt. > > > > But in the timescales we're looking at it seems that there will be > > solutions from both the biggest FPGA vendors, which always helps when > > talking to customers who might exclusively use one or the other...:-) > > > > Cheers > > > > Ian > > > > Austin Lesea wrote: > > > > > Ian, > > > > > > There is a definite advantage to using a transceiver designed to work at > > > 10 Gbs at 6.25 Gbs -- there is a lot of margin! > > > > > > Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them > > > has to be just perfect, and pass the production BER test. We are in > > > production. At 10 Gbs. > > > > > > And, you can see (and get delivery of) the Pro-X transceivers (today at > > > the many RocketLab(tm) demo sites we have around the world). > > > > > > No "will", "more details under NDA", or any of that. Just product, > > > working, on the shelf, shipping NOW. > > > > > > Austin > > > > > > Ian Dedic wrote: > > > > > >> Thanks Dave -- it sounds like all our views agree here (see other > > >> mails in thread) that 5-6Gb/s as a next step avoids the issues which > > >> become difficult at 10-12Gb/s. Also given the number of channels > > >> available (from Altera and Xilinx) this will meet our requirement (up > > >> to about 100Gb/s total throughput). > > >> > > >> IanArticle: 76273
Falk Brunner wrote: > Hello everybody, > > Iam using ISE 6.2 with XST as synthesis tool. So far so good. But Now I have > a design with plenty of timing margin (just 36 MHz ;-) and the goal is to > fit it into a XC2S50E. > At the end, it doesnt. > So looking a little closer to the reports, I saw in the MAP report something > like this. > > blabla > 1000 LUTs used > 300 LUTs used a s route-thru. > > How is this to understand? I understand it this way, that XST (and the other > tools) use a LUT to feed data into a FF, but only 1 input is used, so the > LUT has no real function, maybe only a inversion. Is this how it works? > So how can I tell the software not to use LUTs as route thru, even if this > will decrease timing performance? I mean it is tecnically possible to use th > BY input to feed data into a FF. > > Regards > Falk These LUT route-thrus are inserted during the packing phase of the mapper which is why they are listed in the map report. The packer will normally only use a LUT to reach the FF data input if the corresponding BX/BY pin is already being used for some other purpose. BretArticle: 76274
I'm trying to figure out the best way to floorplan registered adder trees, such as those used in FIR filters. The (Xilinx) placer seems to have very little idea what to do with these. Even when I use an area constraint around the whole tree, the individual adders are not optimally placed, so the result is that my critical path is always between adders, and not the adder carry chain itself. I always have to manually place each adder in the tree to get good results. My questions are: 1. Is there a way to get adder trees to work without manual placement? 2. Is the best placement for an adder tree a tree structure (wide at one end and narrow at the other) or some more rectangular arrangement? -Kevin
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