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Hi Grégory, Sorry, I've no idea how to help you, but I just wondered if anyone outside of academe has used partial reconfiguration? Successfully? I briefly looked back through CAF, and most of the P_R posters I found had edu/ac addresses. Cheers, Syms. "Grégory Mermoud" <gregory.mermoud@epfl.ch> wrote in message news:41a4e4d6$1@epflnews.epfl.ch... <snip> > Grégory Mermoud > gregory.mermoud@epfl.ch > Master Student > Computer Science Departement > I&C Faculty > Swiss Federal Institute of Technology - LausanneArticle: 76101
Hi, I wondered if anyone knows if there are PCB packages which support hierarchical hardware design. For example, everytime I do an FPGA design, I use my favourite switching PSU circuit. The routing has been honed to perfection! Sadly, I can't easily just cut and paste this into my new design, as the Mental, sorry Mentor, PowerPCB tools complain about reference designations, net names and the like being different. What I want is to be able to instantiate my pre-placed and routed PSU into each new design. So, does anyone know of a tool which allows this? Our PowerPCB package sort of supports macro reuse, but in a horrible circuitous fashion. Cheers, Syms.Article: 76102
Hi Symon, Symon wrote: > I wondered if anyone knows if there are PCB packages which support > hierarchical hardware design. For example, everytime I do an FPGA design, I > use my favourite switching PSU circuit. The routing has been honed to > perfection! Sadly, I can't easily just cut and paste this into my new > design, as the Mental, sorry Mentor, PowerPCB tools complain about reference > designations, net names and the like being different. What I want is to be > able to instantiate my pre-placed and routed PSU into each new design. So, > does anyone know of a tool which allows this? Our PowerPCB package sort of > supports macro reuse, but in a horrible circuitous fashion. I believe Altium (DXP2004) does this - you can certainly do heirarchical schematic design, defining module-level ports and so on, then drop it into a top-level design. I'm pretty sure it handles pre placed/routed PCB "macros" as well - I'm sure an Altium sales person would be happy to tell you all about it! :) Rgds JohnArticle: 76103
Thanks for that John. Is that the Protel product you're referring to? From the website it looks as though this could do what I want. Cheers, Syms. "John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:newscache$n1ep7i$fqe$1@lbox.itee.uq.edu.au... > Hi Symon, > > I believe Altium (DXP2004) does this - you can certainly do heirarchical > schematic design, defining module-level ports and so on, then drop it > into a top-level design. I'm pretty sure it handles pre placed/routed > PCB "macros" as well - I'm sure an Altium sales person would be happy to > tell you all about it! :) > > Rgds > > JohnArticle: 76104
Varun, Altera's benchmarking methodology is documented at http://www.altera.com/products/devices/performance/benchmark/per-benchmarkmeth.html. In particular I'd suggest looking at the benchmarking methodology white paper at http://www.altera.com/literature/wp/wpfpgapbm.pdf which articulates our exact methodology. I believe that this clear description of a benchmarking methodology is unique. Altera benchmarking is done by our engineering group which uses these results to optimize new architectures, to improve place and route algorithms, and to improve synthesis results. Marketing uses these results in a peripheral manner (i.e. they are not run by marketing and they are not run for marketing). If you have further interest, Altera will be hosting a net seminar describing this benchmarking methodology, specifying the results, and explaining architectural differences that facilitate the significant performance advantages. Details on the net seminar are found at http://www.altera.com/education/net_seminars/current/ns-s2perf.html [note - there will be marketing participation in this net seminar]. Altera has been shipping Stratix II devices since June and began shipping the Stratix II 2S130 device (biggest FPGA ever shipped by 50%) last week. The comment on unavailability is misguided. Dave Greenfield Altera Marketing > > Varun Jindal wrote: > > > hello all, > > > > i have been reading a lot about performance comparisons between > > leading FPGA chip makers on hteir web-sites. both claim improvement > > upon the other by metrics of 20 - 40 % .... though none has ever > > described what exactly was compared. > > > > are there resources available on the net, which compare different > > architecture in detail (and also impartially) .. !! ?? > > > > -- Varun.Article: 76105
Hi Syms, Symon wrote: > Thanks for that John. Is that the Protel product you're referring to? From > the website it looks as though this could do what I want. > Cheers, Syms. Yep - that's the one. DXP is the suite of tools that includes Protel, and various CAM products and so on. Cheers, JohnArticle: 76106
Symon wrote: > Hi, > I wondered if anyone knows if there are PCB packages which support > hierarchical hardware design. For example, everytime I do an FPGA design, I > use my favourite switching PSU circuit. The routing has been honed to > perfection! Sadly, I can't easily just cut and paste this into my new > design, as the Mental, sorry Mentor, PowerPCB tools complain about reference > designations, net names and the like being different. What I want is to be > able to instantiate my pre-placed and routed PSU into each new design. So, > does anyone know of a tool which allows this? Our PowerPCB package sort of > supports macro reuse, but in a horrible circuitous fashion. > Cheers, Syms. You need the Physical Design reuse (PDR) option for PowerPCB to do this in the most seamless way. However, you should also be able to also do a cut/paste, and then use Syncronise with Schematic, to re-align the Net names/RefDes on any copied block ? PADS will alert to deltas/changes, but does not stop you proceeding. The syncronise option allows the deltas to be cleaned up, but you do also need to watch mounting holed/fidicuals etc. -jgArticle: 76107
I recently upgraded to ISE 6, and have recompiled a project. However, the loader reports Validating chain... Boundary-scan chain validated successfully. ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000000000000000 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000000101000100000000010010011 Am I missing something obvious? I expect others have had this problem and it will take just seconds to fix. TIA, KArticle: 76108
Hello, all I am now doing a program to test my module design and I use ISE6.2 under windows XP. I synthesize the top-level design and modules with XST(under windows mode). When synthesizing top-level file, I selected "Add I/O buffer", and deselecting it when synthesizing modules file. Then I use command mode to implement them. It looks o.k. when I do " ngdbuild –modular initial…." And "ngdbuild –modular module –active module …." But when I use map command to this active module A, the following message appears. ---Writing file test_map.ngm… ---Waring : Line numbe 0: Found and unexpected XMODULE_CELLTYPE property on frag T_b1. … … …-(The same warings to all top-level ports) ---Runing directed packing… ---Running delay-based LUT packing… Running related packing… ---FATAL_ERROR : Ncd : nc_isetfactory_imp.c:738:1.22.4.1 – Active module interfaces are missing. Process will terminate. And there is the same problem when I doing the previous xapp290 example under the same situation. Another question is I add some constrains attribute in VHDL code (i.e. attribute iob : string; attribute iob of LED_A_out : signal is "true";) but it dose nothing. Could anyone give me some ideas about these problems? Thank you very much. gray_iArticle: 76109
As already discussed by Glen, WHAT and HOW the comparison is done is of core importance. Again, Dave, the link provided by you does highlight the methodology of benchmarking. Discussion regarding the use of sub-optimal benchmark designs to generate mis-leading comparisons is very true. But, having discussed this, there is no opinion on the issue of incorrect/incomplete choice of performance ratio. What if the comparison parameters are biased against an architecture. Even if non-disclosure of benchmark designs is valid, what about the performance ratio !? My question is what is the equation of your performance ratio!? Why is it so difficult to disclose this equation. A user holds a right to know what importance you have given to each parameter in order to calculate the performance ratio. i will give you a small example, due to limited funding, the choice of which FPGA device to purchase is heavily governed by the size of chip which can implement my design. But i am not aware whether you have taken this point into account while calculating teh performance ratio. In case you have, what weightable has been given to it !? All this is still black box to me. How do you or anybody else for that matter expect me to rely on the comparison results provided on the web-sites.!? Can different people have different reasons for buying a FPGA device!? How can 'chip size'-based decisions or 'chip performance'-based decisions be made from one set of performance ratio!? -- Varun.Article: 76110
Hi Varun, I think that the simple answer is that a purchase for a single design cannot be made purely off of general benchmarking results. You need to evaluate the performance of our chips (and any others) for your design and its requirements. And you need to factor in other chip features and performance parameters, the price you can get from your distributor/fae, the packaging choices, device availability, etc. Let's step away from questions of benchmarking validity, averaging methods and such. In the end, we get a spread of results. If your design happens to be one of the designs that experiences equivalent performance (or say you are the data point at the extreme left in Figure 1 at http://www.altera.com/products/devices/performance/high_performance/per-high_performance_fpga.html), then our 39% means nothing to you. All benchmarking results do is provide you with some guidance of what to expect. Based on our Stratix II benchmarking results, you can expect a chip that will likely outperform Virtex-4. This could mean that you hit your performance target in one and not the other. Or it could mean that you can buy a cheaper speed grade in Stratix II but need a more expensive speed grade in Virtex-4. Similarly, you can expect Cyclone II to be ~60% faster than Spartan-3. If you only have time to try one chip, I think it should be Stratix II or Cyclone/Cyclone II (depending on your needs), given the average results we see. If you have time to try two chips, I still think you should just buy ours ;-) -- but I will grudgingly accept that you will probably try out what Xilinx has to offer too :-) Does that mean Stratix II is the right chip for you? Not necessarily.Article: 76111
Hi Austin, I believe Dave has addressed the overall question on benchmarking methodology. I'd like to address a few specific benchmarking questions in your posting (which I believe are addressed in the links David provided). > What speed grades were compared (e.g. their fastest with our mid-grade)? We always produce at a comparison of the fastest speed grades available in the software, and we will sometimes publish other comparisons with explicit indications of speed grade. Our philosophy is that if a speed grade is not in software, users can't design to it, and thus it is not real. When a new speed grade becomes available (from either vendor), we re-measure our benchmarks. Note that sometimes speed grades appear in the software that are difficult/impossible to actually get from the vendor. We do not factor this into our benchmarking results. This is can be an advantage for competitors, since we haven't had a speed grade availability issue that I know of. > What were the settings of the synthesis tools (e.g. their default vs our > default -- we default for speed of synthesis, theirs for a compromise of > performance)? We do apples to apples comparisons. We usually use a 3rd party synthesis tool, same version, same settings for both chips. If we are trying to compare architecture speeds, we push synthesis for speed (for both architectures). We also sometimes publish results using the available integrated sythesis. This is particularly relevant in the low-cost market where CAD tool costs can be a factor. If we are comparing architectural speed, we select the settings (for both tools) that yield the best speed results. We do not cripple either tool, and we go as far as running many experiments to try to determine the best settings for our competitors' tools. > What effort was made to use device specific features (e.g. theirs a lot, > ours a little)? We make a fairly signficant effort. We do not go as far as rearchitecting the design to be specifically optimised for a chip. We try to standardize the HDL between the target architectures, with exception of "cores" such as explicitly instantiated memories, multiplier/accumulator blocks, PLL/DCMs, etc. Does this mean for a given design we've extracted the most we can? I'd say no, since that would require an enormous engineering effort on (typically) poorly documented designs (all we get is the HDL, and sometimes it's been anonymized). But our benchmark set comprises designs that were originally targeted to our chips of current and past generations, competitors chips, ASICs, vanilla HDL, etc, so there will probably be headroom left in both architectures under comparison. > What choice of device was made (e.g. their only one choice, versus our > three options to best fit: LX for logic, SX for DSP, and FX for networking > and comms)? We select the smallest device that fits the design, since we believe that our customers would likely do so as well. The whole Virtex-4 alphabet soup issue is new. But since only LX is available, its moot for now -- no point comparing to a family that is not available. As for FX, that's a non-issue as we're talking about core fabric performance. Stratix GX and your FX parts offer additional hard IP that will factor into some customer's decisions, and probably in a way that no amount of benchmarking will be able to quantify. > The "speed superiority" claims appeared three days after we announced the > availability of three V4 parts as engineering samples.....compared to > their unavailability. Hey it ain't fun when your foundry can't supply the > parts to you, is it? I'm not quite sure which three days you are referring to, but the primary reason for the timing of our release was availablity of ISE support for Virtex-4. We can't benchmark against a chip that doesn't exist in the software. If we knew we had a 39% performance advantage earlier, do you think we would have sat on it? I'm not sure what its like when a foundry can't supply us parts Austin, so I can't feel your pain. Sorry. We have one fabulous fab partner in TSMC, and it's the only one we need. Regards, Paul Leventis Altera Corp.Article: 76112
Hello! I want to revitalise a question at was asked in 2001, because I hope something changed during the time. How can a AT49LV001 flash by programmed through a XC9536XL CPLD and its JTAG-connector with really low cost? All address, data and control pins are connected to the CPLD, so ISP via JTAG should be possible.I'm sure there are lots of tools available at this time for programming, but still I don't want to pay >10k USD. Does anyone know if it's possible to program at flash with JAMPLAYER sw from altera? How much effort would it be to implement flash algorithms? regards, WolfgangArticle: 76113
Much appreciated, Jim. It turns out we have a seat with the PDR option, I'll look into it a bit more thoroughly. Thanks again mate, Syms. "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:41bpd.7378$3U4.211289@news02.tsnz.net... > > You need the Physical Design reuse (PDR) option for PowerPCB to do this > in the most seamless way. > However, you should also be able to also do a cut/paste, and then use > Syncronise with Schematic, to re-align the Net names/RefDes on any > copied block ? > PADS will alert to deltas/changes, but does not stop you proceeding. > The syncronise option allows the deltas to be cleaned up, but you > do also need to watch mounting holed/fidicuals etc. > -jgArticle: 76114
"Symon" <symon_brewer@hotmail.com> wrote in message news:30kd25F31qiehU1@uni-berlin.de... > Hi, > I wondered if anyone knows if there are PCB packages which support > hierarchical hardware design. For example, everytime I do an FPGA design, > I > use my favourite switching PSU circuit. The routing has been honed to > perfection! Sadly, I can't easily just cut and paste this into my new > design, as the Mental, sorry Mentor, PowerPCB tools complain about > reference > designations, net names and the like being different. What I want is to be > able to instantiate my pre-placed and routed PSU into each new design. So, > does anyone know of a tool which allows this? Our PowerPCB package sort of > supports macro reuse, but in a horrible circuitous fashion. The Pulsonix software I use lets you do this: http://www.pulsonix.com Download the demo and try it. It will import PADS schematics and PCBs. If you want to try it properly you can request a 30 day license. LeonArticle: 76115
Ben Twijnstra <btwijnstra@gmail.com> wrote in message news:<nZMod.8063$_u6.2552@amsnews02.chello.com>... > > If you are able to select the signal before compilation, either in the block > diagram editor or in the node finder, you can tell Quartus to "Implement as > output of Logic Cell" by using the Assignment Editor. > > This will make sure that the signal is always present in the design (unless > it's unnecessary and optimized away). > > If you use VHDL or Verilog, look at the "keep" synthesis attribute, which > does the same thing, but from your source code instead of from the > Assignment Editor. > > Good luck with these clues. > > Best regards, > > > > Ben Hi Ben, Thanks for your clues, but the signal I need is optimized away. Let me explain my problem in detail: We have a memory in our design and the inputs of this memory are optimized away. And my job is to get the exact delay of the memory! Have you got another clue? Or idea? Thanks EmrahArticle: 76116
Hi. I design a xilinx virtex2pro with pci-x interface that is connected to a server PC. I am using the PCI interrupt. Whenever an interrupt is completed the my fpga drive it to 'Z' and the pullup on the mother board pulls it to '1'. The problem is that the pullup is very slow (300 ns) and the host interrupt service routine is accessed again for nothing. I am using IOB type PCIX. Am I doing something wrong ? ThankX, NahumArticle: 76117
Nahum Barnea wrote: > Hi. > > I design a xilinx virtex2pro with pci-x interface that is connected to a server > PC. I am using the PCI interrupt. Whenever an interrupt is completed the my > fpga drive it to 'Z' and the pullup on the mother board pulls it to '1'. > > The problem is that the pullup is very slow (300 ns) and the host interrupt > service routine is accessed again for nothing. > > I am using IOB type PCIX. > > Am I doing something wrong ? This is normal and to be expected. One approach to dealing with this is to drive the interrupt high for one clock before going Hi-Z. Note that this isn't per the pci spec which says open-drain, using an IOB with low current capability should avoid problems when the interrupt line is shared with another device which is driving low.Article: 76118
"System Alchemist" <dotter@_nospam_btconnect.com> wrote > One approach to dealing with this is to drive the interrupt high > for one clock before going Hi-Z. > Note that this isn't per the pci spec which says open-drain, using > an IOB with low current capability should avoid problems when the > interrupt line is shared with another device which is driving low. Or drive it Hi as you are floating it.Article: 76119
hello all, For a hobbyist purpose, I want to drive an LCD display (320x240) with a CPLD or FPGA in a standalone device (weather station). I've already played with FPGA and VHDL for some projects but I was never involved in the hardware part of such projects. The CPLD would have to read data (bitmap picture) from a dual port RAM and write it to the 4 bit data input of the LCD controller (+control lines, clock...). On the other side of the RAM, a microcontroller will update sometimes the content of the picture to be displayed. I would like to know how to estimate the number of gate needed for the project in order to buy the cheapest CPLD that fits the number of gate. Do I need first to design the VHDL part and synthetize to know the number of gate and then choose the CPLD? I do not really understand the difference between CPLD and FPGA and what is better for me. For a CPLD, the configuration is non volatile and in the FPGA it is volatile so a reconfiguration is needed on each start (via configuration EEPROM or JTAG programming) but the FPGA is much more powerfull. Correct? Is a CPLD enough for my project? I'm turning around Xilinx XC9536 which seems to be very often used nowadays, is it a good choice for this project? Many thanks by advance.Article: 76120
Hi! I solved my problem about bus macro. In fact, my macro was not well placed since I choosed INST "busRegToInc" LOC = "TBUF_R25C17.1" ; INST "busIncToReg" LOC = "TBUF_R26C17.1" ; Using xdl, I noticed that Xilinx uses TBUF number 0 and not 1 in their macro. Then, I wrote INST "busRegToInc" LOC = "TBUF_R25C17.0" ; INST "busIncToReg" LOC = "TBUF_R26C17.0" ; and my macro got well placed and shaped. The problem is now that my design doesn't work, despite of the fact that it seems completely correct in FPGA editor. I don't understand why, but I will keep you informed. Thank you, Grégory P.S. : my assistant has successufully achieved such design, but it seems that he has never encountered such problem. Symon wrote: > Hi Grégory, > Sorry, I've no idea how to help you, but I just wondered if anyone outside > of academe has used partial reconfiguration? Successfully? I briefly looked > back through CAF, and most of the P_R posters I found had edu/ac addresses. > Cheers, Syms. > > "Grégory Mermoud" <gregory.mermoud@epfl.ch> wrote in message > news:41a4e4d6$1@epflnews.epfl.ch... > <snip> > >>Grégory Mermoud >>gregory.mermoud@epfl.ch >>Master Student >>Computer Science Departement >>I&C Faculty >>Swiss Federal Institute of Technology - Lausanne > > >Article: 76121
Mike Treseler wrote: > Hamish Moffatt wrote: > >> Err.. That's functionally correct, but how does it help to get >> Synplify to use the reset inputs for synchronous reset? > > > It doesn't. > > My point was to demonstrate a way to > integrate an external asynchronous reset > with your existing code in a vendor portable way. > > Is this a question of a design not fitting > or unease about wasting gates? It's suspected wasted gates leading to (a) poor placement, and (b) more logic levels than necessary, and therefore difficulty meeting timing. I'm running 200 MHz (+ jitter) in a 2V6000-6 so I don't have many picoseconds to waste. That along with a very wide data bus is making placement rather touchy. HamishArticle: 76122
"Mouarf" <mouarf@chezmoi.fr> wrote in message news:41a5ca7c$0$17590$636a15ce@news.free.fr... > hello all, > > For a hobbyist purpose, I want to drive an LCD display (320x240) with a > CPLD or FPGA in a standalone device (weather station). I've already played > with FPGA and VHDL for some projects but I was never involved in the > hardware part of such projects. > > The CPLD would have to read data (bitmap picture) from a dual port RAM and > write it to the 4 bit data input of the LCD controller (+control lines, > clock...). On the other side of the RAM, a microcontroller will update > sometimes the content of the picture to be displayed. > > I would like to know how to estimate the number of gate needed for the > project in order to buy the cheapest CPLD that fits the number of gate. > > Do I need first to design the VHDL part and synthetize to know the number > of gate and then choose the CPLD? That is my preference. IMHO, CPLD's can be a real pain if one underestimates the size and or fan-in. Also, the implementation is more sensitive to the pin out selected. As a point of reference (FPGA), a monochrome EL display (160x120) used 486/4992 (9%) LE ACEX1K EP1K100FI256-2 40,960/49152 (83%) memory bits (two frames in DP RAM) -- not a particularly good LE to DP RAM ratio. > > I do not really understand the difference between CPLD and FPGA and what > is better for me. Some CPLD's have really low power. Most FPGA's have on board memory that can be conveniently utilized. A uP with dual port ram, and logic could be packaged in a single FPGA chip to drive the LCD display. I've seen some FPGA evaluation boards that claim to do this. The Xilinx website has some boards and links to other vendors that sell this stuff. You may be able to get some other data points from this in order to estimate the amount of logic needed. > > For a CPLD, the configuration is non volatile and in the FPGA it is > volatile so a reconfiguration is needed on each start (via configuration > EEPROM or JTAG programming) but the FPGA is much more powerfull. Correct? There was some talk about someone having an FPGA with configuration flash on board the FPGA, but I can neither confirm nor deny this assertion. An FPGA can be configured from non-volatile storage via a uP too. > > Is a CPLD enough for my project? I'm turning around Xilinx XC9536 which > seems to be very often used nowadays, is it a good choice for this > project? > I would estimate the amount of Dual Port RAM bits required to see if I could get rid of the discrete dual port RAM by using resources in the FPGA. If a suitable FPGA can be found with a good DP RAM to LE ratio, I would further research the cost in an attempt to justify using an FPGA, which I think would be more fun :,) -- Newman > > Many thanks by advance. > > >Article: 76123
Hi all! I wonder if I can use LUT to control LI, LT, RI and RT in Xilinx Bus Macro for partial reconfiguration. I use Spartan2 and ISE6.3.01i SP2. Has someone ever experienced any problems by using this method ? GrégoryArticle: 76124
when simulating the code below with modelsim SE 5.8d (and above), the
CD, Sync, and WaitCnt don't get the correct values under reset ('1',
'0', and 1 respectively). instead, they get 'U','U', and 0.
when running the simulation with Modelsim SE 5.8 they do get the
correct values.
-------------------------------------------------
signal CD :std_logic;
signal Sync :std_logic;
signal WaitCnt : integer range 0 to ..;
begin
reset <= '0', '1' after 2 us;
clk <= not clk after 8 ns; --initialized as '1'.
process(reset,clk)
begin
if reset='0' then
CD <= '1';
Sync <= '0';
WaitCnt <= 1;
elsif clk'event and clk ='1' then
:
:
end if;
end process;
---------------------------------------------------
did anyone encounter a similiar problem?
thank you very much
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