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Thanks for the reply! I realized four 8bit counters in the CPLD and just want to send this information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am not thinking wether this is the optimal solution but if it is possible without an aditional uC (Project at university) I will have a look if I can store enough information in the CPLD for the initialization of the SJA1000 chip... FalkS. "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:mBCqd.13010$3U4.254093@news02.tsnz.net... > Falk Salewski wrote: >> Thank you very much for your reply. >> >> However what I am looking for is how difficult is it to connect a CPLD to >> a CAN-controller chip like the SJA1000 >> http://www-eu3.semiconductors.com/pip/SJA1000.html >> and how many of the CPLD resources it takes to initialize/communicate >> with this CAN-controller. > > You'll need to setup the registers [either a rom in the CPLD, or > a Serial EE holding the init values, to BUS], and then be able to poll > messages, and manage TX packets (which come from where ?). > > All of these are not CPLD-centric tasks, so why not use a small uC > instead - or even better, choose a uC with CAN on chip ? > If you have the XC2C256 there already, needing > 128 MC for other tasks, > then you could use a small portion, for SPI-SJA1000 bridge, and then use a > small SPI uC for the CAN manager/init. > Philips LPC9xx or Silicon Labs C8051F33x series would do this, in tiny > 11-20pin packages. > -jg > >Article: 76226
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:coest7$o8j$1@lnx107.hrz.tu-darmstadt.de... > Falk Salewski <salewski@informatik.rwth-aachen.de> wrote: > : Thank you very much for your reply. > > : However what I am looking for is how difficult is it to connect a CPLD > to a > : CAN-controller chip like the SJA1000 > : http://www-eu3.semiconductors.com/pip/SJA1000.html > : and how many of the CPLD resources it takes to initialize/communicate > : with this CAN-controller. > > : bye > : Falk > > : "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im > : Newsbeitrag news:coensd$mh6$1@lnx107.hrz.tu-darmstadt.de... > : > Falk Salewski <salewski@informatik.rwth-aachen.de> wrote: > ... > > Can communication needs some protocoll stack. Your question seems to be > what > implementing this stack in hardware needs with regards to hardware > resources. > > My guess is that the 2c256 is too small for that task. > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- I thought the protocoll stack is already implemented in the SJA1000 and I just have to write to some kind of send buffer and read from a receive buffer... FalkArticle: 76227
do more homework! there are lots of boards with less than 1KUSD value xilinx/digilent s3-200 is $99 new board with S3-1500 is coming (not announced) I would gess sub $249 price for that xess has s3-1000 board for $199 and there are quite manu more in around $199 price range some v2-1000+ boards are also relativly cheap the price sometimes includes xilinx EDK in case of -"MB" bundled packages from avnet and memec but lots of high end boards cost $5000+ with no bundled at all Antti you want to build a society? that would do what? interesting... "kubik" <jackgroups@interfree.it> wrote in message news:pan.2004.11.29.13.03.45.427048@interfree.it... > Forgive me for these stupid questions, but i'm a beginner in this field. > > I was searching on the web a Xilinx virtex2 board for doing my first > experience. > I' ve found many boards on the xilinx on line store ( the > HW-AFX family ) on the Avnet site ( ADS family ) and so on. But the prices > of these boards are all more then one thousand of dollars. > > Are these prices so high because with them is sold the design software too ? > > If so, and if i want to build a system in fpga i must buy many of these > boards, i don't need many copies of the design software. Are there others > expensive boards that need only to be programmed and cost much less? > > What shoud be the orientative value for the cost for piece that i must > sustain if i want to build a society that sells designs in FPGA? > > Thanks in advance >Article: 76228
"Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message news:310ihvF31ii5hU1@uni-berlin.de... > Thanks for the reply! > > I realized four 8bit counters in the CPLD and just want to send this > information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am not > thinking wether this is the optimal solution but if it is possible without > an aditional uC (Project at university) > I will have a look if I can store enough information in the CPLD for the > initialization of the SJA1000 chip... http://ww1.microchip.com/downloads/en/DeviceDoc/21801b.pdf Quiz: How many macrocells is needed to initialize MMC card (nonSPI mode) and configure and FPGA from bitstream file on the card? Answer: 20 PLD macrocells! http://www.openchip.org/bootx/xmsmmc.html 256 PLD cells can be alot. depends how they are used :) but I would not go with SJA1000+PLD (unless restricted to those component by definition) waste of time and human resources AnttiArticle: 76229
On Mon, 29 Nov 2004 13:28:28 +0100, "Antti Lukats" <antti@case2000.com> wrote: >you want to build a society? that would do what? interesting... > > >"kubik" <jackgroups@interfree.it> wrote in message >news:pan.2004.11.29.13.03.45.427048@interfree.it... >> What shoud be the orientative value for the cost for piece that i must >> sustain if i want to build a society that sells designs in FPGA? maybe he means a company.Article: 76230
Forgive me for these stupid questions, but i'm a beginner in this field. I was searching on the web a Xilinx virtex2 board for doing my first experience. I' ve found many boards on the xilinx on line store ( the HW-AFX family ) on the Avnet site ( ADS family ) and so on. But the prices of these boards are all more then one thousand of dollars. Are these prices so high because with them is sold the design software too ? If so, and if i want to build a system in fpga i must buy many of these boards, i don't need many copies of the design software. Are there others expensive boards that need only to be programmed and cost much less? What shoud be the orientative value for the cost for piece that i must sustain if i want to build a society that sells designs in FPGA? Thanks in advanceArticle: 76231
Hi Antti,
Antti Lukats wrote:
>"Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message
>news:310ihvF31ii5hU1@uni-berlin.de...
>
>
>>Thanks for the reply!
>>
>>I realized four 8bit counters in the CPLD and just want to send this
>>information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am
>>
>>
>not
>
>
>>thinking wether this is the optimal solution but if it is possible without
>>an aditional uC (Project at university)
>>I will have a look if I can store enough information in the CPLD for the
>>initialization of the SJA1000 chip...
>>
>>
>
>http://ww1.microchip.com/downloads/en/DeviceDoc/21801b.pdf
>
>Quiz: How many macrocells is needed to initialize MMC card (nonSPI mode) and
>configure and FPGA from bitstream file on the card?
>
>Answer: 20 PLD macrocells!
>
>http://www.openchip.org/bootx/xmsmmc.html
>
>
No file system support (I assume) and no partition support. How do you
write the bitstream as row data ?
cheers,
Aurash
>256 PLD cells can be alot. depends how they are used :)
>
>but I would not go with SJA1000+PLD (unless restricted to those component by
>definition) waste of time and human resources
>
>Antti
>
>
>
>
--
__
/
Article: 76232On Mon, 29 Nov 2004 12:52:05 +0000, mk wrote: > On Mon, 29 Nov 2004 13:28:28 +0100, "Antti Lukats" > <antti@case2000.com> wrote: > >>you want to build a society? that would do what? interesting... >> >> >>"kubik" <jackgroups@interfree.it> wrote in message >>news:pan.2004.11.29.13.03.45.427048@interfree.it... >>> What shoud be the orientative value for the cost for piece that i must >>> sustain if i want to build a society that sells designs in FPGA? > > maybe he means a company. Yes, i'm not american, but i think i mean a company. I' m looking with interest at the new market of "domotic" and the embedded systems that it could require Thanks at allArticle: 76233
"Aurelian Lazarut" <aurash@xilinx.com> wrote in message news:cofagb$m5k1@cliff.xsj.xilinx.com... > Hi Antti, > > Antti Lukats wrote: > > >"Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message > >news:310ihvF31ii5hU1@uni-berlin.de... > > > > > >>Thanks for the reply! > >> > >>I realized four 8bit counters in the CPLD and just want to send this > >>information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am > >> > >> > >not > > > > > >>thinking wether this is the optimal solution but if it is possible without > >>an aditional uC (Project at university) > >>I will have a look if I can store enough information in the CPLD for the > >>initialization of the SJA1000 chip... > >> > >> > > > >http://ww1.microchip.com/downloads/en/DeviceDoc/21801b.pdf > > > >Quiz: How many macrocells is needed to initialize MMC card (nonSPI mode) and > >configure and FPGA from bitstream file on the card? > > > >Answer: 20 PLD macrocells! > > > >http://www.openchip.org/bootx/xmsmmc.html > > > > > No file system support (I assume) and no partition support. How do you > write the bitstream as row data ? > cheers, > Aurash KISS :) format the MMC card, then copy download.bit to the card! thats it. simple as that. if once written can be overwritten without the need to format the card. Of course I do have some utilities to write directly to the card (in hidden area) too, but those arent even necessary AnttiArticle: 76234
You will find Virtex-II based boards relatively expensive. For cost it is better to look at Spartan-3 based boards. Spartan-3 architecture is derived from Virtex-II. We have offerings in this field as do many of our competitors. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "kubik" <jackgroups@interfree.it> wrote in message news:pan.2004.11.29.13.03.45.427048@interfree.it... > Forgive me for these stupid questions, but i'm a beginner in this field. > > I was searching on the web a Xilinx virtex2 board for doing my first > experience. > I' ve found many boards on the xilinx on line store ( the > HW-AFX family ) on the Avnet site ( ADS family ) and so on. But the prices > of these boards are all more then one thousand of dollars. > > Are these prices so high because with them is sold the design software too ? > > If so, and if i want to build a system in fpga i must buy many of these > boards, i don't need many copies of the design software. Are there others > expensive boards that need only to be programmed and cost much less? > > What shoud be the orientative value for the cost for piece that i must > sustain if i want to build a society that sells designs in FPGA? > > Thanks in advance >Article: 76235
Hello, I have a pll clock multiplier block that multiplies and divides an input clock and uses that clock signal for my FPGA system clock. How can I bring that output to an external pin for debug monitoring as well as use it internally? I tried connecting an output port to the clock multiplier output (also connected to other internal blocks) and I get the following error, when attempting to synthesis the design: Error: ClockLock PLL altclklock0:inst10|altclklock:altclklock_component|outclock0 must feed only one CLKLK_OUT pin Any ideas why and how to fix it? Thanks SalmanArticle: 76236
I have a couple of questions about the board layout of the spartan3 and platform flash. In the spartan-3 family guide there is a schematic for programming the spartan-3 from a platform flash on page 33. To put the spartan 3 in master serial mode you need M0-M2 (mode pins) as 000. In theory the spartan-3 and platform flash should step through the flow chart of boot up mode. Do I need to then change the mode pins, or is it okay to leave them hardwired to GND ? My second question is about JTAG. In order to make this in-system programmable I would of course like to use my JTAG port just like on the sp-3 starter kit. Do I need to do anything in particular to the mode pins, M0-M2, at this point or does JTAG override them so that I can then program up the platform flash just like I do with the starter kit? I had always thought the JTAG would be dominant (using IMPACT) but this isn't something I want to leave to chance, as prototype boards aren't cheap when you aren't doing them yourself. Thanks very much for your time.Article: 76237
"Jon Dohnson" <jon_dohnson@nothanks.usenet.only.com> wrote in message news:pan.2004.11.29.16.58.04.220000@nothanks.usenet.only.com... > I have a couple of questions about the board layout of the spartan3 and > platform flash. In the spartan-3 family guide there is a schematic for > programming the spartan-3 from a platform flash on page 33. To put the > spartan 3 in master serial mode you need M0-M2 (mode pins) as 000. In > theory the spartan-3 and platform flash should step through the flow chart > of boot up mode. > > Do I need to then change the mode pins, or is it okay to leave them > hardwired to GND ? OK > My second question is about JTAG. In order to make this in-system > programmable I would of course like to use my JTAG port just like on the > sp-3 starter kit. Do I need to do anything in particular to the mode pins, > M0-M2, at this point or does JTAG override them so that I can then > program up the platform flash just like I do with the starter kit? nothing special > I had always thought the JTAG would be dominant (using IMPACT) but this > isn't something I want to leave to chance, as prototype boards aren't > cheap when you aren't doing them yourself. it is. JTAG is useable no matter the mode pins, just make sure the PROG is not pulled up correctly, things like that on good advice, look at xilinx, there is an appnote how todo read access to platform flash after config, if that woule be desired you need on more additional connection to platform flash anttiArticle: 76238
I am trying to program my FPGA board without a Xilinx Parallel Cable. I would like to able to program the FPGA using the Serial Cable and Serial Port (DB9). Also I am not sure if I understand JTAG correctly, but is there a way to implement the JTAG interface on serial cable, the way the Xilinx XChecker Cable does. Isnt JTAG simply a translationof voltage logic levels. I was not able to find a schematic for the Xchecker cable. Any help is very much appreciated. Thanks Yaju Nagaonkar ==================================================== y a j u at B Y U edu Electrical and Computer Engineering Department Brigham Young University Provo Utah USA 84604Article: 76239
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0411250721.5b1e7f98@posting.google.com... > "Fred" <Fred@nospam.com> wrote in message news:<41a49114$0$1067$db0fefd9@news.zen.co.uk>... > > I see that Micron SDRAMs are claimed to support Concurrent auto precharge. > > Is this a common feature amongst SDRAMs? > > > > I'm using a sample of a ICSI SDRAM at present and this feature isn't > > mentioned in the data sheet. Is it safe for me to presume it doesn't > > support Concurrent auto precharge? > > > > I am trying to write and read blocks of 4 words and don't really want to > > extend the buffering to accommodate an 8 word burst! > > Hi, > > do you mean that you want to precharge for example bank A while > still accessing bank B ? > > Rgds > André Sorry for the delay in replying but yes it is where I can have 2 banks active and use auto precharge to close a bank. The select another row, in the bank just closed, to give a near continuous data flow.Article: 76240
System : Win XP (Fresh install) Read the user's guide multiple times to ensure correct jumper settings. The board is configured for SelectMAP programming mode JP8 shunted The board is configed in master-serial mode for PROM programming of SPARTAN bridge : JP9 open Other jumpers have default values, triple checked The S1 and S2 dipswitches : S1 : all on off ... CF card loads position 0 normally S2 : all on off as described in user guide inserted the card into 32bit PCI slot for normal PCI use at present time booted PC followed driver installation instructions, windriver6.inf installed by => wdreg -inf "location of inf file" install then copied avpci...inf file to WINDOWS/INF directory then rebooted. Accessed PCI Utility : no board connected Tried to manually install the avpci driver, still nothing detected ... Checked PCI slots, and no extra entries in ID list of device wether or not the device is connected to the bus Has somebody experienced this problem ? Could it be the PROM not longer contains the config file for the bridge or should i look for answers in another direction Thx in advance, PaoloArticle: 76241
I use xilinx shematic editor. On a wire i trying to place two I/O markers (same name ?), but the editor say : "Error : net 'xxx' is already a port with a polarity value 'output' " I want do this for wiring facility on the uper level schema. Any solution ? Thanks UsmgnArticle: 76242
"usmgn" <ANTISPAMMMusmgn@yahoo.fr> wrote in message news:41ab63e3$0$16333$8fcfb975@news.wanadoo.fr... > > I use xilinx shematic editor. > On a wire i trying to place two I/O markers (same name ?), but the editor > say : "Error : net 'xxx' is already a port with a polarity value 'output' " > > I want do this for wiring facility on the uper level schema. > > > Any solution ? think! (sometimes helps) add a dummy buffer to split the wire before connecting to iopad/marker anttiArticle: 76243
"Subroto Datta" <sdatta@altera.com> wrote in message news:<Artqd.1427$Hq6.1260@newssvr31.news.prodigy.com>... > Hi Cristian, > Just a note that the dedicated multipliers in Cyclone-II, Stratix and > Stratix-II (i.e. Embedded multipliers or DSP blocks) can implement full > width 18x18 signed *and* unsigned multipliers. Unsigned multipliers are > supported explicitly, and are not just a special case of signed multipliers. > So for the sample code you gave, it will be implemented in one 18x18 > dedicated multiplier. > > Hope this helps. > > Subroto Datta > Altera Corp. > Subroto, thanks for your information. Actually, when I was doing my tests I was comparing the new Lattice ECP with the Spartan III. I realized that the same code needed 1 18x18 multiplier in the Lattice, whereas it needed 3 18x18 multipliers in the Spartan III. That was the reason of my question. The sysDSP blocks in the ECP are very similar to the DSP blocks available in the Stratix, but in a very low cost device. http://www.latticesemi.com/products/fpga/ecp/sysdsp.cfm thanks again, crisArticle: 76244
Thanks a lot, Dave, I am reading it ... Johnson gpsabove@yahoo.com (Johnson) wrote in message news:<b1ac2406.0411282101.2509ec30@posting.google.com>... > I am a newbie of FPGA. > > Could anhybody please provide me some sample designs of FPGA, better > for Compact Flash peripheral design. We will start a project by using > FPGA for a Compact flash gps receiver. > > Thanks in advance. > > JohnsonArticle: 76245
"Simon Peacock" <nowhere@to.be.found> schrieb im Newsbeitrag news:41a9a25e$1@news.actrix.gen.nz... > basically.. yes... > The LUT as a router is the same as a via on a PCB. annoying to have.. but > imposable to live without If there would'nt be the BY input . . . > How to fit the design... > first... try the optimisations others suggest... Been there done that. Suprisingly the option "Keep hierachy = NO" in XST makes it possible to merge more unrelated logic. Hmmm?? > second.. check with marketing ... it may not be worth the effort when it > would fit comfortably in a 100e Is already in the pipe an will be most probably the final solution, since there are more functions waiting for beeing implemented. > third.. use a better tool ($$$) Hmm, but this is not the answer at all. And its not sooo smart to solve any problem by throhging a lot of money at it. > forth... use as many built in routines as you can find. ??? You mean optimized Xilinx Macros? > fifth.. hand place and route the design (see second above) Not worth the trouble and doesnt answer the core question. Is there a way to tell XST (the synthesizer) and MAP, that we have plenty of time and want maximum density. The usuall settings Speed/Area change nothing here. My design achives 10 ns cycle time, where I have 27 ns. > sixth.. your 30% over budget so throw it away and start again with a better > algorithm... or see second above. This is MY design, so it already has the best algorithm available ;-)) > seventh... just throw functionality out until it fits No option. Everything is needed. No possibilities of time sharing/MUXing. > eighth.. ask your Xilinx reseller to give you a better price on 100e Already in progress. Regards FalkArticle: 76246
Falk Salewski wrote: > Thanks for the reply! > > I realized four 8bit counters in the CPLD and just want to send this > information (4Byte) via the CAN-Bus, lets say all 100ms. Right know I am not > thinking wether this is the optimal solution but if it is possible without > an aditional uC (Project at university) > I will have a look if I can store enough information in the CPLD for the > initialization of the SJA1000 chip... First, find some working SJA1000 software, in any uC family will do. Search also for the 82C200, which is the older sibling of the SJA1000. Philips will probably have some 80C51 examples. Then, look to move that function into the CPLD. To give your tutor some real numbers, assemble JUST the code for init & simple Echo, and print the LINK MAP, to show how much RAM and CODE space is needed. [eg it might be 5 bytes of RAM, and 275 Bytes of Code] I think I saw recently a CAN controller [SJA1000 like], that could as an option, 'wake up' in simple peripheral mode, IIRC using a Serial EE to config. That would be another 'no code' alternative. -jg > > FalkS. > > "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag > news:mBCqd.13010$3U4.254093@news02.tsnz.net... > >>Falk Salewski wrote: >> >>>Thank you very much for your reply. >>> >>>However what I am looking for is how difficult is it to connect a CPLD to >>>a CAN-controller chip like the SJA1000 >>>http://www-eu3.semiconductors.com/pip/SJA1000.html >>>and how many of the CPLD resources it takes to initialize/communicate >>>with this CAN-controller. >> >> You'll need to setup the registers [either a rom in the CPLD, or >>a Serial EE holding the init values, to BUS], and then be able to poll >>messages, and manage TX packets (which come from where ?). >> >> All of these are not CPLD-centric tasks, so why not use a small uC >>instead - or even better, choose a uC with CAN on chip ? >> If you have the XC2C256 there already, needing > 128 MC for other tasks, >>then you could use a small portion, for SPI-SJA1000 bridge, and then use a >>small SPI uC for the CAN manager/init. >> Philips LPC9xx or Silicon Labs C8051F33x series would do this, in tiny >>11-20pin packages. >> -jg >> >> > > >Article: 76247
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:41A9EA9E.2B26BFB9@yahoo.com... > Are you sure this is the output from MAP? My understanding is that it Yes, its the MAP report. > is the routing tool that will add route-thru LUTs, not the mapper. > There would be no point to the mapper adding them since it would have no > idea of where routing is a problem. Yes, but XST does some kind of secret/magic look ahead synthesis, so I guess it does add the route-thru LUTs. > I am thinking that perhaps your synthesis tool is adding them because of > some mistaken option. Or maybe your design won't fit anyway!!! I just > checked and the XC2S50 only has 864 LUTs ignoring the data sheet that It has 1536, 4 per CLB. > says 972. Does your design require 1000 *plus* 300 for routing or just > 700? 1000 for logic PLUS 300 for route-through, according to the MAP report. This somewhere 85 %. But it does not fit since slice usage is then somewhere 110 %. > If it is the router that is adding the routing LUTs, then your design > just won't route in the XC2S50 unless you perhaps try floorplanning the > design to ease routing congestion. Its not a routing problem, the design flow gets killed after MAP (overmapped) Regards FalkArticle: 76248
"Marc Randolph" <mrand@my-deja.com> schrieb im Newsbeitrag news:15881dde.0411290416.c1e473a@posting.google.com... > I'd be real suprised if the synthesis tool did it, since you can syth > a design using larger or smaller size targets than what you finally > create a bit-stream for. Yes, but maybe using the LUT as route through gives better maaping/placement/routing possibilities and in the end better timing. So XST add them (I guess). But it would be nice if there is a switch for "slow" designs. > This is what peaked my interest in wanting to know more about > route-thru's. Regardless if he has 700+300 or 1000+300 (both of which > easily exceed 864), the route-thru's are over 30% of his design - that Its 1526 LUTs in the XC2S50E. > strikes me as a huge percentage. Could this be caused by anything > except a larger number of timing domains that are poorly placed? Its a one clock design (36 MHz). It achives 10ns cycle time, but I can spent 27ns. Regards FalkArticle: 76249
"Mike Treseler" <mike_treseler@comcast.net> schrieb im Newsbeitrag news:4pqdnQS0_PFGfDTcRVn-sg@comcast.com... > Falk Brunner wrote: > > > At the end, I prefer to instanciate such tings anyway. Much easier, > > predictable, portable. > > Why bother with semi-intelligent synthesis tools? > > Sorry to waste your time. > I suppose vhdl synthesis is a little off-topic for this group. Smily missing?? ;-)) There was no offence intended. But it sounded to me like a little bit academic discussion. Regards Falk
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