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Naimesh wrote: > Hello, > > I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i. > > I am observing a illogical problem. > > All my flip flops are negative edge triggered but some how even if the > edge on the clock comes cpld doesnt recognize it. I think you might want to use the global clock pin(s) as your clock input. VAX< 9000 > > So I made a simple flip flop where at Power On Reset I am clearing it > and at the edge of the clock I am setting it to 1. > > Even then I was not able to see that test signal as 1. > > When I converted the test flip flop from -ve edge to +ve edge I was > getting proper result. > > After that I converted all other signals to +ve edge triggered and I > observed same problem as was in -ve edge trigerred.even in test Flip > Flop. > > Again I converted just the Test flip flop to -ve edge and kept all > other +ve edge and again proper results. > > Now I want to buffer the clock as I think this is a problem of loading > of clock. > > but as if I write > > Clock1 <= Clock; > > xst removes it so how can I tell xst to not remove that. > any other suggestions for problem I m observing. > > Thank u > NaimeshArticle: 75451
I am using global clock pin only. Thank youArticle: 75452
On 5 Nov 2004 08:00:23 -0800, conphiloso@hotmail.com (john) wrote: >Hello, > >I am trying to interface a USB receiver chip with the FPGA. The USB >chip can only allow unidirection >communications. it just outputs eight bit of data at 12 MHz at each >rising edge of the USB clock in brust >mode. The scheme I used is simple but my State machine is getting lost >and screwing up the count of the counter. some times It works >sometimes it does not work! >I am using the counter to generate addressess for the Dual port RAM. >My VHDL comlplier also ignoring the intialization >of the signal Flag1 and I do not know why? The FPGA is running at the >clock frequency of 60MHZ. > >Thanks very much. >Regards >john So how exactly are you moving the USB data available status and the data from the 12MHz clock domain to the 60MHz clock domain ???? Maybe go read this: http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm Including the links at the end of the article. Philip Philip Freidin FliptronicsArticle: 75453
Stefan Frank <stefrank@gmx.net> wrote in message news:<418893d8$0$23487$4d4ebb8e@read.news.de.uu.net>... > On 11/03/2004 08:52 AM, geoerge wrote: > > I am trying to get a floating license for Actel Designer. When I enter .... > have you tried lmhostid from the flexlm utilities? If that does not > work, try the MAC address of your ethernet card. > > The hostid command doesn't seem to be appropriate in all cases. > > HTH & HAND, > Steff Thanks Steff, I got the registration done. It is strange, but I got a 9 digit one from lmhostid. However, I prepended 000 to that and got it registered. BTW, looks like mac address (from ifconfig) is same as the lmhostid value. Thanks again, GeorgeArticle: 75454
Hello All, I have questions regarding a project i am currently working on. I have been assigned to develop an SRAM interface to be able to Read/Write an SDRAM (Micron 168-pin).And the SRAM should maintain its own functonality i.e. the SRAM itself can be read/written. Also, whatever data is read from SDRAM should be stroed in SRAM. I am following the XAPP134 article and another free IP from www.cmosexod.com I know that my SRAM should be able to pass Commands (read/write) to SDRAM Controller which inturn will trigger the SDRAM for reads/writes values. my questions are: (1) Should my SRAM jsut issue Read/Write command to SDRAM Controller and then it will do the rest i.e. Read/write from SDRAM. (2) Should'nt the SRAM output (Q) be a bi-directional since this pin Q has to be used for SRAM read and also for SDRAM read? Thanx, waiting..Article: 75455
> > ERROR:Xst:764 - C:/code.vhd line 22: No default binding for component: > > <SRL16E_1>. Generic <INIT> is not on the entity. > > ERROR: XST failed > > > > If I simply change SRL16E_1 to SRL16E the code passes through with no > > warnings or errors. Anyone know what is going on? <snip> > The error occurs because SRL16E is in the library > but SRL16E_1 is not. But the SRL16E_1 component declaration follows directly after the SRL16E component declaration in unisim_VCOMP.vhd and they are both primitives. The declarations are identical except for the difference in name. I can't understand why XST is happy with SRL16E in my most recently posted code but complains when I switch to SRL16E_1 by spitting out the above error message? Eric.Article: 75456
Hi, friends,
I wrote a module to access the compactflash in true ide mode (pio0), the
status register. the clock frequence is 50Mhz, every time I try to read, I
got 0x54 from the cf_data, I think I should get 0x50 if it works right. What
is wrong with me??
Thanks a lot!
following is the code:
wire cf_oe=1'b0;
wire cf_reg=1'b1;
wire cf_we=1'b1;
wire cf_dasp=1'b1;
parameter pio0_t1=5'd5,
pio0_t2=5'd22,
pio0_t3=5'd23,
pio0_t4=5'd30;
reg [4:0] cfcnt;
always @(posedge clk or negedge reset)
if (~reset)
cfcnt<=5'b0;
else if (en)
cfcnt<=5'b0;
else if (cfcnt!=5'b11111)
cfcnt<=cfcnt+1;
else
cfcnt<=cfcnt;
reg cf_ior;
always @(posedge clk or negedge reset)
if (~reset)
cf_ior<=1'b1;
else if (cfcnt==pio0_t1)
cf_ior<=1'b0;
else if (cfcnt==pio0_t2)
cf_ior<=1'b1;
else
cf_ior<=cf_ior;
wire cf_iow=1'b1;
// 10111, the status/command register
wire cf_cs1=1'b1;
wire cf_cs0=1'b0;
wire cf_da2=1'b1;
wire cf_da1=1'b1;
wire cf_da0=1'b1;
reg [7:0] cf_data;
always @(posedge clk or negedge reset)
if (~reset)
cf_data<=8'b0;
else if (cfcnt==pio0_t2)
cf_data<=cf_dd;
else
cf_data<=cf_data;
Article: 75457
Håkon L wrote:
> Hi,
> When I have a synchronous interface running on a clock coming from a PAD on
> a Xilinx FPGA, I know there is a good way to constraint input/output timing
> using OFFSET constraints here.
>
> But,
> How do you specify output timing if you have DATA clocked out by an internal
> clock (generated by a FF) and also forward this clock to the PAD?
>
>
> FF
> Data +---+
> ----------|D Q|--------------------| |Data PAD
> | |
> .---|C |How do I know clock data relationship?
> | +---+
> Internal |
> -------------------------------------| |Clock PAD
> clock
Howdy Håkon,
The short answer is that I'm not aware of a _good_ way to specify it
the way that you have described. In fact, some older (but not very
old!) FPGAs chips won't even let you output the clock to a general
purpose I/O pad, regardless if you're using it for a synchronous
interface or not!
The typical way to do what you want is to use a DDR FF, if the device
supports it. If it doesn't support it, you might be able to use a 2x
internal clock to clock out a toggling 0/1 pattern from the I/O FF.
If none of those are options, the longer answer is that you may not have
to specify it the way you are thinking of. What clock rate and how much
timing margin do you have? In the past, I have used a MAX_DELAY
constraint on the clock net itself, and if memory serves, this actually
appeared to make sure the tools routed the clock to the I/O pad with a
reasonable amount of prop delay. It won't be 500ps or anything, but it
kept the delay in the low single digits.
Have fun,
Marc
Article: 75458Hi, I am new to FPGA design. I am now need to make a switch to control the signals from PC LPT to a character LCD module. Right now I am using Altera UP1 demo board for verfication which has 1 MAX CPLD and 1 FLEX fpga. And I write a simple code just like D_out <= D_in using VHDL, like a wiring from input signals to outputs. I check the LPT signals by connecting to LCD module directly and it shows all the information I want. But After I connecting the FPGA interfance, it never works. I checked the pins again and again, but no use. Then I changed the device from MAX to FLEX, but it didn't work, neither.... I also have another code which is used to initial LCD module and show some words, after I programed, both devices work fine. I don't know what's wrong inside and I even change the code by using schmatics, still not working. Is there anything I can do to improve this ? Thank you! BR, Johnson LeeArticle: 75459
Hello,
I've quickly written AHDL code ( out = !in ), assigned out to the led
pin and in to the on-off switch pin. Then I downloaded that code into
Cyclone using ByteblasterII. Quartus reported that everything gone fine.
BUT...
....all the leds started to blink (including the error led). It seemed like
my design was being loaded then configuration controller realized that
something was not right and was reprogramming Cyclone again and again and
again and.....
Does anybody know how to successfully program that Cyclone chip on the
Nios Development Board?
I'll be very gratefull for any help.
thanks in advance!
Marcin Olak
Article: 75460
Hello,
> I'll be very gratefull for any help.
A simple design THAT WORKS for Quartus 4 Web Edition would be also all
right : )
greetings!
Marcin Olak
Article: 75461Hi, Marcin I got the same problem like you yesterday. What I do is: From the quartus menu assignments->device->device & pin Options ->Unused Pins The default is As outputs, driving ground, change it to "As inputs, tri-stated", then recompile the design. If u still have problem, please mail me, I may send u a simple design.Article: 75462
Johnson Lee wrote: > Hi, > I am new to FPGA design. > I am now need to make a switch to control the signals from PC LPT to a > character LCD module. > Right now I am using Altera UP1 demo board for verfication which has > 1 MAX CPLD and 1 FLEX fpga. And I write a simple code just like > D_out <= D_in > using VHDL, like a wiring from input signals to outputs. > > I check the LPT signals by connecting to LCD module directly and it > shows all the information I want. But After I connecting the FPGA > interfance, it never works. > I checked the pins again and again, but no use. Then I changed the > device from MAX to FLEX, but it didn't work, neither.... > > I also have another code which is used to initial LCD module and > show some words, after I programed, both devices work fine. > I don't know what's wrong inside and I even change the code by using > schmatics, still not working. > Is there anything I can do to improve this ? To summarise :- Test 1: PC LPT-->FPGA-->LCD. FAILS. Test 2: PC LPT-->CPLD-->LCD. FAILS. Test 3: PC LPT-->LCD. No CPLD. No FPGA. Works OK. Test 4: CPLD-->LCD. No PC. Works OK Test 5: FPGA-->LCD. No PC. Works OK. Is this correct? Did you check _all_ outputs using an oscilloscope in tests 1+2? Was the LCD connected to the same outputs in 1+2 as it was in 4+5? Are you using the Altera Quartus development environment? Could you post sample Quartus archive (.QAR) files?Article: 75463
hi all, how to force DC to use a specific cell for specific part of the code in verilog module. Power compiler is implementing my logic with XL gate (low power, high delay) from TSMC library. I want to use X2 or X4 flop for only that part of the code in the total verilog module. How can I do that?? By the way I cant instantiate the gate from cell library since the clock is gated. (becoz I want power compiler to insert clockgate circuitry in the clock pin of the flop.) Regards whizkidArticle: 75464
Hi Michelle, I think Cyclone PLL needs xtal input > 15 MHz, also cannot lock on frequencies below 15 MHz.... Also think that 10 MHz for a PC EPP port is rather high, try 1 MHz to start with. You must synchronise PC EPP signals (strobes, wait ) with the Internal Cyclone signals, use the standard 2 flip-flop synchronisers for this. regards Ron Proveniers www.info-trade.nl "Michele Bergo" <michelebergo@libero.it> schreef in bericht news:%ORid.18871$Ni.665341@twister1.libero.it... > I want to realize an EPP interface using Altera FPGA Cyclone (read and write > operation) but I have some synchronization problems. I want to sample datas > from a 4 bits chip, storing them in a ZBT SRAM memory (Flow trought) and > later acquiring them by parallel port. the chip works at 10MHz but the pll > on board can't divide input clock of 20MHz for 2. How can I divide the > frequency? > thanks. Does anyone do something like that? > >Article: 75465
Eric wrote:
>>>ERROR:Xst:764 - C:/code.vhd line 22: No default binding for component:
>>><SRL16E_1>. Generic <INIT> is not on the entity.
>>>ERROR: XST failed
> But the SRL16E_1 component declaration follows directly after the
> SRL16E component declaration in unisim_VCOMP.vhd and they are both
> primitives.
Then you must have a mismatch between the component
and the instance. Maybe SRL16E_1 requires an "INIT"
generic while SRL16E does not.
-- Mike Treseler
Article: 75466On 6 Nov 2004 06:42:00 -0800, whizkid@gamebox.net (whizkid) wrote: >hi all, >how to force DC to use a specific cell for specific part of the code >in verilog module. Power compiler is implementing my logic with XL >gate (low power, high delay) from TSMC library. I want to use X2 or X4 >flop for only that part of the code in the total verilog module. How >can I do that?? > >By the way I cant instantiate the gate from cell library since the >clock is gated. >(becoz I want power compiler to insert clockgate circuitry in the >clock pin of the flop.) >Regards >whizkid I am not sure why you think instantiating the flop will prevent the PC to do clock-gating. But if that's really the case, you can always upsize the flop after the PC is done before you start the CTS. Write out the verilog, change the flop and continue with the rest of the flow. I still think you should be able to instantiate the flop only (the same type as the PC generates but with a higher drive) and let PC handle the rest.Article: 75467
anttonhu@gmail.com (tripledirrble) wrote in message news:<632786ca.0411051459.77f7326@posting.google.com>... > I have a board using XC2VP20-6FF896c and two xc18v04 proms, seems Jtag > have problem as: > 1) Whenever there is a free-runnimg clock, the Jtag config fails. > when the free-runnimg clock is turned off, config successfully. I've seen EMI cause JTAG to fail configuration when using "flying leads". Making the leads shorter and twisting a ground with each signal helped. > 2) Maseter seral mode never work, check cclk, it is alway there. Did the old Virtex E configuration have only one PROM. IIRC, in a multi-PROM configuration setting, the one electrically closest to the FPGA is the mcs file with a '0' in the name. > > Could clock interference affect Jtag configuration? but I use the > same design with virtex E, there is no problem. > Appreciate any help on this problem.Article: 75468
Hi, I need the programming algorythm for the above devices, because this devices has no JTAG port. This devices cann't be programmed via JTAG, only via special programming sequences but I can't find the programming algorythm on the Web yet. Thank you. AttilaArticle: 75469
> I am not sure why you think instantiating the flop will prevent the > PC to do clock-gating. But if that's really the case, you can always > upsize the flop after the PC is done before you start the CTS. Write > out the verilog, change the flop and continue with the rest of the > flow. I still think you should be able to instantiate the flop only > (the same type as the PC generates but with a higher drive) and let PC > handle the rest. I believe, eventually you are going to do scan insertion. During scan insertion, you may use the folowing command: set_scan_register_type -exact -type <scanFF_cell_name> <chosen regs> (see man page on this command) I also don't think that it is a good idea to edit synthesised gate-level verilog. It is error-prone and hard to repeat each time you do re-synthesis. If you have to to modifications after synthesis - you can do it with dc (or pc) - tcl and then add your modifications to the synthesis script. You can see an example of dc-tcl code on my site: www.adeptix.com/tclforeda -> DC enhancements -> rebind_cell Regards, Alexander GnusinArticle: 75470
whizkid@gamebox.net (whizkid) wrote in message news:<edfc084c.0411060642.1f87efc7@posting.google.com>... > hi all, > how to force DC to use a specific cell for specific part of the code > in verilog module. Power compiler is implementing my logic with XL > gate (low power, high delay) from TSMC library. I want to use X2 or X4 > flop for only that part of the code in the total verilog module. How > can I do that?? > > By the way I cant instantiate the gate from cell library since the > clock is gated. > (becoz I want power compiler to insert clockgate circuitry in the > clock pin of the flop.) > Regards > whizkid Whizkid, Why are posting "ASIC" stuff to the "FPGA" newsgroup? Are you porting a "FPGA" design to an "ASIC"?, or more likely using an FPGA to sanity check an ASIC design. I suppose a small percentage of the group has done both ASICs and FPGAs, I know I did in a prior lifetime, but based on the number of FPGA seats people are suggesting, I suspect that the percentage that do both is relatively small. - regards NewmanArticle: 75471
Hey all, I have some questions on ISE/EDK. I would really appreciate some help. Before I start, some explanation of my project. It's called Network Encryption Engine. There are two components in the project, Client and Server. Client is our FPGA board. Whenever client has request use a specific encryption standard (we just using AES only). It will connect to server and download the bit-stream and run it on FPGA and will give the necessary outputs. Question A For simple case, we assume the AES part is available locally. Our code for AES is on Verilog. Our application is running on PowerPC developed by EDK. Problem is right now interfacing these two. For simpler case, like full adder in Verilog and Simple C application to write the UART (HyperTerminal), how do I integrate it so that I can read the input (full adder) from UART and write it to ports on the Verilog code and display the output back in the UART. Question B For network development part, there are several options a. XIlnet b. RTOS like Vxworks, Linux c. ucLinux d. Connect to another board which has TCP/IP Stack already enabled. -Found the Xilinx site that, option (a) is not stable and unreliable -BSP for option (b) came with the ML310 board, but IDE's to develop application need to be bought and are expensive. - ucLinux must be ported to ML310 Microblaze design - d is most viable option now. Is there any other options we can use to develop this.? Technical Details Development Board: ML310 FPGA: Virtex 2 Pro Thank you in Advance Cheers ShakithArticle: 75472
always@(posedge CLK or negedge RST) begin
if(!RST) begin
EN132 <= 1`b0;
end
else if(ENB) begin
EN132 <= n_EN132;
end
end
say in this is the piece of code...
If I instantiate a DFF from library what will I connect to the CLK pin
of the flop(coz I want to gate the clock).. well its possible to
instantiate the both the flop and the integrated clock gate cell from
the library.. Is that what u meant to say??
thanks
whizkid
mk<kal@delete.dspia.com> wrote in message news:<91tpo09fhc5n5bapiccnbk3ce9c4bpg44v@4ax.com>...
> On 6 Nov 2004 06:42:00 -0800, whizkid@gamebox.net (whizkid) wrote:
>
> >hi all,
> >how to force DC to use a specific cell for specific part of the code
> >in verilog module. Power compiler is implementing my logic with XL
> >gate (low power, high delay) from TSMC library. I want to use X2 or X4
> >flop for only that part of the code in the total verilog module. How
> >can I do that??
> >
> >By the way I cant instantiate the gate from cell library since the
> >clock is gated.
> >(becoz I want power compiler to insert clockgate circuitry in the
> >clock pin of the flop.)
> >Regards
> >whizkid
>
> I am not sure why you think instantiating the flop will prevent the
> PC to do clock-gating. But if that's really the case, you can always
> upsize the flop after the PC is done before you start the CTS. Write
> out the verilog, change the flop and continue with the rest of the
> flow. I still think you should be able to instantiate the flop only
> (the same type as the PC generates but with a higher drive) and let PC
> handle the rest.
Article: 75473Howz the FPGA market doing now, is there any hiring going on in the market for coding and developing. My perceptive is industry is now seeking individuals with more experience , having abilities to manage a group and provide input for architecting future products for the company. So what would be a choice for a fresh graduate , how his outlook should be. If this choice of hiring( experienced ) continues, what sort of training the fresh graduate has to undertake him/herself to break the ice. The current situation forces many B.S students to seek M.S and M.S degree holders to seek Ph.d's. Will this not disturb the balance?? Appreciate the input from experts in this group. MRMArticle: 75474
Hi, all I have found the problem, wrong pin assignment :( Thanks!
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