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"David Dye" <davidd@xilinx.com> wrote in message news:418FB3A2.1000300@xilinx.com... > > > Antti Lukats wrote: > > "Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message > > news:418B3A65.9040700@numeri-cable.fr... > > > >>Antti Lukats a écrit: > >> > >> > >>>advice: if you do any serious FPGA verification (with Xilinx silicon) > > > > you > > > >>>*MUST* use ChipScope - no way around it. There are other OCI solutions > >>>availabe of course also, but I would defenetly consider ChipScope as > > > > primary > > > >>>tool. > >> > >>I still wonder why Xilinx is *selling* this tool, especially since you > >>can't do much serious work without it. > >>Altera's SignalTap is free and (IMO) much more user friendly. > > > > > > You are right - it would much nicer if ChipScope would be free (at least for > > those who have ISE full...) I got ChipScope initially as bundled software > > with ML300 (total value of purchase >$5000 USD), that CS was version 5.1 and > > there was no free update to even 5.2 !! That was bizarre! And the price went > > up 2 times what also isnt so nice change. I guess the reason Xilinx is > > selling ChipScope is that ChipScope cores, including ILA (not only ATC2) - > > are designed by Agilent, so there could be still some ownership issue. This > > information is (about who wrote ILA cores) is from inside Agilent so I > > assume its correct. Possible that also explains why the core integration > > isnt always working as smootly as it could be and why Xilinx still is > > struggling to get Chipscope analyzer to work in Linux. > > > > I have used ChipScope for long time, and sure have a lot of struggle with > > it. Its getting better with every service pack. And if you KNOW it you can > > use it in very friendly manner. If you dont, well then you have to learn, > > possible the hard way. > > > > I dont want to say that, but when I first time tested SignalTap - I was > > really surprised how easy it was! Funny thing is that I used SignalTap to > > check out how MicroBlaze works in Cyclone :) > > ok, YES, SignalTap is easy (its not directly free as you need use it on a PC > > that is required to be online and sends reports back to Altera), SignalTap > > doesnt have some features that I use in ChipScope VIO and core generator are > > not there. > > > > Hm, another thing that is missing from ChipScope is upload of user memories! > > (SignalTap can do that). > > > > ok, enough :) > > Antti > > PS I still have a dream of doing a cross platform OCI system some day > > (partial work is completed) > > Antti, > > Let me clear a couple points you have brought up. > > First, the original ChipScope Pro ILA, IBA and VIO cores, along with the > Generator, Inserter and Analyzer tools were all developed entirely by > Xilinx from the very beginning. The only collaboration with Agilent for > deliverables within the ChipScope Pro toolset has been the development > of the ILA/ATC and ATC2 cores, which has been shared nearly equally > during our partnership. (Agilent, of course, has put a great deal of > effort into their Trace Port Analyzer and the new FPGA Dynamic Probe > tools.) The information you have received was incorrect. The information as I did explain was as correct as received from inside of Agilent, but I agree I could have understant it not 100% precise, I was told by Agilent that not only ATC but also ILA cores are from Agilent, possible they wanted to say "not only ATC2 but also ILA/ATC" are from Agilent. > Second, since the product's introduction in March 2000, the price has > only gone up once, from $495 to $695, to account for a number of new > cores and features. I can't speak for prices of integrated packages, > but any increases have not been due to price changes of ChipScope Pro > itself. I havent hopefully said that price has changed more than once (if I have then that must have been typo error from my side). If you have CS 5.1 but cant upgrage to 5.2 and are required to buy new version with new price? I still thing that updates at least between minor version should be free of charge. > Third, ChipScope Pro is currently (version 6.3i) available for Linux > platforms for Core Generation and Insertion, and expect to see Analyzer > support soon. without Analyzer there is no use for ChipScope. I did expect that Linux Analyzer will be available in 6.3 - I did know its coming..coming and it looked to me as it could come already in 6.3, a small disappointment that it did not make it into 6.3 release > Finally, we still charge for ChipScope Pro because we consider it a > "value-added" product above and beyond the scope of the ISE toolset, > like other tools like EDK, PlanAhead, and System Generator. It is not a > required tool (even though you consider it a "*MUST* Have" -- thanks for > the endorsement!), and I expect we will follow this model for forseeable > future. ok, good this comment is not me, I havent said Chipscope should be free it was somebody else who indicated such a wish. hm that was somebody wondering why it isnt free. uups I better watch what I am saying, I have said it would nice to have CS free for (at least) registered ISE users. Ok that stands, it would be nice. But hasnt have to be no problems with that. It could cost more if it would be more powerful. > Thanks for you comments, > David Dye > Xilinx Technical Marketing > Longmont, Colorado >Article: 75526
Comments included below! "Antti Lukats" <antti@case2000.com> wrote in message news:cmoeif$ngr$03$1@news.t-online.com... > "Symon" <symon_brewer@hotmail.com> wrote in message > news:2v9q51F2j8q2hU1@uni-berlin.de... > > Antti, > > Here's my list! > > 1) Simulate or die. > > sure Symon! - "sure" translated from my mother tong means "die!" ;) - not > kidding. > You want me dead? A little bit of an over reaction!! ;-) > > did you look ever at the signal is coming from RocketIO when there is no > valid signal applied to the RXN/RXP? It is something NEVER documented in > anywhere. It can be analyzed and the result of that can be used to determine > if there is some burst or longer period of silence. Without capturing the > real data its not possible to implement the logic. Not possible to simulate > before you have at least once captured the real signal. There are other > simular scenarios where pure simulations (without ever doing FPGA > verification at all) will not work. Thats what I reffered too. > OK, but this is a hardware issue. And doing things like this is probably OK on the bench, but if Xilinx ever change the die (sure?!), or you buy from a different batch and the behaviour changes, what are you gonna do? They're not gonna support undocumented features. > > > 2) That's it. > > Sure, its the basic rule of digital designs - when you do it right (i.e. > when you connect the wires) then it will always just work. From that if it > works in simulations, it must work in FPGA? I bet most of us know that it > isnt so. Something that works in simulation doesnt necessarily work without > any change done in FPGA, by whatever reasons. Its a little bit better with > ASIC, FPGA's and FPGA tools have too many things unknown or weird (to make > the first FPGA tests always succesful after succesful simulation). > Well, I'm finding it hard to recall an occasion when my simulator and real design differed. Maybe in the bad old days. So, I'll disagree on this point. > <snip> > > A version of ChipScope that has that improvement and not only that exists > already. > Well I dont know the release date but its coming. Really! > Excellent! I wonder how much they'll bump the price? ;-) Best, Syms.Article: 75527
Jim Granville wrote: <snip> > If you look at Figs 49 thru 52 in the Philips 87C888, you get some > idea. > The MIPS/Watt values are very good, especially on what was a relatively > old process. See also how MIPS/Watt scales with Vcc. > > Async is not going to displace Sync designs in all areas, but it > does illuminate design pathways for lower power. > One of those, is Vary of Vcc. > > Presently FPGA's spec only ONE Vcc, but a recent thread covered > an emerging potential for Wider variances on Vcc. > This is somewhat innate in the silicon, it just needs the > mindset and specs change to use it. To update this, for a topical example of SoC design to vary Both CLK and VCC, I see this : Synopsys, UMC, join ARM, National for low-power SoC demo http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=ABWJJD3VJ1Z2IQSNDBGCKHSCJUMEKJVN?articleID=52500027 It states: "The demonstrator is set to use adaptive voltage scaling as well as frequency scaling. The system is expected to make use of the lowest voltage and frequency required to meet software deadlines while maintaining user quality." So, sometime in 2005, we might see a 'like process' comparison between the above and this Async alternative http://www.arm.com/news/6936.html and maybe the FPGA vendors will start to follow this ? -jgArticle: 75528
Hi Patrick, since you use an FPGA you have plenty of opportunities for data exchange. What kind of data and control flow would you like to implement in your system. Can you give us a short more descriptive example? Best Regards Markus "Patrick Gao" <foolboylei@vip.sina.com> wrote in message news:<cmliur$ucn$1@news.yaako.com>... > Hello, > > I am doing a project to build a system to receive GPS signals. > > I selected a Baseband Processor Zarlink GP4020 which has a ARM7TDMI core > embened inside it. > > Now I want to add a FPGA(SpartanII XC2S200) to assist it in some arithmatic > computation. And I want to use a Dual Port SRAM to store the temporary data > and make the main processor and the FPGA communicate with each other. > > My question is : In what way can this two chip synchronize the process with > each other? (maybe about timing and signal exchange) > > > Thank you > > Regards > PatrickArticle: 75529
Hi Vick, please find my remarks in your text below ... iamyourengineer2004@hotmail.com (Vick) wrote in message news:<c373aa10.0411072131.3400cfee@posting.google.com>... > Hello all, > > I had psted this question earlier but havent got any response yet... > I was wondering if the questions I asked made any sense (or) were they > just out of the way... So again, I have the Micron SDRAM Verilog code > and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM > shold maintain its own functionality (i.e. it itself can be > read/written). > > The questions I have are: > > (1) Should my SRAM just issue Read/Write command to SDRAM Controller > and then it will do the rest i.e. Read/write from SDRAM. > > (2) Should'nt the SRAM output (Q) be a bi-directional since this pin > Q has to be used for SRAM read and also for SDRAM read? Normally the SRAM should not drive the data bus if it is not selected... > > > The logidc diagram I have come up with is as below: > > > INTERFACE -Logic > ______________________________ > |IF Read_SDRAM = 1 then | `````````````````` > |- Initiate SDRAM Read Command |------>|SDRAM Controller| > |- Addr = SDRAM_Address; | `````````````````` > | | | > |IF Write_SDRAM = 1 then | | > |- We_n = Write_SDRAM; | | > |- Addr = SDRAM_Address; | | > ------------------------------ v > A ******>| | | ____________ > B**********>| | Addr(11-bits)--->| | > C*************>| other I/Ps | | > | | | ... | | > V V V ... | | > _____ ... | Micron | > Data---->| | ------>| SDRAM | > Wad ---->| |_________ Q | (168-pin) | > Rad ---->|SRAM | | | | > ---->|_____| | | | > ^ ^ ^ | | | > | | | |_______Dq (16-bits)__ | | > | | | | | > clk____| | | ____________ > WE ________| | > RE____________| > Nice drawing, however is your SRAM and your SDRAM connected directly to each other, or is this done through an interface logic inside a CPLD/FPGA ?? > > > > Steps to the above logic-diagram: > > (1) I have allocated 3 new pins to the SRAM above namely A,B,C which > are designated as: > > A --> Read_SDRAM (1-bit) > B --> Write_SDRAM (1-bit) > C --> SDRAM_Address (11-bits) > > > (2) The Interface-Logic shown above programs the SDRAM Controller as > to whether the SRAM wants to Read (or) Write the SDRAM. ie. the SDRAM > Controller is asked to fire the appropriate Command to the SDRAM > (Read, Write, Aotorefresh etc..) > > (3) The SDRAM Controller then takes over by firing executing the > Command requested by SRAM. > > (4) Say, if the SRAM requested a Read from SDRAM, then the data read > (16-bits) is sent back to the pin-Q of SRAM. > > Note: that the pin-Q is also used for outputting the 16-bit data for > Reading the SRAM itself! > > So folks , please let me know if the above logic and its description > makes sense... > Sorry I do not reallyy understand what you want to do. Is the SRAM kind of a memory that stores read/write request operations from/to the SDRAM ? Markus > > Thanx, > Eagerly waiting... > VickArticle: 75530
x_u, Considering the diodes are always there, and they are normally clamping whenever there is overshoot and undershoot, the recovery time must be so short that it is of no consequence. If you are concerned, I would download the hspice models, and simulate the condition you are interested in. http://www.xilinx.com/support/software/spice/spice-request.htm Austin xilinx_user wrote: > The Spartan 3 device can be made 5V tolerant by using a series > resistor to limit the amount of current flowing into a forward biased > clamp diode, when the input voltage exceeds 4V. > > The question I have is how does this affects the AC timing in light of > a diode recovery time when going from forward to reverse voltage. > Let's suppose the maximum forward current is 1 ma.Article: 75531
> 1. Will this approach work?
There is not enough information here
to base any judgment on. You could improve
your odds by focusing on the system description
without assuming so much in advance about
the optimum implementation details.
Or maybe you could restrict the topic to
research into partial reconfiguration, since
this seems to be your overriding interest.
> 2. If the logic is fixed, do I need long lines and TBUFs,
There are no real tri-state buses current FPGAs.
-- Mike Treseler
Article: 75532alex.ungerer@chauvin-arnoux.com (Alex Ungerer) wrote in message news:<24a8d57b.0411080753.41f0e78d@posting.google.com>... > Hello, > > I am not sure if this is the right NG, but since it concerns memory > driven by an FPGA, here goes. > > My question is about burst writes to SDRAM memory (be it standard, DDR > or DDR2). > > Is it possible to sustain a burst write for an undefined number of > words? Here is my setup: > I have some incomming flow of data arriving at a constant speed of, > say 250 MWords/s, which needs to be written to memory in a sequential > order, until a Stop signal ends the burst. The length of the flow can > be as long as several times the size of the memory, in that case the > latter data overwrites the old one. > > Do SDRAM require dedicated refresh cycles, even if the write cycles > will access in turn every possible location in the memory? You don't need to refresh memory as long as you touch (write or read) every row of every bank within the refresh period specification in the datasheet. > > Alternatively, would there be a way of refreshing a bank while writing > into another one, without interrupting the 250 MWrd/s data flow? > There is no "buried" refresh. Even at large burst sizes where the control could overlap access to another bank, you would need to do a read to the unused bank which would necessarily take over the part's data bus. If you have more than one physical bank of parts (i.e. more than one chip select) you could run refresh cycles on the unused parts. Note that auto refresh (what was CAS-before-RAS in the old days) requires ALL banks of the part to be pre-charged so you can't bury it during access to another bank of the same part. > If this is technically possible, do SDRAM Controller IPs available > from FPGA vendors (i.e. Xilinx, Altera) support sustained writes with > no gaps in data flow? I've used parts of a Xilinx reference design to start similar IP of my own. Generally the hard part of the design is getting the DDR data to look like SDR data at twice the width. I use the reference design for this data timing, and then use my own control logic to generate the sequence of commands I want to the RAMs. > > Any pointers to litterature, memory types, SDRAM controller IPs, would > be appreciated. You didn't mention a vendor. If you haven't picked the part yet, I would suggest looking into Lattice EC, Altera Stratix 2, or Xilinx Virtex 4. All of these parts make the high-speed data interface simpler. > > AlexArticle: 75533
Symon wrote: > ... > Well, I'm finding it hard to recall an occasion when my simulator and real > design differed. Maybe in the bad old days. So, I'll disagree on this point. > They don't disagree for me, but I certainly do see cases where a design with a fairly complex interaction with real world interfaces results in signal combinations that trigger unexpected behaviors. An example that comes to mind is a PCI interface on one side and a fairly complex backend on the other (not my design, but I ended up debugging it). When this happens, simulating the exact signal combination generally reproduces the error in the testbench. And figuring out exactly what is going on and how to fix it is much easier within the testbench. But I find this much easier to do if I can find some signal within the FPGA that is not behaving as expected, narrowing down to a general area where the problem is. In the past, I used Xilinx "probes" for looking at these internal signals, but one of these days I'll give ChipScope a try; I had not tried it before because, well, there was no Linux version. -- My real email is akamail.com@dclark (or something like that).Article: 75534
I want to use the Spartan 3 in a "5V tolerant" mode, and will use a series resistor to limit the reverse current to under 1 ma (this is fairly arbitrary; the current can be further limited.) The question I want to ask, therefore, is what is the magnitude of the reverse recovery time. Are the numbers know for this?Article: 75535
I find your query to be quite confusing. According to the diagram, read/write signals to the SDRAM controller are coming from the interface logic, which appears not to be receiving signals from the SRAM, but from the off-page source of A, B, and C. Dwayne Surdu-Miller ------------------------------------------------ Vick wrote: > Hello all, > > I had psted this question earlier but havent got any response yet... > I was wondering if the questions I asked made any sense (or) were they > just out of the way... So again, I have the Micron SDRAM Verilog code > and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM > shold maintain its own functionality (i.e. it itself can be > read/written). > > The questions I have are: > > (1) Should my SRAM just issue Read/Write command to SDRAM Controller > and then it will do the rest i.e. Read/write from SDRAM. > > (2) Should'nt the SRAM output (Q) be a bi-directional since this pin > Q has to be used for SRAM read and also for SDRAM read? > > > The logidc diagram I have come up with is as below: > > > INTERFACE -Logic > ______________________________ > |IF Read_SDRAM = 1 then | `````````````````` > |- Initiate SDRAM Read Command |------>|SDRAM Controller| > |- Addr = SDRAM_Address; | `````````````````` > | | | > |IF Write_SDRAM = 1 then | | > |- We_n = Write_SDRAM; | | > |- Addr = SDRAM_Address; | | > ------------------------------ v > A ******>| | | ____________ > B**********>| | Addr(11-bits)--->| | > C*************>| other I/Ps | | > | | | ... | | > V V V ... | | > _____ ... | Micron | > Data---->| | ------>| SDRAM | > Wad ---->| |_________ Q | (168-pin) | > Rad ---->|SRAM | | | | > ---->|_____| | | | > ^ ^ ^ | | | > | | | |_______Dq (16-bits)__ | | > | | | | | > clk____| | | ____________ > WE ________| | > RE____________| > > > > > Steps to the above logic-diagram: > > (1) I have allocated 3 new pins to the SRAM above namely A,B,C which > are designated as: > > A --> Read_SDRAM (1-bit) > B --> Write_SDRAM (1-bit) > C --> SDRAM_Address (11-bits) > > > (2) The Interface-Logic shown above programs the SDRAM Controller as > to whether the SRAM wants to Read (or) Write the SDRAM. ie. the SDRAM > Controller is asked to fire the appropriate Command to the SDRAM > (Read, Write, Aotorefresh etc..) > > (3) The SDRAM Controller then takes over by firing executing the > Command requested by SRAM. > > (4) Say, if the SRAM requested a Read from SDRAM, then the data read > (16-bits) is sent back to the pin-Q of SRAM. > > Note: that the pin-Q is also used for outputting the 16-bit data for > Reading the SRAM itself! > > So folks , please let me know if the above logic and its description > makes sense... > > > Thanx, > Eagerly waiting... > VickArticle: 75536
Yes, the old Virtex E configuration have only one PROM. what do you mean by "and twisting a ground with each signal helped"? Is that true to have a ground trace in parrallel with each signal?Article: 75537
Hi,
I am using Modelsim 6.0a .. I need to perform floating point
operations in VHDL (multiplication and addition)..But the IEEE library
that I use in Modelsim 6.0 doesnt have the support ..So I need to
create a library and use ..i could get the floating point package
files from http://www.eda.org/fphdl/ but I dont know how to create a
library from these files and start using this library ..Can anyone
help me in this ..Thanks in advance
Article: 75538
Hi Nicolas,
The max fan-out feature is available for the families after Flex10K
i.e , Apex 20K/E/C/II, Stratix, StratixGX, Cyclone, Stratix II and MaxII. If
you are starting a new design the Cyclone device family should support the
performance and or features you need.
Hope this helps.
- Subroto Datta
Altera Corp.
"Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message
news:418F7801.2090301@numeri-cable.fr...
> Hello
> Is there a way to specify a maximum signal fan-out for Altera Flex10K
> FPGAs? The option seems only be available for more recent families.
> I am explicitly duplicating high-fanout signals and putting "preserve"
> constraints but it is long since I don't always know signals fan-out.
>
>
> --
> ____ _ __ ___
> | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
> | | | | | (_| |_| | Invalid return address: remove the -
> |_| |_|_|\__|\___/
>
Article: 75539
Parag wrote:
> I am using Modelsim 6.0a .. I need to perform floating point
> operations in VHDL (multiplication and addition)..But the IEEE library
> that I use in Modelsim 6.0 doesnt have the support ..So I need to
> create a library and use ..i could get the floating point package
> files from http://www.eda.org/fphdl/ but I dont know how to create a
> library from these files and start using this library
Easiest way is to compile the files
you need into your work directory:
vcom some_lib.vhd
and try them out:
use work.some_lib.all;
-- Mike Treseler
Article: 75540Hello, I just released InFormal 0.1.1: a new open-source assertion based verification tool. InFormal can prove the correctness of Verilog designs without using simulation -- otherwise known as formal verification. With release 0.1.1, InFormal now provides initial support for PSL/Sugar. Currently only a small subset of PSL is supported, but it's PSL never the less. Though InFormal is in very early beta, it has already uncovered bugs in real designs -- in part thanks to automatic assertions. Using InFormal's automatic assertions, engineers can find potential design issues without having to explicitly define PSL properties. InFormal leverages the elaboration and synthesis technology of Icarus Verilog with the high performance symbolic model checking engine of NuSMV. Many thanks to the Icarus and NuSMV teams for providing their awesome open-source technology. For more information on InFormal, including source code and Linux binaries, visit: http://www.confluent.org/ Enjoy! -TomArticle: 75541
Hi.. Is it recommended to use following scheme, to generate "Differential SSTL_2" clock signals which are sourcing DDR SDRAM & another controller. 1. Normal 125 MHz LVTTL clock source(Oscillator) feeding clock to FPGA. 2. FPGA functionality inverts this clock. 3. The same i/p clock & inverted clock are sent out of FPGA, with setting I/O standard of these to outputs as "OBUF_SSTL2_I". If this scheme is ok, will there be any constrain on using particular family of FPGA like Spartan 2, Spartan 3 or virtex etc. Cheers, ManishArticle: 75542
Hello Markus, Thanx for the reply. Ok. Here is what I want to do (Objective): Objective:- My SRAM should be able to Read (or) Write the specified # of bytes of data from/to the SDRAM. For eg: Say I want to read 10-byes of data from the SDRAM, then my SRAM should be able to instruct the SDRAM Controller to read that many bytes from the SDRAM at the specified address. And vice-versa for writing the data to the SDRAM. Now this reminds of defining another signal- D D --> # of bytes to be Read/Written from/to SDRAM To answer your questions, Markus:- > Nice drawing, however is your SRAM and your SDRAM connected > directly to each other, or is this done through an interface > logic inside a CPLD/FPGA ?? - Well! I think there definitely needs to be an interface between the SRAM and the SDRAM for carrying out the transactions. So thats why I have defined the interface logic as shown in the diagram. If you are referring to the Dq (16-bits bus) directly connected to the Q (16-bits bus) then I think there also needs to be some sort of interface logic inorder to meet the timing parameters. > Sorry I do not reallyy understand what you want to do. Is the > SRAM kind of a memory that stores read/write request operations > from/to the SDRAM ? - I have specified this above in the Objective. Yes, this SRAM kind of memory will get the Read/Write requests, # of bytes and then process them thru the SDRAM controller as it consists Read/Write and other COmmands defined for SDRAM. So, if the Verilog-model of any standard SRAM is say:- `````````````````````````````````````` SRAM (Data, Q, clk, WE, RE,Wad,Rad); | `````````````````````````````````````` For my application this gets modified to as below:- `````````````````````````````````````````````````` SRAM (Data, Q, clk, WE, RE,Wad,Rad, A, B, C, D); | `````````````````````````````````````````````````` So, the interface-logic I have shown in the diagram will go inside the SRAM block itself. Hope I was clear this time, And am I approaching this problem with rite way, Thanx, Waiting, -V meng.engineering@bluewin.ch (Markus Meng) wrote in message news:<aaaee51b.0411081237.25e186c6@posting.google.com>... > Hi Vick, > > please find my remarks in your text below ... > > iamyourengineer2004@hotmail.com (Vick) wrote in message news:<c373aa10.0411072131.3400cfee@posting.google.com>... > > Hello all, > > > > I had psted this question earlier but havent got any response yet... > > I was wondering if the questions I asked made any sense (or) were they > > just out of the way... So again, I have the Micron SDRAM Verilog code > > and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM > > shold maintain its own functionality (i.e. it itself can be > > read/written). > > > > The questions I have are: > > > > (1) Should my SRAM just issue Read/Write command to SDRAM Controller > > and then it will do the rest i.e. Read/write from SDRAM. > > > > (2) Should'nt the SRAM output (Q) be a bi-directional since this pin > > Q has to be used for SRAM read and also for SDRAM read? > > Normally the SRAM should not drive the data bus if it > is not selected... > > > > > > The logidc diagram I have come up with is as below: > > > > > > INTERFACE -Logic > > ______________________________ > > |IF Read_SDRAM = 1 then | `````````````````` > > |- Initiate SDRAM Read Command |------>|SDRAM Controller| > > |- Addr = SDRAM_Address; | `````````````````` > > | | | > > |IF Write_SDRAM = 1 then | | > > |- We_n = Write_SDRAM; | | > > |- Addr = SDRAM_Address; | | > > ------------------------------ v > > A ******>| | | ____________ > > B**********>| | Addr(11-bits)--->| | > > C*************>| other I/Ps | | > > | | | ... | | > > V V V ... | | > > _____ ... | Micron | > > Data---->| | ------>| SDRAM | > > Wad ---->| |_________ Q | (168-pin) | > > Rad ---->|SRAM | | | | > > ---->|_____| | | | > > ^ ^ ^ | | | > > | | | |_______Dq (16-bits)__ | | > > | | | | | > > clk____| | | ____________ > > WE ________| | > > RE____________| > > > > Nice drawing, however is your SRAM and your SDRAM connected > directly to each other, or is this done through an interface > logic inside a CPLD/FPGA ?? > > > > > > > > Steps to the above logic-diagram: > > > > (1) I have allocated 3 new pins to the SRAM above namely A,B,C which > > are designated as: > > > > A --> Read_SDRAM (1-bit) > > B --> Write_SDRAM (1-bit) > > C --> SDRAM_Address (11-bits) > > > > > > (2) The Interface-Logic shown above programs the SDRAM Controller as > > to whether the SRAM wants to Read (or) Write the SDRAM. ie. the SDRAM > > Controller is asked to fire the appropriate Command to the SDRAM > > (Read, Write, Aotorefresh etc..) > > > > (3) The SDRAM Controller then takes over by firing executing the > > Command requested by SRAM. > > > > (4) Say, if the SRAM requested a Read from SDRAM, then the data read > > (16-bits) is sent back to the pin-Q of SRAM. > > > > Note: that the pin-Q is also used for outputting the 16-bit data for > > Reading the SRAM itself! > > > > So folks , please let me know if the above logic and its description > > makes sense... > > > > Sorry I do not reallyy understand what you want to do. Is the > SRAM kind of a memory that stores read/write request operations > from/to the SDRAM ? > > Markus > > > > > Thanx, > > Eagerly waiting... > > VickArticle: 75543
Hello Dwayne, > I find your query to be quite confusing. According to the diagram, > read/write signals to the SDRAM controller are coming from the interface > logic, which appears not to be receiving signals from the SRAM, but from > the off-page source of A, B, and C. > > Dwayne Surdu-Miller Sorry, there is small correction in the diagram. Please, imagine the interface-logic to be within the SRAM block itself. So, now the SDRAM Controller receives the signals from the SRAM in order to do the read/write, from/to the SDRAM. Also, may i request you to kindly read my follow up posting to Markus. Thanx, Waiting for all your valuable suggestions/comments, -v Dwayne Surdu-Miller <miller@SEDsystems.nospam.ca> wrote in message news:<10ovpsqsqikgo4c@corp.supernews.com>... > I find your query to be quite confusing. According to the diagram, > read/write signals to the SDRAM controller are coming from the interface > logic, which appears not to be receiving signals from the SRAM, but from > the off-page source of A, B, and C. > > Dwayne Surdu-Miller > > ------------------------------------------------ > Vick wrote: > > > Hello all, > > > > I had psted this question earlier but havent got any response yet... > > I was wondering if the questions I asked made any sense (or) were they > > just out of the way... So again, I have the Micron SDRAM Verilog code > > and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM > > shold maintain its own functionality (i.e. it itself can be > > read/written). > > > > The questions I have are: > > > > (1) Should my SRAM just issue Read/Write command to SDRAM Controller > > and then it will do the rest i.e. Read/write from SDRAM. > > > > (2) Should'nt the SRAM output (Q) be a bi-directional since this pin > > Q has to be used for SRAM read and also for SDRAM read? > > > > > > The logidc diagram I have come up with is as below: > > > > > > INTERFACE -Logic > > ______________________________ > > |IF Read_SDRAM = 1 then | `````````````````` > > |- Initiate SDRAM Read Command |------>|SDRAM Controller| > > |- Addr = SDRAM_Address; | `````````````````` > > | | | > > |IF Write_SDRAM = 1 then | | > > |- We_n = Write_SDRAM; | | > > |- Addr = SDRAM_Address; | | > > ------------------------------ v > > A ******>| | | ____________ > > B**********>| | Addr(11-bits)--->| | > > C*************>| other I/Ps | | > > | | | ... | | > > V V V ... | | > > _____ ... | Micron | > > Data---->| | ------>| SDRAM | > > Wad ---->| |_________ Q | (168-pin) | > > Rad ---->|SRAM | | | | > > ---->|_____| | | | > > ^ ^ ^ | | | > > | | | |_______Dq (16-bits)__ | | > > | | | | | > > clk____| | | ____________ > > WE ________| | > > RE____________| > > > > > > > > > > Steps to the above logic-diagram: > > > > (1) I have allocated 3 new pins to the SRAM above namely A,B,C which > > are designated as: > > > > A --> Read_SDRAM (1-bit) > > B --> Write_SDRAM (1-bit) > > C --> SDRAM_Address (11-bits) > > > > > > (2) The Interface-Logic shown above programs the SDRAM Controller as > > to whether the SRAM wants to Read (or) Write the SDRAM. ie. the SDRAM > > Controller is asked to fire the appropriate Command to the SDRAM > > (Read, Write, Aotorefresh etc..) > > > > (3) The SDRAM Controller then takes over by firing executing the > > Command requested by SRAM. > > > > (4) Say, if the SRAM requested a Read from SDRAM, then the data read > > (16-bits) is sent back to the pin-Q of SRAM. > > > > Note: that the pin-Q is also used for outputting the 16-bit data for > > Reading the SRAM itself! > > > > So folks , please let me know if the above logic and its description > > makes sense... > > > > > > Thanx, > > Eagerly waiting... > > VickArticle: 75544
"Duane Clark" <junkmail@junkmail.com> wrote in message news:cmoon20cj5@news4.newsguy.com... > Symon wrote: > > ... > > Well, I'm finding it hard to recall an occasion when my simulator and real > > design differed. Maybe in the bad old days. So, I'll disagree on this point. > > > > They don't disagree for me, but I certainly do see cases where a design > with a fairly complex interaction with real world interfaces results in > signal combinations that trigger unexpected behaviors. An example that > comes to mind is a PCI interface on one side and a fairly complex > backend on the other (not my design, but I ended up debugging it). Yes, PCI is a good example. Or better lets say a complex PCI design is a candidate of an design that may benefit from FPGA probing. And also in generic, if you are doing FPGA verification of an design written by entity A, that is verified by an testbench written by entity B (or A even worse!) and if the design uses modifications or add ona (like PCI backend) written by entity C (or you) and if the final FPGA system has to pass all interoperability and compliance testing, then this is a potential case where FPGA probing may come handy. Even if initial simulations did not show any problems. > When this happens, simulating the exact signal combination generally > reproduces the error in the testbench. And figuring out exactly what is > going on and how to fix it is much easier within the testbench. But I > find this much easier to do if I can find some signal within the FPGA > that is not behaving as expected, narrowing down to a general area where > the problem is. In the past, I used Xilinx "probes" for looking at these > internal signals, but one of these days I'll give ChipScope a try; I had > not tried it before because, well, there was no Linux version. Yes exactly, its generically, if s*** happens (and it does happen!) then probing can narrow down the issue and greatly helps to enhance the testbench (to catch the problem and verify that the core does not behave badly under the conditions that caused the trouble seen using FPGA capture). More for PCI debugging - Gaisler Research free open source GPL licensed GRLIB SoC design environment includes a PCI target/initiatior and also a PCI Trace Buffer! So it provides the PCI core and meand to debug it, and the monitor application is available for Linux too :) Similarly ChipScope has special bus monitor cores for the Xilinx SoC onchip busses (PLB/OPB) to help troubleshooting bus access specially in case of debugging custom EDK IP-Cores. > -- > My real email is akamail.com@dclark (or something like that).Article: 75545
Tom Hawkins a écrit: > Hello, > > InFormal can prove the correctness of Verilog designs without using simulation I'm sure VHDL users will be very happy to know this... -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 75546
Antti Lukats a écrit: > "David Dye" <davidd@xilinx.com> wrote in message > news:418FB3A2.1000300@xilinx.com... >>Finally, we still charge for ChipScope Pro because we consider it a >>"value-added" product above and beyond the scope of the ISE toolset, >>like other tools like EDK, PlanAhead, and System Generator. It is not a >>required tool (even though you consider it a "*MUST* Have" -- thanks for >>the endorsement!), and I expect we will follow this model for forseeable >>future. > > > ok, good this comment is not me, I havent said Chipscope should be free it > was somebody else who indicated such a wish. hm that was somebody wondering > why it isnt free. > > uups I better watch what I am saying, I have said it would nice to have CS > free for (at least) registered ISE users. Ok that stands, it would be nice. > But hasnt have to be no problems with that. It could cost more if it would > be more powerful. It was me wondering why it wasn't free when Altera's SignalTap was. Actually, I'm only using ISE WebPack (we don't do many Xilinx designs, we're more Altera-flavoured) so I'm not complaining too much :o) -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 75547
Hi @ all, I am trying to implement a SDR/DDR SDRAM controller. My question: Is it possible to access (write or read) two different rows in one bank at the same time ? I could not find that situation described in any of those papers I read (for example Micron, Infineon). Thank you for your help. Rgds AndreArticle: 75548
mike_treseler schrieb: >>1. Will this approach work? > > > There is not enough information here > to base any judgment on. You could improve > your odds by focusing on the system description > without assuming so much in advance about > the optimum implementation details. > > Or maybe you could restrict the topic to > research into partial reconfiguration, since > this seems to be your overriding interest. I implemented some partial reconfiguration designs already. Just now, I focus mainly on persistent working logic within a slot under reconfiguration. The communication system connects all slots of my FPGA and shall even work if a slot is under reconfiguration. However, if the CS signal is active of a Xilinx FPGA, the complete logic works. Logic under reconfiguration produces trashy signals, and therefore the C/S has to be suspended if any slot is reconfigured. But IMHO trashy signals are only produced by changing logic, therefore I want to fix the related logic (only one CLB) within each module's type, to avoid suspending of the C/S. And my question is, is this assumption true? >>2. If the logic is fixed, do I need long lines and TBUFs, > There are no real tri-state buses current FPGAs. You haven't understand my question. Real tri-state behavior wasn't a matter. Xilinx approach needs TBUFs and long lines to provide fixed points within a slot to connect signals of all types of a module properly, since logic is changing. But now I have some fixed logic, do I still need fixed communication points? Bye TomArticle: 75549
alex.ungerer@chauvin-arnoux.com (Alex Ungerer) writes: > Hello, > > I am not sure if this is the right NG, but since it concerns memory > driven by an FPGA, here goes. > > My question is about burst writes to SDRAM memory (be it standard, DDR > or DDR2). > > Is it possible to sustain a burst write for an undefined number of > words? Here is my setup: So long as you get the banking right so you can overlap the precharges, then doing the writing is no problem. You'll need to explicitly change row/bank each time you fill a row up, otherwise you'll just wrap around on the row. If you change bank, then you can "start" the access (do the RAS bit) just before the current bank/row is full and then the data will be able to stream continuously. > I have some incomming flow of data arriving at a constant speed of, > say 250 MWords/s, which needs to be written to memory in a sequential > order, until a Stop signal ends the burst. The length of the flow can > be as long as several times the size of the memory, in that case the > latter data overwrites the old one. > > Do SDRAM require dedicated refresh cycles, even if the write cycles > will access in turn every possible location in the memory? > So long as you "touch" each row in each bank often enough you don't have to do refreshes. I have done this in video applications where data is continually being read out, so no refreshes were required. > Alternatively, would there be a way of refreshing a bank while writing > into another one, without interrupting the 250 MWrd/s data flow? > I think you can do this as well. > If this is technically possible, do SDRAM Controller IPs available > from FPGA vendors (i.e. Xilinx, Altera) support sustained writes with > no gaps in data flow? > I don't know, but it wasn't that much effort to write my own when I got around to it! I seem to recall that the Altera core has a fairly low-level interface so you may be able to overlap commands like you want to. Dunno about the Xilinx one. > Any pointers to litterature, memory types, SDRAM controller IPs, would > be appreciated. > Micron have *lots* of good datasheets. Happy reading! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
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