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where is your library unisim statement?Article: 75401
Alan Fitch wrote: > > > As an experiment, what happens if you take HOST_DATA out of > the sensitivity list? For a standard clocked process template > I'd only expect to see asynchronous control signals and > the clock in the sensitivity list, e.g. > > addr_update:process(host_cswr, addr_clk_i) > begin > ... The result does not change (mux infered). Furthermore, I get a warming, WARNING:Xst:819 - C:/busmaster/busmaster.vhd line 16: The following signals are missing in the process sensitivity list: HOST_DATA. Thanks. VAX, 9000 > > > regards > Alan > >Article: 75402
I was wondering if any of these numbers have been given from any of the FPGA vendors, either up to date or during some limited time. 1) Number of ISE/Quartus licenses sold 3) Number of ISE/Quartus web/free edition downloads 3) Number of programming cables sold Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 75403
Alan Fitch wrote: > > As an experiment, what happens if you take HOST_DATA out of > the sensitivity list? For a standard clocked process template > I'd only expect to see asynchronous control signals and > the clock in the sensitivity list, e.g. > > addr_update:process(host_cswr, addr_clk_i) > begin > ... That would not be correct in this case because the signal ADDR will change on a change of HOST_DATA while HOST_CSWR is low. So HOST_DATA does need to be in the sensitivity list. Normally the async control is just a clear or set so the data value is fixed, not a signal. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75404
Marc, You need to consult the design considerations section of the Virtex-II data book. Assuming you have listed all the global clocks in your design there a NO clock conflicts. Conflicts can only exist between primary & secondary pairs (P & S, e.g. 0P & 0S may compete for the same clock resources). It is why the they are named that way. What I see as the primary difference is that cclk_in_g is 7P (board Y) or 3S (board X). These are on different edges of the die. 7P top, 3S bottom. Given that configuration Y works I will venture an educated guess that its being driven by a input (or DCM) also in the top of the die. And in configuration X you have the same source but are now routing the global clock input to BUFGMUX3S on general interconnect all the way across the die (less than ideal at best). Marc Kelly wrote: > Hi, > > >>For X board (NON working..) > > >>| clk_ret_i | BUFGMUX0S| No | 2172 | 0.272 | 1.188 > >>| cclk_in_aux | BUFGMUX4S| No | 33 | 0.069 | 1.157 > >>| cclk_in_g | BUFGMUX3S| No | 3 | 0.000 | 1.136 > >>| dclk_g | BUFGMUX6S| No | 10 | 0.007 | 1.150 > > >>For Y board (working..) > >>| clk_ret_i | BUFGMUX2S| No | 2171 | 0.272 | 1.188 > >>| cclk_in_aux | BUFGMUX4S| No | 33 | 0.029 | 1.167 > >>| cclk_in_g | BUFGMUX7P| No | 5 | 0.138 | 1.161 > >>| dclk_g | BUFGMUX6S| No | 10 | 0.005 | 1.111 > > > Given the above BUFGMUX locations, I think Board X should be working > > and Y should have bad clocks. > > Board Y BUFGMUXs for cclk_in_g and dclk_g are using adjacent BUFGMUXs > > which is not correct. > > I got confirmation today that the whole system of 24 board (all with the > y board clock configuration) has worked and passed the initial > testing. Its part of a hep physics experiment so kind of important that > it works :) > > I would have though that given control over clock placing that the place > &route tool wouldn't choose a non-working combination ( be that the x or > y above...) but then you live and learn.. > > /\/\arcArticle: 75405
vax, 9000,
My first recommendation is to re-write it so the load is
synchronous to clock:
ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I)
begin -- process
if ADDR_CLK_I'event and ADDR_CLK_I = '1' then
if HOST_CSWR = '0' then
ADDR <= HOST_DATA;
else
ADDR <= ADDR_NEXT;
end if;
end if;
end process;
This will still have the mux, but the logic on the
asynchronous control lines is gone.
If you must stay asynchronous, try the following. This
focuses the synthesis tool on the logic on the asynchronous
control lines and keeps the data value '0' or '1' like
it would expect for clear/preset controls.
GenRegs : for i in HOST_DATA'range generate
begin
ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I)
begin -- process
if HOST_CSWR = '0' and HOST_DATA(i) = '0' then
ADDR(i) <= '0' ;
elsif HOST_CSWR = '0' and HOST_DATA(i) = '1' then
ADDR(i) <= '1' ;
elsif ADDR_CLK_I'event and ADDR_CLK_I = '1' then
ADDR(i) <= ADDR_NEXT(i) ;
end if;
end process;
end generate GenRegs ;
If you are worried about optimial logic, you will want
to look at the specifics of your device. What is the
cost of the asynchronous logic vs what is the cost of
a multiplexer (with synchronous controls)? If there is
other logic involved in generating ADDR_NEXT or HOST_DATA?
Will using asynchronous controls prevent some of it from
being merged into the macrocell that creates the register
for ADDR?
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 75406Austin's always banging on about his 200000+ seats. ;-) "We have 200,000+ seats of software out there," http://www.google.com/groups?q=xilinx+seats+group:comp.arch.fpga+author:austin&hl=en&lr=&scoring=d&selm=cl6lj8%24t3p2%40cliff.xsj.xilinx.com&rnum=1 Maybe the most annoying thing about Usenet is people not googling before they post? Much more irritating than top-posting, don'tcha think? ;-) In jest, Symsx. "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:87wtx1y0tx.fsf@parish.home.gustad.com... > > I was wondering if any of these numbers have been given from any of > the FPGA vendors, either up to date or during some limited time. > > 1) Number of ISE/Quartus licenses sold > 3) Number of ISE/Quartus web/free edition downloads > 3) Number of programming cables sold > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 75407
I'm experimenting with chipscope pro to test it and see if we can use it in our company, so i got the 6.3i demo and am inserting the ILA/ICON and VIO and in the PAR report i get: WARNING:Place - The structured logic associated with a shift register could not be placed in such a way as to use the appropriate fast connections. Shift registers should flow through every slice down through the clb(s) that they use. The relative placement required by the logic was impossible to resolve. The following components are involved in this logic: SLICE i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m atch /pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxh/O SLICE i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m atch /pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O SLICE i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m atch /pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O This situation can be resolved by fixing the following issue: The structured logic could not be placed in the relative placement form required. This is due to the fact that the component i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m atch /pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O is already contained in an rpm that will not allow the logic to be placed in the legal form. WARNING:Place - The structured logic associated with a shift register could not be placed in such a way as to use the appropriate fast connections. Shift registers should flow through every slice down through the clb(s) that they use. The relative placement required by the logic was impossible to resolve. The following components are involved in this logic: SLICE i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m atch /pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxh/O SLICE i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m atch /pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O This situation can be resolved by fixing the following issue: The structured logic could not be placed in the relative placement form required. This is due to the fact that the component i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m atch /pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O is already contained in an rpm that will not allow the logic to be placed in the legal form. now i was wondering, is this a fault in my implementation of a mistake by the chipscope generator? Thanks in advanca kind regardsArticle: 75408
"Yttrium" <Yttrium@pandora.be> wrote in message news:wRuid.11510$Hh1.459812@phobos.telenet-ops.be... > I'm experimenting with chipscope pro to test it and see if we can use it in > our company, so i got the 6.3i demo and am inserting the ILA/ICON and VIO > and in the PAR report i get: > > WARNING:Place - > The structured logic associated with a shift register could not be placed > in just dont pay attention to that, it always gives zillion of similar warnings! advice: if you do any serious FPGA verification (with Xilinx silicon) you *MUST* use ChipScope - no way around it. There are other OCI solutions availabe of course also, but I would defenetly consider ChipScope as primary tool. Antti PS I am using ChipScope to to capture at 3GS/S :) with rocketIO and custom "analyzer" application, kinda nice to see 3GS/S Logic analyzer - my primary use was capturing USB HS raw data, V2Pro rocketio can be directly coupled to USB (receive only)...Article: 75409
Anyone looked at or using Synplicity's Identify product? Wanna share your experiences? Cheers, Syms.Article: 75410
"Symon" <symon_brewer@hotmail.com> writes: > Austin's always banging on about his 200000+ seats. ;-) > "We have 200,000+ seats of software out there," > http://www.google.com/groups?q=xilinx+seats+group:comp.arch.fpga+author:austin&hl=en&lr=&scoring=d&selm=cl6lj8%24t3p2%40cliff.xsj.xilinx.com&rnum=1 Thank you for the link. > Maybe the most annoying thing about Usenet is people not googling before > they post? Much more irritating than top-posting, don'tcha think? ;-) Well, I did search, but I was searching for number of licenses and similar terms. Searching for seats did not occur to me at the time. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 75411
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:87sm7pxov0.fsf@parish.home.gustad.com... > Well, I did search, but I was searching for number of licenses and > similar terms. Searching for seats did not occur to me at the time. > I was just pulling your leg, Petter! I only knew what to search for because Austin had posted so recently in a thread I was interested in. I remember wondering if the other 199,999 designers have as much 'fun' with the software as I do! ;-) Good luck with your research, All the best, Syms.Article: 75412
Yes!! They are D2SBs!! Okay, this is too much of a coincidence, any idea why THESE SPECIFIC boards are breaking all the time? "Vadim Vaynerman" <vadimv@ieee.org> wrote in message news:<ee89de4.2@webx.sUN8CHnE>... > Let me guess - are these Digilent 2SB boards, with the Spartan2E 200K FPGA? I work in a university also, and those are the boards that we got as a donation. 3 out of 5 are down, with the same symptoms... -VadimArticle: 75413
I have a design that has compiled fine under ISE for three years. Now ISE 6.3i sp2 has a problem with the module name "adc". Specifically, it can't figure out this module's correct place in the design hierarchy. In the "Sources in Project" window it lists this module at the top of the hierarchy instead of down under the module in which it is instantiated. Adding one character to the module name fixes the problem. Anyone else seen this? The problem did not exist in ISE 5.2i sp3. That's the last version I used before 6.3i sp2. RobArticle: 75414
Hi, Austin Lesea <austin@xilinx.com> wrote: > Additionally, there are three known ways to eliminate soft errors as a > cause of functional failures, so you had better worry about the 'real' > problem, and not chase red herrings (where in the world does that > colloquialism come from?). Would you think it is possible to have a design in an Xilinx fpga with FIT rates below 20 usable in Orbit? I can't sell my customers a single component with FIT rates of several hundreds. Even if I could prove, that other failures are dominant over fpga failures. My answer based on the question if an Cpld would be better than an Fpga in safty critical applications which is not the overall case in my opinion, because I see no technical advantage of an Cpld, which might be seen by people thinking Fpgas are always SRAM-based. I would like to have you proving that even SRAM-based Fpgas are good enough. bye ThomasArticle: 75415
Antti Lukats a écrit: > advice: if you do any serious FPGA verification (with Xilinx silicon) you > *MUST* use ChipScope - no way around it. There are other OCI solutions > availabe of course also, but I would defenetly consider ChipScope as primary > tool. I still wonder why Xilinx is *selling* this tool, especially since you can't do much serious work without it. Altera's SignalTap is free and (IMO) much more user friendly. -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 75416
"Symon" <symon_brewer@hotmail.com> wrote in message news:2uve7mF2es7aoU1@uni-berlin.de... > Anyone looked at or using Synplicity's Identify product? Wanna share your > experiences? > Cheers, Syms. :) yes looked only shortly, its more like "rtl debugger" not logic analyzer. A nice tool in any case that for sure. Unfortunatly our free license expired before I had any chance to test any further. Its funny, they Identify lite is supposed to be free, but after registration they will try to call your mobile, and the free license expires very quickly. AnttiArticle: 75417
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:418A6AC2.3DD89BD0@yahoo.com... > Alan Fitch wrote: > > > > As an experiment, what happens if you take HOST_DATA out of > > the sensitivity list? For a standard clocked process template > > I'd only expect to see asynchronous control signals and > > the clock in the sensitivity list, e.g. > > > > addr_update:process(host_cswr, addr_clk_i) > > begin > > ... > > That would not be correct in this case because the signal ADDR will > change on a change of HOST_DATA while HOST_CSWR is low. So HOST_DATA > does need to be in the sensitivity list. Normally the async control is > just a clear or set so the data value is fixed, not a signal. > Oh yes, sorry, brain failure :-) Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 75418
I'm the parent poster who started this thread. I was over seas this past few days, so I wasn't able to provide the requested information on power. Currently the DSP draws under 130 mA @ 1.25 V (core) and under 80 mA 3.3V I/O, clocked @ 300 MHz. The processing is using less than 15% of the DSP's available horsepower, which means the functionality should easily fit into an FPGA. Would a modern FPGA with twelve 6-stage (3 biquad) IIR filters, 32-bit fixed- point, clocked at 1 MHz be able to significantly beat those power levels? What about handling a softcore? John.Article: 75419
Hi all, after syntheising with design Compiler , I manually changed a cell from the netlist(changed the gate strength)... How can get an SDF file for this new netlist...using DC thanks whizkidArticle: 75420
whizkid@gamebox.net (whizkid) writes: > Hi all, > after syntheising with design Compiler , I manually changed a cell > from the netlist(changed the gate strength)... How can get an SDF file > for this new netlist...using DC You get and SDF file from your place and route tool. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 75421
"Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message news:418B3A65.9040700@numeri-cable.fr... > Antti Lukats a écrit: > > > advice: if you do any serious FPGA verification (with Xilinx silicon) you > > *MUST* use ChipScope - no way around it. There are other OCI solutions > > availabe of course also, but I would defenetly consider ChipScope as primary > > tool. > > I still wonder why Xilinx is *selling* this tool, especially since you > can't do much serious work without it. > Altera's SignalTap is free and (IMO) much more user friendly. You are right - it would much nicer if ChipScope would be free (at least for those who have ISE full...) I got ChipScope initially as bundled software with ML300 (total value of purchase >$5000 USD), that CS was version 5.1 and there was no free update to even 5.2 !! That was bizarre! And the price went up 2 times what also isnt so nice change. I guess the reason Xilinx is selling ChipScope is that ChipScope cores, including ILA (not only ATC2) - are designed by Agilent, so there could be still some ownership issue. This information is (about who wrote ILA cores) is from inside Agilent so I assume its correct. Possible that also explains why the core integration isnt always working as smootly as it could be and why Xilinx still is struggling to get Chipscope analyzer to work in Linux. I have used ChipScope for long time, and sure have a lot of struggle with it. Its getting better with every service pack. And if you KNOW it you can use it in very friendly manner. If you dont, well then you have to learn, possible the hard way. I dont want to say that, but when I first time tested SignalTap - I was really surprised how easy it was! Funny thing is that I used SignalTap to check out how MicroBlaze works in Cyclone :) ok, YES, SignalTap is easy (its not directly free as you need use it on a PC that is required to be online and sends reports back to Altera), SignalTap doesnt have some features that I use in ChipScope VIO and core generator are not there. Hm, another thing that is missing from ChipScope is upload of user memories! (SignalTap can do that). ok, enough :) Antti PS I still have a dream of doing a cross platform OCI system some day (partial work is completed)Article: 75422
Hello, I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i. I am observing a illogical problem. All my flip flops are negative edge triggered but some how even if the edge on the clock comes cpld doesnt recognize it. So I made a simple flip flop where at Power On Reset I am clearing it and at the edge of the clock I am setting it to 1. Even then I was not able to see that test signal as 1. When I converted the test flip flop from -ve edge to +ve edge I was getting proper result. After that I converted all other signals to +ve edge triggered and I observed same problem as was in -ve edge trigerred.even in test Flip Flop. Again I converted just the Test flip flop to -ve edge and kept all other +ve edge and again proper results. Now I want to buffer the clock as I think this is a problem of loading of clock. but as if I write Clock1 <= Clock; xst removes it so how can I tell xst to not remove that. any other suggestions for problem I m observing. Thank u NaimeshArticle: 75423
Thanks for all the responses.
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
> where is your library unisim statement?
I was attempting to declare the component's interface myself, but I'm
using the unisim declaration again now. I have now got an error at
synthesis:
ERROR:Xst:764 - C:/code.vhd line 22: No default binding for component:
<SRL16E_1>. Generic <INIT> is not on the entity.
ERROR: XST failed
If I simply change SRL16E_1 to SRL16E the code passes through with no
warnings or errors. Anyone know what is going on?
Eric.
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.VComponents.all;
entity ten_srl16s is
port(
Clock : in std_logic;
CE : in std_logic;
NewContent : in std_logic_vector (9 downto 0);
Stimulus : in std_logic_vector(3 downto 0);
Output : out std_logic_vector(9 downto 0)
);
end ten_srl16s;
architecture structure of ten_srl16s is
signal tempoutput : std_logic_vector(9 downto 0);
begin
-- Instantiate the 10 srl16s
instantiatesrl16s: for i in 0 to 9 generate
cell : SRL16E_1 port map(
Q=>tempoutput(i),
A0=>stimulus(0),
A1=>stimulus(1),
A2=>stimulus(2),
A3=>stimulus(3),
CE=>CE,
CLK=>Clock,
D=>newcontent(i)
);
end generate;
process(Clock)
variable answer : std_logic_vector(9 downto 0);
begin
Output<=answer;
if (Clock'event) and (Clock='1') then
answer:=tempoutput;
end if;
end process;
end structure;
Article: 75424
Hi,
When I have a synchronous interface running on a clock coming from a PAD on
a Xilinx FPGA, I know there is a good way to constraint input/output timing
using OFFSET constraints here.
But,
How do you specify output timing if you have DATA clocked out by an internal
clock (generated by a FF) and also forward this clock to the PAD?
FF
Data +---+
----------|D Q|--------------------| |Data PAD
| |
.---|C | How do I know clock data
relationship?
| +---+
Internal |
-------------------------------------| |Clock PAD
clock
Regards
Hakon
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