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Gregory Burd wrote:
> I'm looking to do some experiments with FPGAs, but I work solely on my
> Mac PowerBook laptop and I don't really have an easy place to keep an
> exposed FPGA development board lying around (I live on a sailboat).
A sailboat would be a good place to learn HDL simulation.
Here's one for Mac OS X:
http://www.gmvhdl.com/mac-dv.html
-- Mike Treseler
Article: 77001Thanks Hal and Philip. That Annapolis Micro Wildcard-II (http://www.annapmicro.com/wildcard2.html) seems like the beast I was looking for. Windows and Linux drivers. If the Linux drivers are open source it won't be hard for me to port it to Mac OS/X. The driver kit is fairly straight forward. With that I should be able to talk to it, poke around a bit. As for development software, gee I don't know. Anyone have suggestions? I'm really just starting out in hardware design. I've been in software land for 15 years professionally. I've been looking for a challenge and I saw the empty PCMCIA slot on my Mac and said, "Hey, I wonder what fun new interesting thing I could plug in there and learn about?" FPGAs have always been very interesting to me, so a few seconds later I launched my quest. I'm a fan of very high level languages (lisp, Erlang, etc) and yet I've done a lot of work at the C and assembly levels so I'm really interested to see how far I can get toward making a tool like the Wildcard-II available to the general user via say Io (www.iolanguage.com). I'm very curious about async logic design and non-von Neumann computer architectures. I know, I know I'm in way over my head. But that's the fun part, right? cheers, any additional help always appreciated. -gregArticle: 77002
Mike Treseler wrote: > Gregory Burd wrote: > >> I'm looking to do some experiments with FPGAs, but I work solely on my >> Mac PowerBook laptop and I don't really have an easy place to keep an >> exposed FPGA development board lying around (I live on a sailboat). > > > A sailboat would be a good place to learn HDL simulation. > Here's one for Mac OS X: > http://www.gmvhdl.com/mac-dv.html > > -- Mike Treseler Thanks Mike. Its Winter here in Boston so I have to keep the brain moving so it won't freeze up. This looks like a good exercise to do just that. -gregArticle: 77003
"Gregory Burd" <gburd@sleepycat.com> wrote in message news:10sbag6rstknjcd@corp.supernews.com... > Thanks Hal and Philip. That Annapolis Micro Wildcard-II > (http://www.annapmicro.com/wildcard2.html) seems like the beast I was > looking for. Windows and Linux drivers. If the Linux drivers are open > source it won't be hard for me to port it to Mac OS/X. The driver kit > is fairly straight forward. With that I should be able to talk to it, > poke around a bit. As for development software, gee I don't know. > Anyone have suggestions? I'm really just starting out in hardware > design. I've been in software land for 15 years professionally. I've > been looking for a challenge and I saw the empty PCMCIA slot on my Mac > and said, "Hey, I wonder what fun new interesting thing I could plug in > there and learn about?" FPGAs have always been very interesting to me, > so a few seconds later I launched my quest. I'm a fan of very high > level languages (lisp, Erlang, etc) and yet I've done a lot of work at > the C and assembly levels so I'm really interested to see how far I can > get toward making a tool like the Wildcard-II available to the general > user via say Io (www.iolanguage.com). I'm very curious about async > logic design and non-von Neumann computer architectures. I know, I know > I'm in way over my head. But that's the fun part, right? Might be interesting having a look at the Celoxica offering - C-ish program compiled to FPGA (I think it's C with fiddly bits to describe the parallelism in hardware design).Article: 77004
Neil wrote: > I am looking for some material about the various clock synchronization > techniques, their advantages etc. A flipflop does the job. There is little else to be said. You're not talking about a PLL do you ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 77005
Michel Bieleveld wrote: > I am trying to achieve something that probably thousand have done > before me. I want to program a sram module that is attached to my fpga > (xc2s300). I have a parallal cable programmer that is compatible with > imPact. Now i am wondering what do you use (software/hardware) to > program ram by jtag. There must be an easy way !? > > Michel Bieleveld. Hi. I am not sure how your particular FPGA implements its JTAG interface, but you can probably obtain control of the pins on the FPGA (the ones that connect to your RAM) by clocking in and out serial data through the JTAG port (IEEE 1149.1 standard). I used a homemade substitute of the parallell-programmer to write data into flash memories attached to a MCU this way. I rewrote the code found on http://www.lart.tudelft.nl/projects/jtag/ to suit my particular hardware configuration. Hope this helps you find a solution. Redards Daniel NilssonArticle: 77006
I'm trying to read a list of stimulus files from a directory file.
This is described on page 527 of Ashenden's book.
At the start of file_loop, read(directory, file_name, file_name_length);
doesn't do what I expected. I assumed it would read an individual
string representing a file name, and would stop when it came to a <CR>
or <LF> . Then on the next pass of the loop it would read the
next filename. Instead, it fills file_name with 50 characters
(including <CR> and <LF>) on each pass.
What am I doing wrong?
Thanks
file_reader : process is
type directory_file is file of string;
file directory : directory_file open read_mode is "stimulus-directory";
variable file_name : string(1 to 50);
variable file_name_length : natural;
variable open_status : file_open_status;
variable char : character;
type char_file is file of character; -- one byte each
file stim_file : char_file;
begin
file_loop : while not endfile(directory) loop
read(directory, file_name, file_name_length);
if file_name_length > file_name'length then
report "file name too long: " & file_name & "... - file skipped"
severity warning;
next file_loop;
end if;
file_open (open_status, stim_file,
file_name(1 to file_name_length), read_mode);
if open_status /= open_ok then
report file_open_status'image(open_status) & " while opening file "
& file_name(1 to file_name_length) & " -file skipped"
severity warning;
next file_loop;
end if;
stimulus_loop : while not endfile(stim_file) loop
if (rst = '1') then
sig <= "00000000";
data_valid <= '0';
elsif (clk'event and clk='1') then
data_valid <= valid;
if (valid = '1') then
read(stim_file, char);
end if;
sig <= char2std(char);
end if;
end loop stimulus_loop;
file_close(stim_file);
end loop file_loop;
wait;
end process file_reader;
Article: 77007On Thu, 16 Dec 2004 04:11:48 -0600, hmurray@suespammers.org (Hal Murray) wrote: >I can't see how to make a 1 Hz output with a 27 bit phase accumulator >running at 100 MHz. Works great if I have a 134.217728 MHz clock. > >If I have a 27 bit accumulator and I add 1 each cycle with a >100 MHz clock, I get 0.745 Hz. Adding 2 makes 1.490 Hz. > >Is there some variation of the simple phase accumulator that I >haven't stumbled into yet? If so, what's the magic word? ********* Unless you are dealing with an application that needs a frequency tolerance of +/- less than 1 Hertz, a 27 bit accumalator and a 100 MHz clock is quite fine. It is rare in consumer or most industrial electronics that the frequency generated need be that tight of tolerance. Even if so then pick a value for your accumalator and match the crystal that will give you 1 Hz steps. jamesArticle: 77008
... >user via say Io (www.iolanguage.com). I'm very curious about async >logic design and non-von Neumann computer architectures. I know, I know >I'm in way over my head. But that's the fun part, right? > >cheers, any additional help always appreciated. All the stuff you mentioned is very high level. If you want to run something on your PCMCIA card, you need the low level tools, and I don't know of anything that runs on the MAC. The low level place-and-route tools are roughly the assembler part of a compiler/assembler combination. You might consider taking a 1-day intro class or find a friend who has the tools installed and will help you get started. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 77009
tnx for that.Article: 77010
Austin Lesea wrote > Jim, > > We can keep the memory contents of the 4VLX25 all the way down to where > the configuration logic recognizes a power down condition (runs around > ~0.6 V). > > Now, to be sure, we have not characterized everything down that far > (0.6V), but we did do all characterization for functionality tests from > 1.0V to 1.4V, so we know for sure we are safe inside this region (memory > contents stay). If someone had a killer app that needed beaucoup parts, > we would consider binning for lower numbers. > > Some people are considering operating at the 1.2V nominal, and then > 'sleeping' at 1.0V. The sleeping is just all clocks stopped (disabled). On this subject of lowering FPGA Vcc's to a keep-alive level / hibernate, this is a new device from Linear http://www.linear.com/press/pressNewsDisplay.do?releaseID=1402 It has an i2c BUS + 6 bit DAC, which covers 0.85..1.55V on Core, plus two Aux LDO paths. -jgArticle: 77011
Hello, We're employing FPGAs in industrial conditions (wide temperature range, noise). Currently we are using ACEX1K. Some people are reluctant to move to the new technologies (Stratix, Stratix II) because of their low core voltage. Are there are articles about the reliability of various FPGAs in industrial applications ? Any information about the lower reliability of 1.8 and 1.5 volt core devices ? TxArticle: 77012
I require some basic help in understanding the various memories and their usage for the Xilinx V2 Pro series of FPGA. Basically, external to the chip I have SRAM and FLASH - I think I grasp that internally, there is BRAM which is physical memory and you also have the option of Select RAM which is just memory configured from CLBs. What I am trying to understand is what buses are used to allow 'sharing' of memory between the FPGA and PPC Core ?? My application involves the FPGA gathering serial data (lots of it) and then I need to fetch it and do some work on it. At the moment we are only using a small pice and I think it must be Select RAM as the PPC accesses it via the DCR bus - which is SLOW and where my problem lies !! Is it possible for the FPGA and PPC to use the same piece of BRAM ?? What about the external SRAM ?? And if so, what buses are used to do the comms ?? Thank You A chucked in at the deep end PPC developer.Article: 77013
HI, (Apologies if this has been discussed before) We have installed modelsim 6.0 on our network and are experiencing unusual behavior. From the command line.... vcom....works vsim -h ...works vsim ......gives a segmentaion fault ** Fatal: Segmentation Violation. This happens on Linux and Solaris but not on XP. Some other users in my department see this but others dont. Has anybody experienced this type of behaviour? Thanks, JamesArticle: 77014
Hi GL, I talked to one of our design experts, and he is almost certain he knows what you're seeing (to be 100% sure he'd have to see the design, but he's pretty confident he knows the issue). The asynchronous FIFO has a path between two grey coded counters, with appropriate metastability registers. The design assistant does not know that the bank of registers involved in this transfer are grey-coded counters, so it is flagging what appears to it to be a valid warning about a multi-bit transfer across clock domains. The grey-coding makes this safe in this case though, so you can ignore the warning. There is already a software problem report open on this, and the long-term solution is to make the design assistant aware of the higher-level functionality of the FIFO. If you want to make this warning go away, you can put a timing cut between the two banks of registers (or between the two clock domains, but that is more dangerous since it will cut all timing paths between the clock domains). That will stop the design assistant from analyzing this transfer. Regards, Vaughn Altera v b e t z (at) altera.com [Remove spaces and add proper @ to reach me] > "GL" <a@b.c> wrote in message news:mn.753a7d4ca170b3de.23732@b.c... > > I'm using quartus 4.2, and create some fifo with the mega wizard. > > on one side, synchronous data are writen at 27 MHz (from external > > pins), and on the other side, I'm reading the data with a 80 MHz clock > > (to my design). > > > > The design assistant give me the following warnings : > > > > Data bits are not synchronized when transferred between asynchronous > > clock domains > > Multiple data bits that are transferred across asynchronous clock > > domains are synchronized, but not all bits may be aligned in receiving > > clock domain > > > > my fifos are : > > - without common clock between read and write side > > - the clocks are not synchronized > > - in legacy synchronous mode > > - perfomance are not maximized > > > > > > What should I do ? > > > > -- > > Ceci est une signature automatique de MesNews. > > Site : http://www.mesnews.net > > > >Article: 77015
Gregory Burd wrote: > > so I thought that there must be some FPGA with at least > 8MB of SDRAM packaged as a Type I PCMCIA card > In the close-but-no-cigar category (type II), see also: http://www.comblock.com/download/com1300.pdf Type II PCMCIA/Cardbus, XC3S400, 32 Mb SDRAM, $295 USD BrianArticle: 77016
eliben@gmail.com wrote: > Hello, > > We're employing FPGAs in industrial conditions > (wide temperature range, noise). Currently we > are using ACEX1K. Some people are reluctant to > move to the new technologies (Stratix, Stratix II) > because of their low core voltage. > > Are there are articles about the reliability of > various FPGAs in industrial applications ? Any > information about the lower reliability of 1.8 > and 1.5 volt core devices ? A linear regulator should keep the core as clean as is needed for the devices to operate reliably. I/O voltage(s) remain the same. Remember that most modern devices are not able to deal with much more than 3.5V I/O... so if some of the industrial things you are interfacing to are still in the 5V world, you'll have to get inventive (opto's maybe? relays?) Have fun, MarcArticle: 77017
"Marc Randolph" <mrand@my-deja.com> wrote in message news:1103547600.160962.304190@f14g2000cwb.googlegroups.com... > > A linear regulator should keep the core as clean as is needed for the > devices to operate reliably. ...and a switching supply will work fine too. In fact, I'd bet that a switcher solution is smaller, because you don't need so much heatsinking, and more reliable as your circuit will be operating at a lower temperature. Remember, you're throwing away all that energy in the linear regulator. Design of a switcher is pretty easy too; can you copy a demo board layout? Cheers, Syms.Article: 77018
Hi James, Have you tried 6.0b? Which Linux distro are you using? Hans www.ht-lab.com "James Brennan" <brennan@xilinx.com> wrote in message news:41C6C544.364908B0@xilinx.com... > HI, > (Apologies if this has been discussed before) > We have installed modelsim 6.0 on our network and are experiencing > unusual behavior. > From the command line.... > vcom....works > vsim -h ...works > vsim ......gives a segmentaion fault > ** Fatal: Segmentation Violation. > > This happens on Linux and Solaris but not on XP. Some other users in my > department > see this but others dont. > Has anybody experienced this type of behaviour? > Thanks, > James > >Article: 77019
Shreyas Kulkarni wrote: > hi there, > > i have a (probably very fundamental) doubt regarding PCI - > what is the difference between a PCI master, arbiter and initiator? > they all look same to me. > > TIA, > Shreyas The arbiter is a seprate function that decides which initiator gets the bus. Initiators request the bus and the arbiter grants the bus to one initiator at a time. Every PCI bus must have one and only one arbiter.Article: 77020
Hans, We have got to bottom of problem. Another application that was using FlexLM licensing was corrupting the .flexlmrc file in the home drive. Thanks Hans wrote: > Hi James, > > Have you tried 6.0b? Which Linux distro are you using? > > Hans > www.ht-lab.com > > "James Brennan" <brennan@xilinx.com> wrote in message > news:41C6C544.364908B0@xilinx.com... > > HI, > > (Apologies if this has been discussed before) > > We have installed modelsim 6.0 on our network and are experiencing > > unusual behavior. > > From the command line.... > > vcom....works > > vsim -h ...works > > vsim ......gives a segmentaion fault > > ** Fatal: Segmentation Violation. > > > > This happens on Linux and Solaris but not on XP. Some other users in my > > department > > see this but others dont. > > Has anybody experienced this type of behaviour? > > Thanks, > > James > > > >Article: 77021
Yes you can use BRAM for FPGA and PPC. You can connect on Port to the a process outside the edk ppc system and the other port to the plb or opb bus on the ppc system. If you want the ppc to work fast on that data then use the dsocm interface to connect a bram to ppc. That interface is quit fast and you do not need the plb or opb bus. So no traffic.Article: 77022
To achieve high reliability on low voltage cores, keep in mind to be careful to follow the power on ramp rate requirement of each voltage. For example, the Xilinx Virtex 2 Pro series can have 4 power voltages: 3.3V I/O power, 1.5V FPGA core power, 1.8V PROM core power, and 2.5V auxillary power. The core power for the FPGA and the PROM have a minimum and maximum ramp rate. I had to add large capacitors to the LDO regulator outputs in order to meet the minimum ramp rates. Also, be careful to look for any voltage sequencing requirements the FPGA may have. Sometimes the order the various voltages come up does not matter, but sometimes it does. JohnArticle: 77023
Stephen Maudsley wrote: > Might be interesting having a look at the Celoxica offering - C-ish program > compiled to FPGA (I think it's C with fiddly bits to describe the > parallelism in hardware design). > > Interesting thought. You're suggesting that I take the Io runtime and compile it using this tool? Interesting idea. -gregArticle: 77024
Hal Murray wrote: > .... > >>user via say Io (www.iolanguage.com). I'm very curious about async >>logic design and non-von Neumann computer architectures. I know, I know >>I'm in way over my head. But that's the fun part, right? >> >>cheers, any additional help always appreciated. > > > All the stuff you mentioned is very high level. If you want to run > something on your PCMCIA card, you need the low level tools, and I > don't know of anything that runs on the MAC. > > The low level place-and-route tools are roughly the assembler > part of a compiler/assembler combination. > > You might consider taking a 1-day intro class or find a friend > who has the tools installed and will help you get started. > Hal, Good advise. Part of my goal is to somehow make it possible for those using Mac OS/X to do FPGA development. Seems like a rich untapped market. -greg
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z