Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:<25eqc.5035$SZ4.1551@newsread2.news.pas.earthlink.net>...
> "Tony Dean" <td@emu.com> wrote in message
> news:33aa9b10.0405171520.7798497d@posting.google.com...
> > I want my master input clock, which is on a dedicated pin, to clock
> > most of my logic through a BUFG. I also want it to drive a CLKDLL so I
> > can use the CLK90 output.
> >
> > After much head-banging I assert the following:
> > On a Spartan IIE, an IBUFG output cannot be routed to both a CLKDLL
> > input AND a BUFG input simultaneously.
> >
> > Synplicity will synthesize this setup beautifully, but the Xilinx
> > Placer won't accept it.
> >
> > Yes, I know I could use the CLK0 output through a BUFG instead of my
> > original clock, but my input clock can change speeds abruptly, which
> > will cause the CLKDLL to unlock and exhibit undefined behavior until
> > relocked. This makes me nervous and I'd rather just use my original
> > input, thank you.
> >
> > A double mocha to he or she who can disprove my assertion.
> >
> > -td
>
> Tony,
>
> You should be able to do this:
>
> Connect the IBUFG to a BUFG. Connect the DLL input to the output of that
> BUFG. Use another BUFG on the DLL's 90deg output.
>
> Bob
Hi Bob,
I agree, you should be able to do this. But you can't, or at least I
can't.
I'm getting a Place error on something as trivial as:
input_clk_buf : BUFGP port map (I=>extclk, O=>dll_in_clk);
dll_fb_buf : BUFG port map (I=>dllout_clk0, O=>dll_fb_clk);
dll90_buf : BUFG port map (I => dllout_clk90, O=> clk90);
dll : CLKDLL port map(CLKIN=>dll_in_clk, CLKFB=>dll_fb_clk,
CLK0=>dllout_clk0, CLK90=>dllout_clk90, etc.);
The BUFGP is just a IBUFG+BUFG, like you suggest.
I still get the following Place errors:
ERROR:Place:106 - Could not find an automatic placement for the
following
components:
dll90_buf of type GCLK BUFFER is unplaced.
input_clk_buf/BUFG of type GCLK BUFFER is unplaced.
extclk of type GCLK IOB is unplaced.
dll_fb_buf of type GCLK BUFFER is unplaced.
dll of type DLL is unplaced.
ERROR:Place:107 - Xilinx requires using locate constraints to preplace
such
connected GCLK/GCLKIO/DLL components.
Is it just me?
-td
Article: 69701john jakson wrote: > > "Dave Marsh" <me@privacy.net> wrote in message news:<40a4ce89$0$4587$db0fefd9@news.zen.co.uk>... > > "Andy Peters" <Bassman59a@yahoo.com> wrote in message > > news:9a2c3a75.0405131635.25f8ea90@posting.google.com... > > > "Leon Heller" <leon_heller@hotmail.com> wrote in message > > news:<40a0ebc8$0$25328$cc9e4d1f@news-text.dial.pipex.com>... > > > > > > > > Reflow soldering without baking them (probably 120 C for 24 hours) might > > > > give problems. Hand soldering should be OK: I never have problems, > > anyway. > > > > > > I'm not so sure about that. I bought a handful of microcontrollers > > > about a year ago and stuffed boards, and all was fine. I never > > > resealed the bag (I don't have the facility) so they sat until I used > > > them a month ago. I handsoldered one prototype and it failed in a > > > particular way. After much gnashing of teeth (I hate shotgunning > > > parts), I removed the micro and replaced it with another from the same > > > bag, which worked. I have since hand-built three more prototypes and > > > I've had a 50% fallout. I guess I should've baked the parts... > > > > > > -a > > > > Thanks Andy. That's interesting - One of the assembly houses I've come > > across on the web says the parts would need baking before they will hand > > solder them . This seems to concur with your experiences. > > > > Dave > > Perhaps one of those BlackNdecker toaster ovens will do the job since > they were mentioned awhile back as being useable for home based reflow > ovens in another thread on BGA pcb work. I am sure any oven that will maintain the required temps will do. But I am not convinced that hand soldering without oven drying will cause failures. I have had many boards built by hand without any problems that I can relate to moisture. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69702
Jim Lewis wrote: > > Jon Beniston wrote: > > >>>Ok, maybe not that particular case, but most other configurations of > >>>dual-port RAM can be infered. In Verilog at least, isn't this a > >>>problem with the language rather than the FPGA tools (i.e. you can't > >>>write to the same variable from two different processes)? > >> > >>Verilog does not have this restriction. I've searched the LRM and > >>I've run testcases through two reputable implementations without > >>complaints (ncverilog, icarus). > > > > > > You are correct. Although it is only ever supported for simulation. I > > can kind of understand why though. Take the following: > > > > module test(c1, c2, a, b, d); > > input c1, c2, a, b; > > output d; > > reg d; > > always @(posedge c1) > > d <= a; > > always @(posedge c2) > > d <= b; > > endmodule > > > > What logic would you synthesize it to? Have you tried this with a > > behavioural synthesis tool? Maybe that could do a better job. > > > > Another interesting question about the proposed > code above is, during a given simulation cycle > if both clocks rise at the same time, which > executes first in simulation? > > Can you re-write the code so that one always > has wins or if both happen a the same time > an 'X' is generated on d? Same as in the real world, the result is indeterminate. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69703
Anders wrote: > > Two months after Xilinx acquired Triscend, it now seems they are planning > to kill the Triscend products. We recently got the End-of-life > notification for the A7 processor, and I guess the E5 is also going. > > Can anybody guess what their plans might be? What is the point of buying a > company and dropping the products? Except for the purpose of getting > irritated customers who will get enourmous redesign work using some other > processor. > > I can't imagine that Triscend was a very big threat to the Microblaze > market, to warrant shutting it down just to kill the competition. > > Does anybody know of a replacement for the Triscend A7 processor? We are > using it together with a Xilinx FPGA (at least until now...) and have > implemented a FIFO in the CSL to move data at high speed from the FPGA to > external SDRAM (Up to 128 Mbits/second in packets of 8 32-bit words). This > link seems to be difficult to implement using a "standard" ARM7 > processor. > > Any suggestions and views are appreciated. I am surprised that Xilinx is ending the A7 line. I expected that they were buying Triscend to get an ARM license and technology to compete more directly with the Altera ARM/FPGA chips. I agree that it makes no sense unless they are going to produce a new device with the ARM7/9 combined with one of their own FPGAs like the V2Pro. But I am sure they know better how to approach this market than I do. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69704
Hi Sander, http://www.dspguru.com/info/tutor/quadsig.htm Cheers, Syms.Article: 69705
John_H wrote: > > "Jon Beniston" <jon@beniston.com> wrote in message > news:e87b9ce8.0405180353.48eef0f2@posting.google.com... > > > Zigbee news from Atmel - what's key here, is a move from generic > > > uC/Chip sales, into also selling the Zigbee SW stack, so users have > > > minimal SW developments for their links. > > > > Trouble is, they're using a 900MHz radio, whereas everyone else in the > > ZigBee/802.15.4 world is doing 2.4GHz. > > > > I personally would recommend this device: > > > > http://www.oki.com/en/press/2004/z04017e.html > > > > (Disclaimer: I designed half of it ;) ) > > > > Cheers, > > JonB > > Looks like a neat device from the press release. > > It's too bad I have no idea what the part number or ballpark price might > be - it seems the press release isn't geared much for the design engineer. > :-/ OKI expects that you won't be shy and can contact your local rep or disti. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69706
This is an extremely basic question about complex math. Real and Imaginary number pairs make up a cartesian coordinate pair. Think of the real part as the x-axis and the imaginary part as the y-axis. Amplitude and phase values produce a polar coordinate location. Think of the amplitude as the distance from the (x,y)=(0,0) origin and the phase as the angle counter-clockwise from the x-axis. The conversion from cartesian to polar comes from: amplitude^2 = x^2 + y^2 tan( phase ) = y/x I hope your FPGA work doesn't get hampered too much by your limited engineering-math knowledge. Good luck with the project! "Sander Odekerken" <sander.odekerken@lycos.nl> wrote in message news:c8ddio$drv$1@news3.tilbu1.nb.home.nl... > Hello everybody, > > For a school project I use the Xilinx Coregen FFT core. It does work, but > what does the output mean? Is the Real output the amplitude and the > Imaginary output the phase? > > If anyone knows, please HELP!!! > > thanks, > > Sander Odekerken > >Article: 69707
If you aren't already using a DLL, you might consider it. It can remove several nanoseconds of clock-to-output delay. These are available in the device you're using. Increasing drive strength can cause problems with simultaneous switching such as ground bounce. Xilinx's documentation should have guidelines telling you how many drivers of each strength you can use within a bank before having problems, but these are only guidelines. "prav" <praveenkn123@yahoo.com> wrote in message news:863df22b.0405180416.23b4ec7e@posting.google.com... > Hi all, > > I am targeting my design to XCS200 -5 fg256(SPARTAN device) . My > OFFSET OUT timing constraints are very tight.So inorder to decrease > the PAD delay i am forced to set the drive strength to 24 and > SLEW=FAST. only 2 pins of the 137 I/O's which i am using have a drive > strength of 24 rest of them have a DRIVE=12. > > Can anyone tell me what is the significance of this DRIVE strength in > REAL time.Will it create any problems having a DRIVE=24 in real > time??. > > Thanks n rgds, > pravArticle: 69708
Hi, I am learning Verilog with a mind to implementing a simple 1980s style video generator, hooked up to a W65C02S microprocessor. Very 80s. The processor interface will have a dozen or so 8-bit registers, and the memory interface at least a 16-bit memory address register, some state registers and a few counters. The VGA timing interface will have a couple or three counters. As you can instantly tell, it hasn't been thought through yet. This is day two of my "do something concrete" plan. In looking at FGPA specifications on the XILINX site, I see gate counts and CLB counts. The specs suggest that a CLB can hold two registered bits. I figure two things: 1. I need a device with at least nRegisterBits/2 CLBs. 2. nRegisterBits/2 is probably grossly optimistic. So my questions are: 1. How do you get a coarse feel for the size of FPGA you need for a design such as this? 2. Do CLBs map 1:1 with registered bits, or per spec 2:1. I was hoping to be able to keep to a sub $50 FGPA, but it's not looking promising. I'd appreciate any advice or pointers from real engineers on how to go about selecting the right device. Thanks, Paul.Article: 69709
Aniket Naik <aniket@tifrpune.res.in> wrote in message news:<Pine.LNX.4.44.0405181824410.6377-100000@tifrpune.res.in>... > Hi, > > I have instantiated a dual port block ram through coregen with a 128 bit > write only port and a 32 bit read only port. > > I am using chipscope to debug the FPGA and when I view all signals > connected to ram, all write port signals are correct, but the data read > out from read port is sometimes correct, and other times it is garbage > data. > > Could somebody suggest a solution to this problem. > Is it a timing problem? (the frequency of operation is low around 10 Mhz) Possibly not the same problem, but I've seen issues recently with a Core Gen RAM not being synthed properly by XST. I switched over to Synplify and the problem disappeared.. My faith in XST is limited! Cheers, JonArticle: 69710
td@emu.com (Tony Dean) wrote in message news:<33aa9b10.0405171520.7798497d@posting.google.com>... > I want my master input clock, which is on a dedicated pin, to clock > most of my logic through a BUFG. I also want it to drive a CLKDLL so I > can use the CLK90 output. > > After much head-banging I assert the following: > On a Spartan IIE, an IBUFG output cannot be routed to both a CLKDLL > input AND a BUFG input simultaneously. This seems strange because I just tried this on a Spartan II (not E) with Foundation Schematics and it does let me connect the IBUFG to both a DLL and a BUFG. I verified this in the FPGA Editor. Unfortunately the Foundation tools don't support the Spartan IIE so I tried the same thing with ISE 6.1i and found that it won't allow the dual connection for the Spartan II as well as the IIE. That tells me that the tools are doing this to you, not the part. I suggest opening a web case with Xilinx > > Synplicity will synthesize this setup beautifully, but the Xilinx > Placer won't accept it. > > Yes, I know I could use the CLK0 output through a BUFG instead of my > original clock, but my input clock can change speeds abruptly, which > will cause the CLKDLL to unlock and exhibit undefined behavior until > relocked. This makes me nervous and I'd rather just use my original > input, thank you. > > A double mocha to he or she who can disprove my assertion. > > -tdArticle: 69711
Paul Marciano wrote: > Hi, I am learning Verilog with a mind to implementing a simple 1980s > style video generator, hooked up to a W65C02S microprocessor. Very > 80s. > > The processor interface will have a dozen or so 8-bit registers, and > the memory interface at least a 16-bit memory address register, some > state registers and a few counters. > > The VGA timing interface will have a couple or three counters. > > As you can instantly tell, it hasn't been thought through yet. This > is day two of my "do something concrete" plan. > > > In looking at FGPA specifications on the XILINX site, I see gate > counts and CLB counts. The specs suggest that a CLB can hold two > registered bits. I figure two things: > > 1. I need a device with at least nRegisterBits/2 CLBs. > 2. nRegisterBits/2 is probably grossly optimistic. > > So my questions are: > 1. How do you get a coarse feel for the size of FPGA you need for a > design such as this? > 2. Do CLBs map 1:1 with registered bits, or per spec 2:1. > > I was hoping to be able to keep to a sub $50 FGPA, but it's not > looking promising. I'd appreciate any advice or pointers from real > engineers on how to go about selecting the right device. > > > Thanks, > Paul. Hi! Each logic element holds basicaly a DFF and a 4 input LUT, meaning that you can make any logic that uses a single FF and some logic with max 4 inputs. They do have also a carry chain, meaning that a simple counter will use one logic element per bit. Each Xilinx CLB has two o these. Each ALTERA LE is one of these. Gate count is useless. For your registers, donīt forget the embedded ram blocks. Both ALTERA Cyclone and XILINX SpartaIIe should achieve what you want at arround $20 a single FPGA chip (Digikey price for XILINX, Arrow price for ALTERA). The best option to have it selected is, usually, take ALTERA QUARTUS or XILINX WEBPACK, make a first version and see where it fits. Double it to have plenty of room for ajustments corrections and improvements. If it were a product, choose the smallest not so tight device for production. Hope to have helped... RicardoArticle: 69712
rajes_kumar@yahoo.com (Rajesh Murugesan) wrote in message news:<5b293f11.0405172336.39ea9f62@posting.google.com>... > Hi all, > > In my design, DLL is used to multiply the input frequency at the > factor of 2. Since the input source clock is from the external PLL > (Generates 2 different frequency---Change in input frequency), a > manual reset is mandatory. When I tried to generate an INTERNAL SIGNAL > and mapped to the reset signal (RST) of the DLL, there were errors as > mentioned below: > > ERROR:NgdBuild:455 - logical net 'rst_in' has multiple drivers. The > possible > drivers causing this are: > pin G on block XST_GND with type GND, > pin PAD on block rst_in with type PAD > ERROR:NgdBuild:466 - input pad net 'rst_in' has illegal connection. > > Would the design implementation in FPGA allow the user to map an > internally generated reset signal to the reset signal of the DLL? > > Tool: Xilinx ISE 6.2i > > Device: Spartan XC2S200 > > Eagerly waiting for your suggestions.. > > Thanks in advance > > Regards > Rajesh I have the same requirement and have successfully generated a reset signal for the CLKDLL, so I know it can be done. It looks something like this: dll : CLKDLL port map ( CLKIN => clk, CLKFB => clkfb, RST => dll_reset, etc. ); dll_reset <= error1 OR error2; -- error1, error2 generated by internal logic Good luck! -tdArticle: 69713
Hi Rajesh, I wonder if net 'rst_in' has multiple drivers? Have you checked your code to make sure you're not driving it to '0' as well as driving it from your input? cheers, Syms. "Rajesh Murugesan" <rajes_kumar@yahoo.com> wrote in message news:5b293f11.0405172336.39ea9f62@posting.google.com... > ERROR:NgdBuild:455 - logical net 'rst_in' has multiple drivers. The > possible > drivers causing this are: > pin G on block XST_GND with type GND, > pin PAD on block rst_in with type PAD > ERROR:NgdBuild:466 - input pad net 'rst_in' has illegal connection.Article: 69714
Paul Marciano wrote: > Hi, I am learning Verilog with a mind to implementing a simple 1980s > style video generator, hooked up to a W65C02S microprocessor. Very > 80s. That would be just few PALs ;-) > The processor interface will have a dozen or so 8-bit registers, and > the memory interface at least a 16-bit memory address register, some > state registers and a few counters. > > The VGA timing interface will have a couple or three counters. > > As you can instantly tell, it hasn't been thought through yet. This > is day two of my "do something concrete" plan. Have a look at www.fpgacpu.org. Jan Gray put a 16bit RISC,DMA,MemoryControl & Video in a chip which is so small, it isn't even supported by xilix tools anymore ;-) Just as an idea how to do things ... > In looking at FGPA specifications on the XILINX site, I see gate > counts and CLB counts. The specs suggest that a CLB can hold two > registered bits. I figure two things: If you're new to this FPGA business, forget about it at the beginning. > I was hoping to be able to keep to a sub $50 FGPA, but it's not > looking promising. You look fine, as long as you talk about $50 for the FPGA alone. > I'd appreciate any advice or pointers from real > engineers on how to go about selecting the right device. Just start with your design, and look the place & route statistics. Then you really get a feeling what resources you use on what function, and probably you even notice, that you implement it in a not so efficient way for an FPGA. And as soon you have some solid design, you still can run the place & route on different families & chips, then you really see what the difference is. Hope it helps at least a little, good luckArticle: 69715
The ratio of LUTs to flip-flops depends heavily upon your design. For
current xilinx FPGAs, there are two flip-flops per slice, and either two
or four slices per CLB (two for virtex, 4 for virtex2). Even the
smallest FPGAs (XC2S15) have sufficient resources for a simple video
text display generator if you are clever with the design (eg, be smart
about the load values for the counters to make the decodes easy, as in
not requiring a full decode of the counter). Depending on the size of
your page and which FPGA you use, you may need some external RAM for the
page memory.
Count the register bits in the design. Look at each register and take a
swag at the number of inputs to the logic leading up to that register
and map that to 4 input logic cells. Anything with less than 4 inputs
is free, as it comes with the register. stuff with more than 4 inputs
that is not arithmetic (add/subtract) adds another LUT for each 4
inputs. With that you can get a fair guess at the number of LUTs and
FF's needed. It is easier to let the synthesis tool do it for you if
you've gotten far enough on the design.
> So my questions are:
> 1. How do you get a coarse feel for the size of FPGA you need for a
> design such as this?
> 2. Do CLBs map 1:1 with registered bits, or per spec 2:1.
>
> I was hoping to be able to keep to a sub $50 FGPA, but it's not
> looking promising. I'd appreciate any advice or pointers from real
> engineers on how to go about selecting the right device.
>
> Thanks,
> Paul.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69716Getting back to FPGA's after some years (Xact 6 days), I downloaded the Webpack 6.1, and the ISE6 in depth tutorial. Following along, everything seems fine, except when it asks me to use CoreGen. After looking for a while it seems, according to Xilinx web site, that CoreGen is not included in the free version. It would be nice if the tutorial explained that, but I found the already generated files in the watchver directory, so I could continue. I am trying to do a "proof of concept" for a new design, somewhat based on the previous one. If it works, the company that will actually build it will have the full version, but I don't have that. I am not sure yet if I will need CoreGen or not. One question now. Does CoreGen allow user supplied cores, or only Xilinx supplied ones? For Xact, I used RPM's, macros hand designed using the cell editor, and substituted at place and route time for dummy cells in the verilog code. Other than that, the most complicated logic block is a RAM or ROM, though I don't know if I can do that without CoreGen. It would be nice if at least simple CoreGen cores were included in the free version. -- glenArticle: 69717
The Coregen tool - in my humble opinion - is generally a dummies guide to the Xilinx Library primitives. I find that instantiating my own memories, DCMs and the such are much better done by reading up on the primitives and doing a manual instantiation. You shouldn't need Coregen - which currently only produces Xilinx-specific modules if I recall correctly - to do a proof of concept for the design. "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:NOvqc.113406$Ik.9242773@attbi_s53... > Getting back to FPGA's after some years (Xact 6 days), > I downloaded the Webpack 6.1, and the ISE6 in depth tutorial. > > Following along, everything seems fine, except when it > asks me to use CoreGen. After looking for a while it seems, > according to Xilinx web site, that CoreGen is not included > in the free version. > > It would be nice if the tutorial explained that, but I > found the already generated files in the watchver directory, > so I could continue. > > I am trying to do a "proof of concept" for a new design, > somewhat based on the previous one. If it works, the > company that will actually build it will have the full version, > but I don't have that. I am not sure yet if I will need > CoreGen or not. > > One question now. Does CoreGen allow user supplied cores, > or only Xilinx supplied ones? For Xact, I used RPM's, > macros hand designed using the cell editor, and substituted > at place and route time for dummy cells in the verilog code. > Other than that, the most complicated logic block is a > RAM or ROM, though I don't know if I can do that without > CoreGen. > > It would be nice if at least simple CoreGen cores were > included in the free version. > > -- glen >Article: 69718
> Looks like a neat device from the press release. > > It's too bad I have no idea what the part number or ballpark price might > be Don't know what the OKI part number is, but the CompXs device is the CX1540. For pricing, contact: sales@CompXs.com Cheers, JonArticle: 69719
Jim Granville wrote: <snip> > There are a LOT of Arm cores comming as MCU, with on chip FLASH, and > that solves the smaller-memory end, by removing the memory BUS layout > problems. > > Look at Philips LPC2xxx, STm STR7xxx, Analog Devices ADuC7xxx, TIs > TMS470, Sony, etc for FLASH+ARM offerings, many with external memory > interfaces. .. I should have included Motorola's MAC7100 ARM devices, TQFP144, 512KF, 32KR, Automotive specs.. -jgArticle: 69720
John_H wrote: > The Coregen tool - in my humble opinion - is generally a dummies guide to > the Xilinx Library primitives. I find that instantiating my own memories, > DCMs and the such are much better done by reading up on the primitives and > doing a manual instantiation. > You shouldn't need Coregen - which currently only produces Xilinx-specific > modules if I recall correctly - to do a proof of concept for the design. The design is pretty specifically Xilinx, so I am not so sure about that, yet. If I can manually get to the library primitives, that should be enough. I haven't reached that point in the manual yet. Can I make my own primitives, like RPMs in Xact? That is more important. -- glenArticle: 69721
I am having problem with my NIOS Stratix Board. I am not able to download just my own, simple, compiled VHDL code onto the Stratix FPGA. The device is EP1S10F780C6ES. After JTAG (ByteBlaster) download finishes, the board resets and MAX configuration-device loads Stratix with the default configuration stored in the on-board FLASH memory (which is a NIOS based server thingy). I tried loading to the FLASH and that failed too. Any ideas ?Article: 69722
I am using an OPB_gpio for the push buttons with an interrupt on a Memec eval board. We see the interrupt when we press one of the buttons (an led blinks for 1/2sec when interrupt line to the processor goes high and sw jumps to the int routine). The GPIO has a read and toggle status register that we are supposed to hit to clear the interrupt on the service routine. The problem seems to be that the write and toggle bit does not work. When the interrupt happens- it cannot be cleared. I know that the GPIO bits are no longer toggling- so this should clear. We have the GPIOs configured for all input. Anyone else have this issue?Article: 69723
Run the input clock to to clock pins. On one, use the CLKDLL. On the other, use the IBUFG. (You didn't say you needed that other clock pin for something else :-). Tony Dean wrote: > I want my master input clock, which is on a dedicated pin, to clock > most of my logic through a BUFG. I also want it to drive a CLKDLL so I > can use the CLK90 output. > > After much head-banging I assert the following: > On a Spartan IIE, an IBUFG output cannot be routed to both a CLKDLL > input AND a BUFG input simultaneously. > > Synplicity will synthesize this setup beautifully, but the Xilinx > Placer won't accept it. > > Yes, I know I could use the CLK0 output through a BUFG instead of my > original clock, but my input clock can change speeds abruptly, which > will cause the CLKDLL to unlock and exhibit undefined behavior until > relocked. This makes me nervous and I'd rather just use my original > input, thank you. > > A double mocha to he or she who can disprove my assertion. > > -tdArticle: 69724
Vadim, make sure that you have the Unused Pins for your Quartus project set to be Inputs Tristated. You can do this as follows after the project is opened in Quartus: 1. Click on Assign Device 2. Click on the Device and Pin Options Button 3. Click on the Unused Pins Tab. 4. This should be the first Radio button. Hope this helps. - Subroto Datta Altera Corp.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z