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Clark, Thank you for your reply. I will try your suggestion hoping it will work fine in my case too. Regards, Andrea SabatiniArticle: 78251
If I'm not using a vendor's board like memec, could I use the Basic System Builder? If so, which module should be edited after using BSB? I just know .ucf file, does any other file should be edited? thxArticle: 78252
Antti Lukats wrote: > Hi Jim, > > any more about this lattice info I mean of what you can say ;) > > I have a bit more about PA3, there: > > <http://www.openchip.org/mambo/index.php?option=com_content&task=view&id=12&Itemid=1> > > the OOPS with PA3 is that the blockRAM can not be used as ROM, no init from config, and that the FROM (1k flash array) is not writeable from FPGA only from ext JTAG > > and MAX2 has no BlockRAM, so interesting what the Lattice thing will be, and what OOPses are there > > Antti They are called XP devices...looks like EC with integrated flash memory for configuration...have some presentation around which I received last November.. rickArticle: 78253
Hello.. Is there a tool which can generate binary files for EPCS memories? Quartus programmer doesn't generate them...only on-the-fly when programming EPCS or compatible devices... rickArticle: 78254
Hi Rudi for iMpact: install 3 jumpers in JP14 fixes CRC error during Download. for ChipScope wait for ChipScope bugfix !!! ChipScope just doesnt work :( <http://openchip.org/mambo/index.php?option=com_content&task=view&id=13&Itemid=2> AnttiArticle: 78255
I want to map an RTL which synthesize on Synopsys Design compiler on FPGA (Synplify is the tool and Xlinx is the FPGA I want to use for mapping) The issue is that this unit uses Synopsys Designware components (FIFO controller, counters and 8b10b enc / dec) What is tyhe safest and fastest path to migrate this design on Sinplify? Thanks in advanceArticle: 78256
Sean wrote: > >I have a 3.3V-LVPECL-clock source, which I need to connect to > a global clock pin that is inside a bank powered with VCCO=3.3V. > If driving a Xilinx 2.5V LVPECL input from an external 3.3V LVPECL driver, there's a good chance the driver output swings will exceed the specified Xilinx input common mode range- I'd either AC couple with a bias network (for a continuous clock) or use a resistive level shifter. Besides XAPP696, see also: - Answer Record 16830 - http://www.onsemi.com/pub/Collateral/AN1568-D.PDF > >But is the IBUFDS_LVPECL_25 really 2.5V, even if it resides > in a bank powered with 3.3V? <snip> >Is this because differential input buffers are powered by VCCAUX, >which is 2.5V, regardless of the bank's VCCO? > Yes to both, according to Answer Record 16830. (note, I haven't verified this myself on a V2Pro) Symon wrote <re. _DT terminators in a 3.3V bank> > > Please let me know if you get an answer! Check out these CAF threads > Check out the recently updated Answer Record 17244 ( no damage, sorta works but lower impedance) BrianArticle: 78257
hi I maybe have to take my prev message, partially - i used EDK+Chipscope design for testing so USER1 was used by MDM, and as of V4LX25 errata USER2 is not available, so Chipscope might still be useable in designs where MDM is not utilized eg USER1 is free. But I have not yet verified this.Article: 78258
Jedi wrote: > Hello.. > > > Is there a tool which can generate binary files for EPCS memories? > > Quartus programmer doesn't generate them...only on-the-fly when > programming EPCS or compatible devices... > > > rick > Stupid me (o; It's just .rpd file bit-reversed (o; never mind (o; rickArticle: 78259
confirmed: chipscope can be used, in case the PLD is added to chain (the 3 jumpers fix in V4LC board) when bitstream is loaded with impact and chipscope ICON sits on BSCAN/USER1. downloading with chipscope does not work, simultanuous use of MDM and Chiscope in EDK doesnt work. anttiArticle: 78260
Gabor wrote: > Jim Granville wrote: > > nathan wrote: > > > The 60Hz is a square wave output from an opto-isolator. It rises > from > > > 0.6V to 4.7V in 110 microseconds. Is that fast enought? > > > > No, typically 10-20ns is spec, but upto around 150ns is tolerated. > > Can you change the opto to a schmitt model ? > > -jg > > I've been following this thread for a while and still can't figure > out why Nathan really wants to use 60 Hz as a clock signal rather > than using some higher frequency to sample and debounce it. I never > saw a reply to Dan's post on what else is inside the CPLD that would > warrant using the part in the first place. Clearly if all you had > was a 4 bit count at 1 Hz, you could do the whole job in the > cheapest 8-pin PIC micro (PIC12C508 comes to mind) which has an > internal 4 MHz oscillator and requires almost no external parts > (just decoupling caps). > > So if the CPLD has something else going on, what is the rest clocked > with, and if not why use a CPLD at all? It's something I'm doing for fun. I built a circuit to run my Nixie tube clock but it used about 12 ICs. They were all counters used for either dividing or 4 bit counters for the numbers. My goal is to have the least amount of ICs/discretes and do it with a CPLD. This is my first time using programmable logic. (I have used a 68HC11 before) To save on complexity and parts, I thought I'd use the line frequency from the wall for my clock. I had a schmitt previously hooked up to the 8VAC output from a transformer. It had issues with ground. I'll try hooking the opto-isolator output to the the schmitt and see how that goes.Article: 78261
On 27 Jan 2005 07:30:35 -0800, "nathan" <nathan_wilson@hotmail.com> wrote: > >Gabor wrote: >> Jim Granville wrote: >> > nathan wrote: >> > > The 60Hz is a square wave output from an opto-isolator. It rises >> from >> > > 0.6V to 4.7V in 110 microseconds. Is that fast enought? >> > >> > No, typically 10-20ns is spec, but upto around 150ns is tolerated. >> > Can you change the opto to a schmitt model ? >> > -jg >> >> I've been following this thread for a while and still can't figure >> out why Nathan really wants to use 60 Hz as a clock signal rather >> than using some higher frequency to sample and debounce it. I never >> saw a reply to Dan's post on what else is inside the CPLD that would >> warrant using the part in the first place. Clearly if all you had >> was a 4 bit count at 1 Hz, you could do the whole job in the >> cheapest 8-pin PIC micro (PIC12C508 comes to mind) which has an >> internal 4 MHz oscillator and requires almost no external parts >> (just decoupling caps). >> >> So if the CPLD has something else going on, what is the rest clocked >> with, and if not why use a CPLD at all? > >It's something I'm doing for fun. I built a circuit to run my Nixie >tube clock but it used about 12 ICs. They were all counters used for >either dividing or 4 bit counters for the numbers. My goal is to have >the least amount of ICs/discretes and do it with a CPLD. This is my >first time using programmable logic. (I have used a 68HC11 before) To >save on complexity and parts, I thought I'd use the line frequency from >the wall for my clock. > >I had a schmitt previously hooked up to the 8VAC output from a >transformer. It had issues with ground. I'll try hooking the >opto-isolator output to the the schmitt and see how that goes. At that low freq you should be able to simulate a schmidt by feeding the signal back out of an output and resistively coupling it to give a small amount of positive feedback.Article: 78262
AdamS wrote: > I couldn't find the "what's new" in Xilinx's web. > could anyone tell me? thanks^_^ Changes in microblaze, 3.00.a microblaze, 3.00.a - Changes in VHDL sources (.vhd) -------------------------------------------------------------------------------- New revision. Adds exception support: unaligned access, illegal instruction, I/D bus error, divide by 0. Adds FSL based cache-link memory interface.Article: 78263
> > The reason I keep resorting to emulating the IWM and 8390 is
because
> > I'd like the thing to be able to boot MacOS when I'm done.
>
> I reckon you need to start with a working Mac board and replace one
PAL at a
> time.
I too would suggest doing this so you don't have to worry about the IWM
until you are done with the rest. If everything else is known to work
except for a single part you have replaced, debugging will be far
easier and faster.
Today I looked through the back ups of my old floppy disks (copied to
the HD of a Classic II about a year ago. Those that could still be
read, that is, which wasn't the case for over half of them) to see if I
happened to have a copy of the simulations I had done. Unfortunately my
only LogicWorks files seem to be a part of the DMA circuit for the
original PC and a test of a Manchester encoder/decoder design.
A file called "PALs" from the MacWrite floppy seemed promising, but it
turned out to be original version that I had scanned in on Monday
(before being scribbled on, of course). The only interesting thing
about it is that it includes an additional PAL ("PAL5 - Analog Signal
Generator") that is missing from the printed version. There is an odd
comment that this is a 16R8 and the original was a 16R6. The equations
look like wild guesses, more to illustrate the general shape that this
PAL should have and we decided that it wouldn't have to be changed and
so I wouldn't worry about it anymore.
Too bad I don't have any convenient way of transferring this to my more
modern machines so I could post this file as well - though it is rather
short I don't have the time to retype it right now.
Article: 78264"Brian Davis" <brimdavis@aol.com> wrote in message news:1106838032.079432.105830@z14g2000cwz.googlegroups.com... > Sean wrote: > >Is this because differential input buffers are powered by VCCAUX, > >which is 2.5V, regardless of the bank's VCCO? > > > Yes to both, according to Answer Record 16830. > (note, I haven't verified this myself on a V2Pro) > > Symon wrote <re. _DT terminators in a 3.3V bank> > Check out the recently updated Answer Record 17244 > ( no damage, sorta works but lower impedance) > Thanks Brian! I wonder, is there an email notify thingy when a specific answer record changes? So, as it happens, I know that _DT works on 3.3 Vcco banks to some extent because I tried it on a prototype. I bottled out on the real thing and put a level shifter in for the single ended signals and made it a 2.5 Vcco bank. It still begs the question as to why Xilinx were able to power the differential input from Vccaux, but not the differential termination gizmo. If only they were perfect like what I am. ;-) Thanks again, Syms.Article: 78265
My plan was to replace one IC at a time, I just think ahead of mysefl. Making a plan. ;) I've got a mac plus on the bench booting off of a ZIP drive. It was dead for a while, it had one 256k SIMM with the 1MB. The computer will also not boot without a disk drive attached. There might be a sense pin to short, But I'm not going to worry about that. I've captured a few logic patterns so far. On the opening screen with the happy mac I was able to capture about one full frame worth of video. That's around 430,000 samples at 10ns. I was just testing the equipment. Once I get decent info from the PALs I'll post it. Is there a chance that the floppy included the full report? :) I will scan the 21 pages from the BYTE magazine when I get them in the mail. GrantArticle: 78266
I have found that I must take special care with CPLDs, especially the 7000s Altera that I worked with. They root a lot easier if I allowed the compiler/placer to choose the pins. FPGAs I found much easier. I use a lot of Cyclone 1C3 and 1C6 QFP packages and I haven't found any problems with wayout layouts. Victor Schutte http://www.zertec.co.za <usrdr@yahoo.co.uk> wrote in message news:1106820658.378210.250960@z14g2000cwz.googlegroups.com... > hello everbody, > While drawing new scheme with FPGA or CPLD, Must I care about pin sort? > Like as Macrocell 1 should control RAM and Macrocell 7 should control > SPI? What should I care about new design? >Article: 78267
ispXPGA? those are "old" stuff it was available long time before EC/ECP was announced, I did think jg was referring something new, eg not-announced lattice product... anttiArticle: 78268
depends what board you use and what ip cores you include. in the best case changing the .ucf and selecting correct fpga part is all that is needed. try getting some minimal system, gpio leds? working then add other peripherals... anttiArticle: 78269
I think that refdesign in question was included in some earlier EDK versions! in 6.3 it seems to be taken out, I looked myself to for it. anttiArticle: 78270
Victor Schutte wrote: > I have found that I must take special care with CPLDs, especially the 7000s > Altera that I worked with. They root a lot easier if I allowed the > compiler/placer to choose the pins. > Another way to put this is never draw the schematic before you've done at least one pass on the CPLD code and fit it into the part. It's been a while since I've last done design with CPLD's but in the old days the big issue was routing signals between the blocks. If you can fit a design such that each block of I/O's has unused connections to the global routing pool, you'll be less likely to require pinout changes if you need to update the logic. I think newer parts have a little more flexibility such as programmable routing between the macrocells and the I/O's, and some "CPLDs" are just small FPGAs with instant load from flash. But I think its still a bad idea to design a CPLD into a board before designing the internals. > FPGAs I found much easier. I use a lot of Cyclone 1C3 and 1C6 QFP packages > and I haven't found any problems with wayout layouts. > I rarely have the luxury of designing FPGA internals before the board schematic. I usually design the FPGA guts while the board is in layout and fabrication. Usually I find no problems with pin assignments, but I have been burned when using some of the advanced I/O features of Virtex 2. In particular you need to watch out for differential signal pairing requirements and also IOB clock routing. When you use DDR flip-flops in these parts (and I imagine Spartan 3 is similar) pairs of IOB's share some clock routing resources making it impossible for example to use one IOB in a pair for the DQ of DDR SDRAM and its partner for a DQS. The shared routing resources use the same pairing as the differential I/O. > > Victor Schutte > > http://www.zertec.co.za > > <usrdr@yahoo.co.uk> wrote in message > news:1106820658.378210.250960@z14g2000cwz.googlegroups.com... > > hello everbody, > > While drawing new scheme with FPGA or CPLD, Must I care about pin sort? > > Like as Macrocell 1 should control RAM and Macrocell 7 should control > > SPI? What should I care about new design? > >Article: 78271
Andy Luotto wrote:
> I want to map an RTL which synthesize on Synopsys Design compiler on
> FPGA (Synplify is the tool and Xlinx is the FPGA I want to use for
> mapping)
>
> The issue is that this unit uses Synopsys Designware components (FIFO
> controller, counters and 8b10b enc / dec)
>
> What is tyhe safest and fastest path to migrate this design on
> Sinplify?
>
> Thanks in advance
>
Hi Andy,
Xilinx offers a rich suite of LogiCore IP which are delivered
through the Xilinx CORE Generator, and included with your ISE
installation. You can then instantiate the generated cores into
your design. We have solutions for all of the elements you
mention. To access them from CORE Generator:
Basic Elements -> Counters -> Binary Counter
Communication & Networking -> Building Blocks -> Decode 8b/10b
-> Encode 8b/10b
Memories and Storage Elements -> FIFOs -> Fifo Generator
You can find more information on all of the IP available from our
IP Center:
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Intellectual+Property
I hope this helps-
-Stacey
Article: 78272Has anybody datasheet of XC4005-6PQ160C or XC4000 seria? Thanks for link or sending ... Simon (c-aza@c-mail.cz)Article: 78273
Has anybody complete example of pci core implementation to XC4013E or 4000E? Thank You very much.Article: 78274
Antti Lukats wrote: > I think that refdesign in question was included in some earlier EDK versions! in 6.3 it seems to be taken out, I looked myself to for it. > > antti Thanks Antti, I already got it. I contacted xilinx web support center and they sent it to me. It seems that EDK 6.2 included it but somehow it was excluded from EDK 6.3. Moti.
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