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Hi, Does someone know where I could find a quartz at 100MHz and 200MHz in a socket DIP8 for the Digilent Spartan3 board? Thank You. AlexisArticle: 78451
I’m wondering if its possible to directly input a 0 – 5 volt logic level signal to a input pin on a Spartan 3?Article: 78452
Elektro wrote: > I’m wondering if its possible to directly input a 0 – 5 volt logic level > signal to a input pin on a Spartan 3? > > Yes you can...you can even input 1000MegaVolts to it...no problem (o; No seriously..the Spartan 3 chips only allow 3.3V IO voltage max. Have you read any datasheets yet? rickArticle: 78453
Elektro wrote:
> I'm wondering if its possible to directly input a 0 - 5 volt
logic level
> signal to a input pin on a Spartan 3?
There have been other threads on this. The short answer is no -
at least not directly. Xilinx says you can use a series resistor
and let the Vcco clamp diode limit the input voltage. Other approaches
include using a MOSFET buffer ("Quickswitch") or a resistor divider.
Also when you say 0 - 5 volt, remember that the output of 5 volt
logic doesn't usually drive to the Vcc rail. CMOS devices like
FCTxxxT indicate "TTL compatible" meaning both input threshold and
output drive. You may be able to get away without a resistor on
these since they can be very wimpy above 3.5 volts, but it's much
safer to put in the resistor in case you get the chip with a slightly
higher Voh or have power-on sequencing issues (5V coming up first).
Article: 78454Hi, Did anybody work on OPB_EMAC xilinx core at 100mbps with PPC405.How did you develop drivers for that?Please let me know. Thanks & Regards, IvanArticle: 78455
Dave wrote: > Hi, > > I am implementing a state machine in a FPGA using VHDL. > Several states are determined by 4 external event inputs (falling > edge) which occur asynchronously to the 25MHz FPGA clock (I might need > to increase to 50MHz). The events occur at random intervals of 10us or > more. > > I have a couple questions which someone may be able to guide me on: > > 1) Should I have a synchroniser (2-stage shift reg) at each of the 4 > event inputs before being sampled by the state machine to avoid > meta-stability problems? At 25 or even 50 MHz, the likelihood of a metastability event on the output of the first synchronizer stage lasting into the setup time of the next clock edge is very low. BUT at least put the asynchronous inputs through one flip-flop. That way the various flip-flops inferred by your state logic will see the same value on the same clock edge. Not doing this is the classic way to create a "zero-hot" or "multiple-hot" condition in a one-hot state machine. If you are worried about that small chance of metastability, by all means use two flip-flops to reduce the chance to near zero (as in not likely to happen in our lifetimes at 25 MHz). > > 2) I'm using the following VHDL code to detect a falling edge on the > event inputs. Is there a better way? > > process( clk, ev1, ev2, ev3, ev4, reset) > variable prev_ev1: std_logic; > variable got_ev1: boolean; > > <variables for other events omitted> > > begin > if (reset = '1') then -- reset the event states > prev_ev1 := event; > got_ev1 := false; > elsif (rising_edge(clk)) then > if (event = '0') then -- event signal is low > if (prev_ev1 = '1') then > got_ev1 := true; -- falling edge detected > end if; > prev_ev1 = '0' > else > prev_ev1 = '1'; > end if; > > <repeat edge detection for the other events> > > <process 'got_ev' flags in state machine & reset them> > end if; > end process; In this case without the input synchronizer, your danger is for prev_ev1 to go active because it saw an event at some clock edge, but got_ev1 staying false because it didn't see the event on the same edge. This way you would miss an event. After a single stage synchronizer this would only happen if the event caused metastability on the output of the synchronizer flip flop lasting into the setup time to the next clock edge, nearly a full cycle of 25 MHz. This is an extremely unlikely event for most FPGA processes, but as I mentioned above you can add one more input stage and reduce the risk further. > > Any advice welcome! > Thanks > DaveArticle: 78456
Hi, What is the usual ratio to know how many gate does a design represent when we get the number of xilinx slice needed?? Regards, AlexisArticle: 78457
kcl wrote: > Hi, > > What is the usual ratio to know how many gate does a design represent when > we get the number of xilinx slice needed?? > > Regards, > > Alexis Here we go again... There have been many discussions on design gate equivalents and how the "gates" in a part relate between manufacturers. You can't really relate the slice count in a design to gates, because the gate count depends on what resources you use from each slice. For example some slices may implement a 4-input lookup that would require several 2-input gates to implement plus a flip-flop which could be built of several more gates. Other slices could implement dual-port RAM that would count as a whole bunch of gates, or a route-through that counts as no gates. At one time the tools reported the equivalent gate count of a design and I have no idea what algorithm they used to get it. I often had designs in an XCV50 that reported 150,000 gate equivalents or three times the supposed gates available in the part. I think most of us have given up on counting gates and let the marketing guys argue over who has more. If you're not planning to move your FPGA design to an ASIC, you probably don't need to know the gate count and if you are moving to an ASIC, I'm not sure the tools will give you an accurate estimate anyway. Good luck, GaborArticle: 78458
Well, I can obviously not speak for Altera ;-) But go to the Xilinx website and either scan the TechXclusives (good stuff!) or search for "metastable" or for my name, and you will find quantitative data, XAPP094 is the best source, but it is being refurbished right now... Peter Alfke, Xilinx ApplicationsArticle: 78459
<<Don't know if my previous posting made it out...>> Vasus_ss, Aldec's simulators (http://wwww.aldec.com) is the only tool I know of that can functionally verify EDIF netlists. I whish they also did formal verification and linting... *** Alfredo vasus_ss@yahoo.co.in wrote: > Hi all, > > I was given an EDIF netlist for evaluation of IP core. I could > synthesize it and see and everything. But i am unable to check > functional simulation of the core as to how it works. Is there any way > to do it with Modelsim and Xilinx tools > > thanks in advanceArticle: 78460
There isnt anyway to 'reverse engineer' the edif netlist to see what the original vhdl looked like using modelsim if thats what you mean.The best you can hope for is to look at the data flow of the edif to vhdl writer produced vhdl which isnt going to be easy and thats basically the whole idea.Article: 78461
On Tue, 01 Feb 2005 03:07:59 -0800, vasus_ss wrote: > Hi all, > > I was given an EDIF netlist for evaluation of IP core. I could > synthesize it and see and everything. But i am unable to check > functional simulation of the core as to how it works. Is there any way > to do it with Modelsim and Xilinx tools > > thanks in advance You can convert the EDIF to a Verilog file. If you received an ngc file then you can do an ngc2hdl. If you received and edif then you have to do two steps, edif2ngd followed by ngd2ver.Article: 78462
Dear Mr Tschaggelar, let us assume the following situation: I have an 16bit bus which is synchronous to an external clock 30MHz. If I sychronize this bus with a set of three stage-flip flop-chains clocked by an internal generated 90MHz clock will the sampled pattern be wrong? I do not know if you were talking about asynchronous bus without any clock or if you were talking about asynchronous bus with regard to the FPGA internal sampling clock. Thank you for sheding some light on it. Best regards André >>ALuPin wrote: >> In one of the last posts I read the following: >> >>>It is true though that a more common mistake is to synchronize a >>>multibit bus without realizing that this will result in invalid values >>>except in the case of Gray-coded logic. >> >> Does that mean that using a multi-stage flip flop chain to synchronize >> the asynchronous input bus will lead to invalid values ? >Since the indivdual bits of the multi bit bus may change at >their own time, sampling at odd intervals may result in >sampled bus pattern that are just temporary in nature. >Thus the sampled pattern may be wrong. >Only the gray code is save to sample at odd intervals as >only one-bit changes are allowed. > >Apart from that, the multi bit bus could also contain its own >clock, showing when the data is valid. > >Rene >-- >Ing.Buero R.Tschaggelar - http://www.ibrtses.com >& commercial newsgroups - http://www.talkto.netArticle: 78463
vasus_ss@yahoo.co.in wrote: > Hi all, > > I was given an EDIF netlist for evaluation of IP core. I could > synthesize it and see and everything. But i am unable to check > functional simulation of the core as to how it works. Is there any way > to do it with Modelsim and Xilinx tools > > thanks in advance > Your synthesizer probably gives you the option of creating an HDL netlist. You may use this for a post-synthesis simulation.Article: 78464
"> I think most of us have given up on counting gates and let the > marketing > guys argue over who has more. yes marketing guy what we couldn't do without them ^^ If you're not planning to move your FPGA > design to an ASIC, you probably don't need to know the gate count and > if you are moving to an ASIC, I'm not sure the tools will give you an > accurate estimate anyway. > No it's not to move from a fpga to an asic , it's just for my resume i wanted to indicate the size in gate of an IP I developped during my internship AlexisArticle: 78465
kcl wrote: > "> I think most of us have given up on counting gates and let the > > marketing > > guys argue over who has more. > > yes marketing guy what we couldn't do without them ^^ > > > If you're not planning to move your FPGA > > design to an ASIC, you probably don't need to know the gate count and > > if you are moving to an ASIC, I'm not sure the tools will give you an > > accurate estimate anyway. > > > > No it's not to move from a fpga to an asic , it's just for my resume i > wanted to indicate the size in gate of an IP I developped during my > internship > I see, so it's marketing after all :) By all means use the largest number you can find! > AlexisArticle: 78466
Okay..no answer yet from Altera support...probably never will be (o; At least before they answered with "contact your local FAE" (o; rick Subroto Datta wrote: > Yes Petter, I meant the Windows platform, in my initial reply. > > - Subroto Datta > Altera Corp. > > <newsmailcomp5@gustad.com> wrote in message > news:kjupszmu4ql.fsf@shardlow.dolphinics.no... > >>"Subroto Datta" <sdatta@altera.com> writes: >> >> >>> Quartus II 4.2 allows for multiple installations to co-exist on a >>>computer. Prior versions of Quartus II i.e 4.1 and earlier allowed only a >>>single installation to exist on a computer at any one time. When you >>>install >> >>That must be under Windows. I have all the following versions >>installed under Linux: >> >>quartus2-2.1 >>quartus2-2.1sp1 >>quartus2-2.2 >>quartus2-2.2sp1 >>quartus2-2.2sp2 >>quartus2-3.0 >>quartus2-3.0sp1 >>quartus2-3.0sp2 >>quartus2-4.0 >>quartus2-4.0sp1 >>quartus2-4.1 >>quartus2-4.1sp2 >>quartus2-4.2 >> >>I guess the problem under Windows is the global registry. >> >>Petter >>-- >>A: Because it messes up the order in which people normally read text. >>Q: Why is top-posting such a bad thing? >>A: Top-posting. >>Q: What is the most annoying thing on usenet and in e-mail? > > >Article: 78467
How can you get ModelSim to print the wave window in color? I tried printing to a color printer and only got BW. Thanks, JTArticle: 78468
There seems to be a misconception that you can Gray-code any bus. Not true. Gray-coding applies only to counters, where it guarantees that only one bit changes on any transition. There is no "general purpose" Gray coding ... Peter Alfke, Xilinx ApplicationsArticle: 78469
ALuPin wrote: > let us assume the following situation: > > I have an 16bit bus which is synchronous to an external clock 30MHz. > If I sychronize this bus with a set of three stage-flip flop-chains > clocked by an internal generated 90MHz clock > will the sampled pattern be wrong? > > I do not know if you were talking about asynchronous bus without any clock > or if you were talking about asynchronous bus with regard to the FPGA internal > sampling clock. Andre, The "Moving Data Across Asynchronous Clock Boundaries" article by Peter Alfke shows how to synchronize a bus by implementing a simple handshake protocol. http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_clock_bound HTH, -- GeorgiArticle: 78470
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0502010803.7714b29d@posting.google.com... > Dear Mr Tschaggelar, > > let us assume the following situation: > > I have an 16bit bus which is synchronous to an external clock 30MHz. > If I sychronize this bus with a set of three stage-flip flop-chains > clocked by an internal generated 90MHz clock > will the sampled pattern be wrong? > > I do not know if you were talking about asynchronous bus without any clock > or if you were talking about asynchronous bus with regard to the FPGA > internal > sampling clock. > > Thank you for sheding some light on it. > > Best regards > André > >>>ALuPin wrote: >>> In one of the last posts I read the following: >>> >>>>It is true though that a more common mistake is to synchronize a >>>>multibit bus without realizing that this will result in invalid values >>>>except in the case of Gray-coded logic. >>> >>> Does that mean that using a multi-stage flip flop chain to synchronize >>> the asynchronous input bus will lead to invalid values ? > >>Since the indivdual bits of the multi bit bus may change at >>their own time, sampling at odd intervals may result in >>sampled bus pattern that are just temporary in nature. >>Thus the sampled pattern may be wrong. >>Only the gray code is save to sample at odd intervals as >>only one-bit changes are allowed. >> >>Apart from that, the multi bit bus could also contain its own >>clock, showing when the data is valid. >> >>Rene >>-- >>Ing.Buero R.Tschaggelar - http://www.ibrtses.com >>& commercial newsgroups - http://www.talkto.net There is no guarnatee that your data will be correct. Your 90Mhz clock is asynchronous to your 30Mhz clock. It doesn't matter how many synchronizing flops you send it through ... if on the first set of flops, 1 bit does not meet the setup time and all the others do ... you will latch the wrong data and this will be propagated through all your other synchronization flops. one technique to solve this issue is to utilize a single bit signal that indicates that data is valid ... send this signal through your synchronizing flops and then when you sample this valid in your internal clock domain ... it guarantees that the data will also be sampled properly. MikeArticle: 78471
kcl wrote: > Hi, > > Does someone know where I could find a quartz at 100MHz and 200MHz in a > socket DIP8 for the Digilent Spartan3 board? http://www.comtec-crystals.com/ But I would suggest that you use the 50MHz clock provided with the board and mutliply it with one of the four DCMs to the frequency of your choice. Kolja SulimmaArticle: 78472
Do not try to find an exotic and expensive oscillator. Go with standard 40 or 50 MHz and use the DCM to give you the desired internal clock rate. Peter Alfke, Xilinx Application kcl wrote: > Hi, > > Does someone know where I could find a quartz at 100MHz and 200MHz in a > socket DIP8 for the Digilent Spartan3 board? > > Thank You. > > AlexisArticle: 78473
Antti Lukats wrote: > confirmed: chipscope can be used, in case the PLD is added to chain (the 3 > jumpers fix in V4LC board) when bitstream is loaded with impact and > chipscope ICON sits on BSCAN/USER1. downloading with chipscope does not > work, simultanuous use of MDM and Chiscope in EDK doesnt work. > > antti I did try that and my in my environment chipscope did NOT work. It only recognized some of the ILA configuration but could not capture any data. Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78474
Hi Niel, Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote: > Rudolph, > > Making the CPLD the last device in the chain should make the issue go > away since the CPLD seems to be able to sample the TDO before is > tristates. I did try that and it did not work with any of the 3 boards I have. > It is also known that the new Platform Cable USB makes this problem go > away because it samples the TDO earlier. Unfortunately that does not work with linux so it's not an option for me at this point. > I believe that Autin indicated that they have another solution that they > have hadd success with in the lab. I think this involved judicious > capacitor selection. He indicated he would supply the details Yes I did receive several emails from Peter, and will try those solutions tomorrow. Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis
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