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Hi Hendra, > I am thinking of building a fully functional mp3 player with an FPGA. I > will appreciate any help if your guys can give me any suggestion. I > want the design to be as original as possible. For example: I prefer to > implement mp3 decoding mechanism inside an FPGA by myself, rather than > purchasing an off the shelf mp3 decoder. My preliminary spec is a > simple mp3 player with an FPGA, USB memory stick, an LCD display, a > keypad and whatever other external components necessary to build a > complete system. > 1. If I use USB memory stick, is it significantly more difficult than > using IDE harddrive? Oh yes. Writing an USB host is definitely not trivial, even if you only write for a bulk-class device like an USB stick. > 2. Where can I download the mp3 specification and algorithm? Is it in > public domain, or is it a copyright secret? There's lots of free implementations. Just Google around a bit. > 3. What kind of other external components needed to implement this > project? Well, a DAC and an amplifier circuit would be good. Then of course there's the switches, LCD connector etc. > 4. Do I need an advanced knowledge in DSP for this project? I have > basic background in DSP, but not at advanced level. To start from scratch I'd say you would. However, if you pick one of the libraries floating around the web I don't think you need a very high degree of DSP technology. I know for a fact that there's a new MP3 player reference design for Altera's NIOS II development kit. The sound is pretty horrible due to the output being generated by a PWM, but if you stick a DAC onto one of the expansion connectors you'd have something workable. The kit comes with a CompactFlash connector so refreshing your song list wouldn't be too hard using a cardreader, and one of the expansion headers could even function as an IDE interface, so an FPGA-based IPod is within grasp ;-) Best regards, BenArticle: 78526
> If I would make a top list for SPI flash it would look like: > > 1. SST > 2. ST > 3. Nexflash > > best regards > rick > > > ps: And still no answer given regarding Atmel making EPCS chips > for Altera (o; > > I certainly have not heard anything about this. Checked out the different alternative. Nexflash is nice due to uniform sector size. All parts seems to have 256 byte pages. It makes it easy to do a FAT file system w 512 B sectors. Fairly low current, both in read (4 mA) and in power down (1 uA) 64 kB Sector erase time sucks greatly - 2 seconds !!! Single RAM page in the device, so you have to wait until the device is ready until you shift in more. Max size 16 Mbit... SST is very quick to program/erase - 70 msa for chip erase. 18 ms for block erase. The 4 kB sectors makes the part harder to use, since it becomes hard to allocate a block for a single data entity. Single SRAM page, byte write is nice. 100 years data retention. Is this to be believed? 33 Mhz operation is also nice. Is only useable for 3.0V-3.6V - No mobiles phones ...(Run at 2.8 V) Anything larger than 8 Mbit? .... ST - 8 Mbit 64 kB Sector erase time is up to 5 seconds (he he he..) Say no MORE... Comparing them to the AT45DB642 (which is several years old) 1056 byte sectors, note: Not 1024: this measn that the extra bytes you need for handling the flash like CRC, erase count etc are inside the sector... Dual SRAM page, which means that you can load in a page, start programming the page and while the programming is in progress you can start loading the next page. 4 mA read current, and 2 uA power down current. 18 ms page programming, but the page size is 4 x Nexflash and they will need to shift in between every programming cycle, so in reality, they are quite close. 18 ms block erase. This is 8 pages or8 kB, so multiply by 8 to get 144 ms per 64 kB block. Obviously it is faster, if you are happy with erasing a block. Lacks byte programming unlike SST. 20 Mhz clock rate is a little low, but it will soon increase to 50 Mhz and the size will also increase to 128 Mbit. I leave it to the reader to draw conclusions. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 78527
Hi, I am working with FPGAs after some time. SO here is a trival question. I downloaded the new webpack 6.3 and ran a simple design to check if things are OKie. I find that I get the following error! --> compiling XilinxCoreLib library > working... ERROR:cxl[lib]:3- file missing 'C:\Xilinx\vhdl\src\XilinxCoreLib\vhdl_analyze_order' compilation aborted. After googling for few hours and downloading the new coregenearator library. I am still where I started! ANybody else with similar problem! help! Thanks, VSRArticle: 78528
VSR wrote: > Hi, > I am working with FPGAs after some time. SO here is a trival question. > > I downloaded the new webpack 6.3 and ran a simple design to check if > things are OKie. > I find that I get the following error! > --> compiling XilinxCoreLib library > > > working... > > ERROR:cxl[lib]:3- file missing > 'C:\Xilinx\vhdl\src\XilinxCoreLib\vhdl_analyze_order' > > compilation aborted. > > After googling for few hours and downloading the new coregenearator > library. I am still where I started! > ANybody else with similar problem! help! > Thanks, > VSR I have this file on my system, but I'm running FOundation ISE, not the WebPack version. I though WebPack didn't come with COREgen, so I'm not sure what point there would be in shipping the XilinxCoreLib library with it. I'm assuming it needs this for simulation? A typical VHDL file in this directory has the following header comments: -- Description: -- Compontent declaration -- Asynchronous FIFO Simulation Model The file you're missing is a list of the source files in C:\Xilinx\vhdl\src\XilinxCoreLib\ So I would check if you even have that directory on your system. If not maybe you're trying to do something that webpack won't do.Article: 78529
Does anybody know what version/servicepack of ISE is required in order to be able to do static timing analysis of Spartan-3 designs using the Voltage/Temperature pro-rating feature in the timing analyser? Thanks, JeremyArticle: 78530
Hi Vincent, > Here's a question I know has already been asked but I was not > satisfied with the answer. > > How could I get Quartus II to support the FLEX 8000 devices? The FLEX 8000 are 'not recommended for new designs', and have had this status for a much longer time than the FLEX 6K and 10Kx series, so support for these beasts was never planned for Quartus, even after they put MaxPlus into maintenance mode. Although I concur that Quartus is a great step ahead from MaxPlus, I don't think MP2 is a bad tool. Okay, the GUI looks pretty clunky, but on the other hand it's fast, doesn't eat up a lot of resources and pretty much does the job. Is there a strong reason for you to keep using the (old, small, slow) 8K series instead of the newer stuff, apart from the fact that you already have a few parts? Best regards, BenArticle: 78531
Jacob Bower wrote: > Hi, > > I'm working on a small research project, for which I'd really like to be able > to modify a post-PAR Xilinx design. Specifically, I'd like to remove routing > information for a single net, add have it rerouted with new timing constraints. > > So far I have come accross two possible ways of realistically doing this, but > they both have problems. There is no need to unroute the net. Just edit the PCF file to change the timing constraint and resubmit the routed NCD to PAR in reentrant mode (-k). There is also a hidden feature that allows you to limit the router to specified nets. Put one or more net names in a file and then set the following environment variable to the file name. Windows: SET RCT_SIGFILE=file_name.txt Linux or Solaris: setenv RCT_SIGFILE file_name.txt Using this feature, you'll be preventing the rip-up and rerouting of other nets that may be necessary for the specified net to meet the new timing constraint, but this sounds like what you are trying to get the router to do. BretArticle: 78532
Wojciech Zabolotny wrote: >Asynchronous Preset and Clear >This is the most problematic register for the ACT 2, XL, DX, MX, SX >and ACT 3 architectures. You can only use one cell (the DFPC cell) to >design an asynchronous preset and clear register. The DFPC uses two >CMODs to form a master latch and a slave latch that together form one >register. This uses two CMODs per register and offers no logic >combinability with the SMOD. The DFPC requires more setup time and no >combinability. The net timing loss can often be as high as 10ns. Actel >recommends that you do not use any asynchronous preset and clear >registers on critical paths. Use a synchronous preset with >asynchronous clear or a synchronous clear register instead. You can >use an asynchronous preset and clear register if it does not affect a >critical path or cause high utilization in the design. >[...] > >Well, if it is impossible to build such flip-flops with the R-cells, >and if the price of RT parts is unacceptable, what are the >alternatives? >Does anybody know if there are some data about radiation hardness of >eg. Altera Hardcopy devices??? I've tried to google them, but found >almost nothing... > > > If you really need asynchronous presets or clears, especially if you need DIFFERENT signals to be these asynch. presets and clears, Xilinx is the only architecture that can handle this. I know they have a line of rad hard parts, too. We have used their parts to implement such oddities as needing several hundred totally asynchronous FFs in a device to delay signals from nuclear particle detectors. At that time, Xilinx was the ONLY device that could implement this, as you could connect the asynch. set and clear, as well as the clock of the flip-flops to any signal on the FPGA. Many other architectures are wired so these inputs can only be tied to some of the global clock or set/reset resources. For normal digital designs, that is adequate, of course. JonArticle: 78533
ivan wrote: > Hi, > > Did anybody work on OPB_EMAC xilinx core at 100mbps with PPC405.How > did you develop drivers for that?Please let me know. > Thanks & Regards, > Ivan I have an Avnet development board with a V2P20 on it. It came with a reference design that has Linux running on the PPC, and uses the OBP_EMAC core to talk to a PHY on the development board. The demo include a simple web sever, and it works. The Linux distribution came from www.denx.de and has an old version of a driver for the Xilinx EMAC core. The driver was written by MontaVista. There is a newer version of the driver available in the bitkeeper repository for the PPC version of the kernel. Look at www.klingauf.com/v2p/index.phtml for information on how to get the kernel, and other good info. Also check out www.penguinppc.org John McCaskillArticle: 78534
Hi Che Fong, Core logic/routing performance is only one aspect of the overall performance/design suitability question. Many customers *do* have trouble meeting timing in the core of their design, and a faster chip (e.g. Stratix II) can make it easier to do so, leaving you with more time/energy to spend on other problems such as I/O interfaces and debugging. A faster chip can also mean you can by a cheaper speed grade and still meet core timing, provided that device meets your other needs. If you don't need core performance at all, then that particular aspect of Stratix II will not be of use to you. Everyone has different needs. Many customers do need speed. Regards, Paul Leventis Altera Corp.Article: 78535
Hi, I'm new to embedded development so I hope you will excuse my possibly stupid questions. I would like to add a custom peripheral to my MicroBlaze design in EDK 6.3. I have simple GCD algorithm given in VHDL that I would like to interface with the MicroBlaze using the OPB bus. I have used the "Create and Import Peripheral Wizard" to generate a skeleton for an OPB interface. The result of runnig the wizard is a collection of files that I need to edit in order to interface the bus with my GCD coprocessor. I have been toying around with these files for quite a few hours now and I have gotten nowhere. In this regard I have several questions that I would love to get answered.. First, are there any examples (or documentation= of how to interface the files produced by the wizard with a custom design? Second, which of the files the wizard created for me should I be editing ? Currently I am adding the "generic paramters" to the "mydesign-imp.vhd" file and doing the interfacing in the "user_logic-imp.vhd" file. Third, I have connected the "Bus2IP_Clk" and "Bus2IP_Reset" signals to the clock and reset ports of my GCD processor but if i try to "implement design" in ISE 6.3 I get errors about "multiple drivers" and "illegal connections". Why is that ? .. should I not synthesis the peripheral using ISE 6.3 ? Finally, do any of you know of a webpage containing resources regarding peripheral development ? Thanks, PeterArticle: 78536
>Their newest game is giving leakage current values at 25 deg=ADrees. Nice >numbers, but totally meaningless and utterly misleading. How=AD does one >expose this? Legally, it's not exactly a lie, but it has the=AD same >effect as if it were. Some engineers and managers may even b=ADe >inexperienced enough to fall for this kind of nonsense. The =ADquestion is >just: How fast will it backfire? The earlier, the better ! Wow. I can't believe how completely backwards this is -- who is lying here Peter? Who is playing the "games"? >From the very first release in November 2004, all our Stratix II tools have provided static power as a function of junction temperature (ranging from 25C to 100C) and process (typical and worst-case silicon). Contrast this to your Virtex-4 data. Until two weeks ago, the only available data was 25C, Typical silicon. Then with WPT 4.0 you finally caught up on temperature-dependent static power. But still, only typical silicon. Sub-threshold leakage increases exponentially with threshold voltage and gate length, and thus is extremely sensitive to process variation. I wonder how many of your customers have fallen for your marketing story only to find themselves with atypical units of silicon that burn more power than your spec? Altera prides itself on operational excellence and reliability. This extends to our power models. At the introduction of Stratix II, we provided conservative power specs (both typical and worst-case) to ensure that our customers could safely design to this product. These specs reflected the uncertainty that comes hand-in-hand with software before silicon release. As the various family members have come back from the fab, we have tightened the specs based on preliminary measurements, and we will further improve things in the future once full data collection and analysis is complete. Dare I point out that the copious amount of press release/collateral/FUD you guys have disseminated over the past year on power is based on "totally meaningless and utterly misleading" (your words) 25C typical data for Virtex-4? You have no worst-case data and you do not have any real power tools for your Virtex-4 customers. I think you should be the one worried about backfire. >The emotional words about benchmarks were no play-acting. I =ADstill have >scars from Altera's reckless destruction of the old PREP coo=ADperation, >more than a dozen years ago. And they are still up to their =ADsame old >trickery. I know nothing of PREP (before my time). But if you have specific concerns with the benchmarking methods we use, I'd love to hear them. There is no trickery -- Stratix II has a +39% performance advantage. Regards, Paul Leventis Altera Corp.Article: 78537
Jim George wrote: > Hi, > Why is it that you cant put a FDRE and an SRL16E on the same slice? > I looked at a V2 slice within FPGA Editor (woohoo, got the full version > of ISE at last!) and it shows me there's a WE signal going to the SRL16, > driven by the slice's SR input. Now why would you want to drive it with > the SR input when there's already a CE input available??? I wanted to > construct a delay line (SRL16 + FF), whose output FF can be reset but > then this is not allowed. Any workarounds? > Thanks. > -Jim Nossum, I too am puzzled why we cant use ALTDIG as an input for an SRL16. SHIFTIN is meant as a "carry" input from another SRL16, it's a dedicated line which doesnt go to the nearby switchbox, so that's out too. Unless, like you said, I can use two SRL16s to form an "SRL32", which would free BX (which was DI of the SRL16 in LUT F). I guess this BX can then be used as a reset for FFX. John, I can tolerate the delay, I guess. I will be running the design at 65 MHz. The reason I cant use either this or John's suggestion of an external flop is that I want to pack this with as much density as I can (2 bits per slice). Sometimes the SLICE design of a Virtex just puzzles me! Thank you for the replies. -JimArticle: 78538
Jezwold wrote: > Why do you want to re-invent the wheel when there are perfectly good > mp3 decoder chips which will do the job? Why did you learn how to make a full adder in college while an off the shelf calculator can do a much better job? It's for LEARNING experience. Otherwise I can just buy an IPOD and forget about my project. > If you don't know anything about the mp3 alogo then what makes you > think that its a suitable project? I understand that this is a very challenging project. Nevertheless, I want to build it. When it's done, I will include the project in my resume and my website for prospective employer to see. HendraArticle: 78539
Rene Tschaggelar <none@none.net> wrote: >Peter Alfke wrote: > >> There seems to be a misconception that you can Gray-code any bus. Not >> true. >> Gray-coding applies only to counters, where it guarantees that only one >> bit changes on any transition. There is no "general purpose" Gray >> coding ... > >Sure, a bus cannot live from 1 bit transitions. I was >unclear about that. A clock as qualifier is >appropriate. I'm not sure why you would want to, but a bus with single bit transitions could work. It would be very ineffiecient. You would need n wires to send n states. Suppose you wanted to send a four bit command to some remote device on a different clock, and you could not send a clock with the data (I can't think of realistic reasons why, but humor me). So on each clock, the sending circuit would decode the four bit command to one of sixteen bits to XOR with the current state of the bus. This would toggle one bit of the sixteen bus wires to indicate which command was being sent. The receiving circuit would look for one bit to change and would decode this to the correct command. I can't think of any practical examples, but maybe there is one somewhere. -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 78540
Thanks, It was only staring me right in the face.... "Stefan Frank" <stefrank@gmx.net> wrote in message news:4200c7cc$0$5309$4d4ebb8e@read.news.de.uu.net... > On 02/01/2005 05:48 PM, JT wrote: >> How can you get ModelSim to print the wave window in color? I tried >> printing to a color printer and only got BW. > > Select File -> Page setup... in the wave window. There is a radio button > for the output color. My version is Modelsim 6.0b. > > HTH & HAND, > StefanArticle: 78541
Dear all, I've placed my design in an Altera Stratix and use a PLL for clock generation. In a first stage PLL generated 22 MHz as output freq and Quartus II (3.0 release) showed 36 MHz as fmax. Due to this result, I have decided to increase PLL output to 33 MHz (without any change on the design). Now, after placement, Quartus Timing Analyzer shows 33.1 MHz as new fmax. I've repeated both placements (with a 22MHz PLL and with a 33 MHz PLL) multiple times and the results are similar. Has the PLL configuration any impacts on other parameters which affect timings ? I've also tried a backannotation when going to 33 MHz, but the results are the same. I can't use Chip Editor, since it crashes. Thanks for your help.Article: 78542
Hi all,
Been reading a lot from the archives about synch/asynch resets. Found lots
of good stuff and am now more enlightened.
My conclusions so far:
(1)
Use synchronous reset in general on the flip flops for FPGAs
(2)
If system requires asynch reset on the flip-flops, synchronise the release
of the reset to the appropriate clock domain to avoid the release spanning a
clock edge due to fanout delay.
Question 1:
I guess the main reason for using an asynch reset is for when the circuit
must be reset in the absence of a working clock? If so, how can the release
ever be synched to said clock if it is not working? Hence, why ever use
asynch reset on a clocked circuit?
Question 2 (the main one):
In general it seems the best idea is to use a synchronous reset i.e.:
if (clk'event and clk = '1') then
if (rst = '1') then
// do reset
else
// synchronous logic
end if;
end if;
The question is to do with the source of the rst signal. Assuming that the
rst signal pulse comes into the device via a pad, I assume that the
circuitry external to the FPGA generating the pulse *must* do so
synchronously to clk? (clearly if rst is generated on the device
synchronous to clk then no problem). Otherwise, if rst is asynchronously
generated, there must be a chance of the rst pulse transitioning too close
to a clk edge at the flops and causing metastability? Or does this
metastability issue only apply for the D/Q pins on the flop?
Thanks in advance for your time,
Ken
Article: 78543Hi Hendra, May be You can look into http://www.pjrc.com/tech/mp3/ and there is an example on the xilinx web site for mp3 player.Article: 78544
In an FPGA design with an Altera ACEX and Quartus II I get clock skew. There are data paths between several modules and a derived 64 MHz master clock. Adding or changing the design in another part of the design leads to a change or the distance of the data paths of the modules. As a result there is always the possibility of incorrect circuit functionality due to clock skew. The Quartus Handbook says in the chapter Advanced Timing Analysis: "... This is achieved by adding cells to the path or through the placement of the source and destination registers." Conclusion: (1) If adding or changing the design I have to control the clock skews and therefore place lcells into the data paths EVERY compiler run (2) Place the source and destination registers by hand on the layout? This is not possible in the ACEX ... Is this really the way to make a good FPGA design or am I missing something in the assignments or timing requirements? Thanks for any help. /AloisArticle: 78545
Hendra wrote: > 1. If I use USB memory stick, is it significantly more difficult than > using IDE harddrive? Don't. AFAIK there is no free USB host IP for FPGAs available and you do not want to build your own. Use compact flash cards. They are simple to interface to, cheap and it is reasonably simple to purchase connectors. > 2. Where can I download the mp3 specification and algorithm? Is it in > public domain, or is it a copyright secret? It is an open standard. You might be able to access the original standard through your universities library. You can also download sources for one of the myriad open source implementations of the decoder. I would suggest that you rip the decoder algorithm source code from some open source decode and first try to build a PC software that decodes mp3 into audio files so that you are sure that everything works as expected and that you are sure that you understand how to apply the algorithm. Then I would build a system on a chip in your FPGA with some processor from www.opencores.org that can run the software decoder. (Some of these cores should come close to real time decoding allready, but realtime is not necessary at this step) When this works you can replace some of the simple bu time consuming parts of the algorithm by a coprocessor to your CPU to achieve real time decoding. A development board that has audio output, a compact flash connector, LCD, remote control input and switches is this one: http://www.trenz-electronic.de/prod/proden20.htm Have fun, Kolja SulimmaArticle: 78546
Thanks to all of you for your replies. I am going to squeeze in the resistors somehow (the problem is to fit all the vias). Kolja Sulimma Jim Granville wrote > On a short run, just where the termination is, is not as critical as > having the temination itself. [...] > you can get 4 resistors in a single package, and mount them > routing-practical distances from the receiver ? > > -jg >Article: 78547
Hi when i launch ModelSim 5.8c XE, the windows with the logo of modelsim( a rhinoceros) open and after a few seconds it close and nothing else happen there no process of modelsim running in the process list of winXP I don't understand because last week It always run correctly. I tried to reinstall Modelsim and it don't change Does anyone know this problem?? Thank you AlexisArticle: 78548
kcl wrote:
> when i launch ModelSim 5.8c XE, the windows with the logo of modelsim( a
> rhinoceros) open and after a few seconds it close and nothing else happen
I've seen that happen when the license file can't be located.
-- Mike Treseler
Article: 78549
Alois Huber wrote:
> In an FPGA design with an Altera ACEX and Quartus II I get clock skew.
Maybe your clock isn't on one of the global clock networks.
-- Mike Treseler
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Compare FPGA features and resources
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