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Ken, I'm not sure how you know that bandpassFilter and differentiatorFilter are inherited rather than contained by BluetoothReceiver. The initializer list syntax is valid for both data members and base classes when used in a constructor. I suspect it is used here for data members because "bandpassFilter" is used (and not "BandpassFilter") suggesting a member, not a class. Of course the only way to be sure is to see the declarations of these identifiers.Article: 77976
OK I understand that you can take the output of Design Compiler and feed it through the xilinx tool given I write a library that gives an FPGA equivalent for each gates. I suppose this would work if the design is only a bunch of gates with only one clock domain. Our design has only one clock domain (everything is coded in verilog with 'enable' line going to every flip flop). However, there is this step in Design Compiler where you tell it to add 'gated clocks'. As far as I know, this removes the 'enable' lines and actually clock the flip flops with divided version of the master clock. It makes sure that the clock boundaries crossing are ok. How would the xilinx tool handle a netlist of gates that has all those clock gating circuit? Thanks, David John Adair wrote: > If you have a netlist which I am guessing is mainly ANDs, ORs or even > technology specific elements. You can model each gate/element to an > equivalent in the FPGA. We do this kind of thing for clients from time to > time. More often the biggest issues come in ASIC designs that use a lot of > clocks and have a lot clock boundary crossing. When you get into this type > of design you need to be careful of how it will work in the FPGA. It isn't > impossible but care is needed in designs with large numbers of clocks. As a > side point it is worth looking at Virtex4 for this kind prototyping of as > the family has features aimed at designs with lots of clocks and even clock > boundary crossing assistance. > > If at all possible when starting a new design try structure the design to be > friendly to both types of target. If do it early enough is can be a painless > process and does not cost ASIC resource if done properly. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "gretzteam" <david.lamb@gmail.com> wrote in message > news:1106241119.166667.167990@z14g2000cwz.googlegroups.com... > > Hi, > > We are currently using virtexIIpro and virtex4 fpga to prototype a dsp > > processor. All the code is synthesizable verilog and we are using > > Xilinx ISE to do synthesis and place and route. Everything works fine > > and the processor runs at full speed (50Mhz). However, this is only > > good for functionnal verification on the bench. The ASIC flow and the > > FPGA flow are very different so the actual gates in the FPGA are > > different than what will be on the ASIC. For example, we can't use the > > FPGA to verify the test vectors and scan chains that the test engineer > > is working on. > > > > Is it possible to prototype the EXACT same gates that will be in the > > ASIC? We use Synopsys Design Compiler to generate the ASIC gates. > > Basically is there a way to take the gates generated by Design > > Compiler, and map them in the FPGA? We don't really care if this runs > > slower, but it would allow the test engineer to start working on all > > the test vectors before we receive silicon. > > > > Thank you very much, > > David > >Article: 77977
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:10v27avp1mno13b@corp.supernews.com... > Thanks. > > And how much does Synplify cost? Their sales folks will be happy to talk to you. http://www.synplicity.com/corporate/globallocations/index.html Be sure to consider the Synplify or Synplify Pro product with HDL Analyst - an add-on. While I use Synplify (non-pro) there are benefits with retiming and auto-constraints for aggressive performance in the Pro product worth considering since so much time is spent trying to eke out that last nanosecond in some paths.Article: 77978
Voxer wrote: > Dear All, > > I am looking into the possibility of running nested interrupts. > > Effectively what I have at the moment is a single thread of control > and an external non critical irpt which does some comms stuff. > > I now want to add a critical interrupt handler but what would happen if > I was executing my non-crit handler and the crit irpt went off. I am under > the impression that > I need to complete my handler before the other one would start. > > There is a query like this on the Xolinx web page but it is a one sentence, > non-helpful answer. > > Thanks In Advance > > The PowerPC Reference Manual contains the following information: Critical and Noncritical Exceptions The PPC405 supports critical and noncritical exceptions. Generally, the processor responds to critical exceptions before noncritical exceptions (certain debug exceptions are handled at a lower priority). Four exceptions and their associated interrupts are critical: • Critical-input exception. • Machine-check exception. • Watchdog-timer exception. • Debug exception. Critical interrupts use a different save/restore register pair (SRR2 and SRR3) than is used by noncritical interrupts (SRR0 and SRR1). This enables a critical interrupt to interrupt a noncritical-interrupt handler. The state saved by the noncritical interrupt is not overwritten by the critical interrupt. Because a different register pair is used for saving processor state, a different instruction is used to return from critical interrupt handlers—rfci. This is covered in Chapter 7. The manual can be found here: http://www.xilinx.com/ise/embedded/edk_docs.htmArticle: 77979
Thankyou i think you are right...possibly memory conflict......i would check BRAM size ....(if this is a way to check "memory conflict" --: ) by the way, in base system wizard (and microblaze reference guide), we can choose 8K, 16K, 32K...BRAM size... Question is that can we set BRAM size 12KB ? (base address 0000 0000 - 0000 3fff) thankyou again regards DerekSimmons@FrontierNet.net wrote: > I don't have experience with this platform but from the information you > provided, I would conclude it is a memory conflict. > > Why: The error message indicates that it could be from either an 'out > of memory condition' or a 'memory conflict'. You have stated that you > have set memory at 3 Gb. In the memory message it said that it is using > 1.95 Gb. Therefore I would conclude it is some kind of memory conflict > sense it is using less memory than you have allocated. Have you checked > for a conflict? > > Hur wrote: > >>dear >> >>In EDK6.3 XPS, microblaze netlist generation, >> >>Following 'out of memory' error occurred. >>Memory is 3GB, (sufficient enough, i think) >> >>Someone who has experience like me, how did you manage this problem? >> >>---------------------------------------------------------- >>ERROR:Portability:3 - This Xilinx application has run >>out of memory or has encountered a memory conflict. >>Current memory usage is 2044740 kb. Memory problems >>may require a simple increase in available system >>memory, or possibly a fix to the software or a special >>workaround. To troubleshoot or remedy the problem, >>first: Try increasing your system's RAM. >>Alternatively, you may try increasing your system's >>virtual memory or swap space. If this does not fix >>the problem, please try the following: Search the >>Answers Database at support.xilinx.com to locate >>information on this error message. If neither of the >>above resources produces an available solution, please >>use Web Support to open a case with Xilinx Technical >>Support off of support.xilinx.com. As it is likely >>that this may be an unforeseen problem, please be >>prepared to submit relevant design files if necessary. >> >>make: *** [implementation/microblaze_0_wrapper.ngc] >>Error 19 >>--------------------------------------------------------- >> >>thx >> >>regards > >Article: 77980
On 21 Jan 2005 07:56:03 -0800, "gretzteam" <david.lamb@gmail.com> wrote: >OK I understand that you can take the output of Design Compiler and >feed it through the xilinx tool given I write a library that gives an >FPGA equivalent for each gates. I suppose this would work if the design >is only a bunch of gates with only one clock domain. > >Our design has only one clock domain (everything is coded in verilog >with 'enable' line going to every flip flop). However, there is this >step in Design Compiler where you tell it to add 'gated clocks'. As far >as I know, this removes the 'enable' lines and actually clock the flip >flops with divided version of the master clock. It makes sure that the >clock boundaries crossing are ok. How would the xilinx tool handle a >netlist of gates that has all those clock gating circuit? > Divided clocks are not that difficult but some power optimization scripts add gated clocks where the clock line is controlled with a latch and "and" gate sometimes at individual dff level. These would be more difficult manage. Basically it depends on the number of clock domains (divided+gated) you're generating.Article: 77981
Brad Smallridge wrote: > An answer not posted to the group: > > Macros are not components that can be instantiated in HDL. Macros are > only available in ECS, the Xilinx schematic entry tool. In the XACT days there were ways of doing this. You make an empty HDL module with the appropriate I/Os, and if you want to simulate it you can include non-synthesizable code. At some point after synthesis and before place and route you tell it to remove the dummy and substitute the macro version instead. It might be that a similar method is available with current tools. -- glenArticle: 77982
Does anyone have a very good reference for designing ADPLL's in FPGA architectures? I have various books on PLL design, and they mostly talk about DPLL and LPLL style circuits. They mention ADPLL, and give 1-2 examples, but nothing in depth... Thank you, -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 77983
I must say that I find the xilinx docs to be vague. I am trying to configure the FPGA using uProcessor. Since a way to program the FPGA is via the PROM, I thought i would program the PROM first and then load the data from the PROM to FPGA. How does the Master-serial configuration mode work? Does the FPGA have some hard-coded state machine which clocks the data from the PROM? Can we use any generic PROM or does it have to be Xilinx PROM? Thanks for any help -YajuArticle: 77984
There is a Horizontal, Vertical, and composite output. You can connect those signals pretty much directly to a multisync vga monitor and get a large screen...maybe even an LCD, but I'd put the signals through an optical isolator on my monitor... ;) One of the sync lines had to be inverted to work with old RGB/CGA monitors, but my 10 year old multi sync VGA monitor work with almost any combination of /V /H, V H, /V H, V /H, etc. The weird thing is that sometimes a new combination will cause the image to get larger.Article: 77985
There are application notes that talk about this. Go to support.xilinx.com and choose the Documentation link and then App notes (that's from memory--hopefully its right). The key word that Xilinx uses for this is configuration. Once you figure that out its not hard to find the info you are looking for. There is sample code available for this sort of thing although you will more than likely have to port it to your situation. Hope that helps. On Fri, 2005-01-21 at 09:54 -0800, Yaju N wrote: > I must say that I find the xilinx docs to be vague. > > I am trying to configure the FPGA using uProcessor. Since a way to > program the FPGA is via the PROM, I thought i would program the PROM > first and then load the data from the PROM to FPGA. > > How does the Master-serial configuration mode work? Does the FPGA have > some hard-coded state machine which clocks the data from the PROM? > > > Can we use any generic PROM or does it have to be Xilinx PROM? > Thanks for any help > > -Yaju >Article: 77986
savingsandloan wrote: > Just out of curiosity, is it possible to pipeline successive reads and > writes to SDRAM? For example, I want to send a read command and then a > write command, where the memory address will be different for reads and > writes. After the necessary latency after the first read command, will > there also be a delay between when I clock in data from that read and > when I can start outputting write data? > As far as I remember, there is no delay if the write is to a row that is currently active. In SDRAM you have 2 or 4 banks and each bank can have one row active at a time. There are special commands to activate a row and precharge (store back) a previously activated row. You can only read/write to an activated row. SDRAM datasheets from Micron, ISSI, and others have nice timing diagrams illustrating different cases. -- GeorgiArticle: 77987
Vadim Vaynerman wrote: > Yes, it would seem to be a software issue, as nothing goes over the serial port. I have tried a utility such as userport, which allows the old inb/outb commands in Win2000, but to no avail. I was indeed logged inn as an administrator... I was really hoping that Xilinx put something out that corrected this, but it seems that Xchecker is meant to wither and die away. Vadim, The xchecker was officially obsoleted in 1999. None have been produced since and software support was removed from all applications released after that time. The application that last used it (JTAGProgrammer and HardwareDebugger) were developed and verified to support only Win95/98 and WinNT. Changes to the Win2K and WinXP may be interfering with serial port communications. You could try and run JTAGProgrammer through the compatibility wizard and see if that makes any difference (I suspect not) I am afraid that your choices are limited to (a) not upgrading your OS -or- (b) purchasing a new parallel cable (about $150) and using the latest iMPACT Configuration Software (available as a free download) - which can still accept older bitstreamsArticle: 77988
The CF from the SystemACE CF is not configurable via boundary-scan. It can only be configured using a CompactFlash programming cable through your PC. The CF could, however, be addressed using an embedded processor using the microprocessor port on the controller chip. I think, though, that you have misunderstood the interaction between SystemACE CF and the FPGA. You should be able to reach the FPGA through the boundary-scan of the SystemACE CF controller in all scenarios Scarex wrote: > I'm working on a Xilinx demonstration board equipped with a jtag chain > including a SystemACE CF and a Virtex-II FPGA. > My goal is to configure the FPGA via Jtag bypassing the SystemACE. > Unfortunaly, after the hardware reset, the SystemACE is configured by > default to look for a bitstream on the Compact Flash: in this way, it > doesn't allow me to > reach the FPGA through the Jtag. I have to use Impact software to > configure for the first time, and then I can access to FPGA. So, I think > that Impact configures > the SystemACE in order to transfer data to FPGA. > It's possible to program the SystemACE via Jtag?On Xilinx 080 Datasheet > (SystemACE CF solution) I can find only 4 instructions (idcode, sample, > extest, bypass); > in adding to this, it seems that Jtag Configuration Register is not > present. > Are there any others not documented commands which allow me to configure > SystemAce (for example cgfin and cfgout)? Otherwise, have anybody a > solution for my problem? > Thank you very much. > SalvatoreArticle: 77989
hi,
I'm working with ISE6.3.03i
I want to run my design at 160MHZ. So I put this contraints on my .ucf
file :
Clk = 6.25ns
Offset in = 6.25 ns;
Offset out = 6.25 ns
In my place end route report, I have 'All constraints are met". But
when I run my design wih ModelSim some Hold and Setup error occur. So
I watch the timing report (Post Place And Route). I have something
like that :
setup hold
ARST 4.683 3.136
ENI -0.455 3.489
SRST 3.786 3.514
WRCFG 1.424 4.196
.... ... ...
Why setup or hold could be negative?
How could I have a better control to my design?
thanks
Article: 77990Georgi Beloev wrote: > savingsandloan wrote: > > Just out of curiosity, is it possible to pipeline successive reads and > > writes to SDRAM? For example, I want to send a read command and then a > > write command, where the memory address will be different for reads and > > writes. After the necessary latency after the first read command, will > > there also be a delay between when I clock in data from that read and > > when I can start outputting write data? > > > > As far as I remember, there is no delay if the write is to a row that is > currently active. In SDRAM you have 2 or 4 banks and each bank can have > one row active at a time. There are special commands to activate a row > and precharge (store back) a previously activated row. You can only > read/write to an activated row. > >From a practical standpoint you should figure on wasting at least one cycle when switching between read and write in order to avoid overlapping drive on the DQ pins. If you're continuing to just write (or just read) you can burst continuously by "burying" the row precharge. This requires switching banks whenever you start a new row, however if you define "sequential" addresses such that the bank address bits are lower than the row address, you will be able to burst write or read the entire memory without any NOP cycles on the data lines. Also when switching from write - which presents data and command on the same cycle - to read, which has the "CAS latency" between the read command and the data cycle you will have multiple unused data cycles if you stay on the same bank (i.e. one bank cannot have a read command issued during a write burst). > SDRAM datasheets from Micron, ISSI, and others have nice timing diagrams > illustrating different cases. > > -- GeorgiArticle: 77991
Yaju N wrote: > I must say that I find the xilinx docs to be vague. > > I am trying to configure the FPGA using uProcessor. Since a way to > program the FPGA is via the PROM, I thought i would program the PROM > first and then load the data from the PROM to FPGA. > > How does the Master-serial configuration mode work? Does the FPGA have > some hard-coded state machine which clocks the data from the PROM? > If you want to control the loading process from the uProcessor and not the FPGA, you should use slave serial mode instead. In master serial mode, the FPGA drives the CCLK line out and expects one bit from the configuration bitstream on each rising clock edge. The CCLK will continue to switch until the configuration is complete. Since the minimum CCLK frequency in this mode is about 2.5 MHz, the uProcessor would need to respond very quickly to supply data a bit at a time. In slave serial mode, the uProcessor would drive CCLK and DIN, making sure that DIN is stable at the rising edge of CCLK. When the bitstream is completely shifted out, the uProcessor would wait for the done line to go high while continuing to shift 1's and toggling CCLK. This allows for the startup pipe to complete (see configuration options in bitgen). To prepare a bitstream for loading, use impact to generate a HEX format file. These files have no relation to any particular PROM and contain only the bitstream stored as 2 hex characters per byte. I forget which bit to shift out first, but I think you want to shift LSB first if you generate the HEX file with the default option of "swap bits". If I'm wrong, instead of fixing your program, just un-check the "swap-bits" option and re-generate the HEX file. I generally convert the HEX file to straight binary with a simple C program before storing it in the uProcessor's ROM. > > Can we use any generic PROM or does it have to be Xilinx PROM? You only need a Xilinx PROM if you want to directly program the FPGA without help from the uProcessor. In this case you would want to use master serial mode. > Thanks for any help > > -YajuArticle: 77992
Again I don't have experience with your target platform but I'll venture putting my foot in my mouth. Base on the sizes you listed, if it will let you specify 12 Kb and build without any errors or warnings then it might be actually allocating 12 Kb of 16 Kb and not addressing the last 4 Kb or memory so that you can put something else in that address space. DerekArticle: 77993
Neil Glenn Jacobson ha scritto: > The CF from the SystemACE CF is not configurable via boundary-scan. It > can only be configured using a CompactFlash programming cable through > your PC. The CF could, however, be addressed using an embedded > processor using the microprocessor port on the controller chip. > > I think, though, that you have misunderstood the interaction between > SystemACE CF and the FPGA. You should be able to reach the FPGA through > the boundary-scan of the SystemACE CF controller in all scenarios > Hi Neil, today I've solved the problem. Using Jbits on jtag chain, I've discovered I've to give to SystemACE the JSTART command, like FPGA, even if in the SystemACE Datasheet Xilinx doesn't report this command. Bye ScarexArticle: 77994
>To prepare a bitstream for loading, use impact to generate a HEX format >file. These files have no relation to any particular PROM and contain >only the bitstream stored as 2 hex characters per byte. I forget which >bit to shift out first, but I think you want to shift LSB first if you >generate the HEX file with the default option of "swap bits". If I'm >wrong, instead of fixing your program, just un-check the "swap-bits" >option and re-generate the HEX file. > >I generally convert the HEX file to straight binary with a simple >C program before storing it in the uProcessor's ROM. There used to be a .rbt file format - raw bits. The bits in the file were ascii 1s and 0s. That's horribly inefficient, but you don't have to worry about LSB vs MSB. And efficienty isn't too important if you are running it through a program only once to convert it to a format that's reasonable for your usage. You can also use it just for debugging - look at the .rbt version to figure out how to parse the .hex version. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 77995
Yaju N wrote: >I must say that I find the xilinx docs to be vague. > >I am trying to configure the FPGA using uProcessor. Since a way to >program the FPGA is via the PROM, I thought i would program the PROM >first and then load the data from the PROM to FPGA. > >How does the Master-serial configuration mode work? Does the FPGA have >some hard-coded state machine which clocks the data from the PROM? > > > In master mode, YES, the FPGA has a complete sequencer to clock bits out of a serial PROM, deblock it, CRC check it, load it into the logic array, and finally terminate the process with a DONE signal if it completed the configuration correctly. >Can we use any generic PROM or does it have to be Xilinx PROM? >Thanks for any help > > As long as it responds correctly to the INIT/ and serial clock signals, producing the correct bit on the first clock pulse, etc. then anyone's SPROM will work. There are several standards for the control of serial PROMS, so not all of them are compatible. The PROM has to be voltage compatible with the FPGA, as well. JonArticle: 77996
I sense confusion here... It appears to me that you are mixing up the address space of your microblaze design and the address space of the computer on which you are compiling your target design. Unfortunately, the error message is referring to the latter and not the former. The computer on which you are compiling the design has run out of memory. Try increasing your computer's memory if possible. Some platforms have different memory limits. (Example: WinXP usually reserves 1GB for OS and 2GB for applications.) Changing the address space of your microblaze design is probably not going to get you anywhere with this problem. You can check http://support.xilinx.com for possible solutions. If there are no solutions readily available to you you can open a case with the Xilinx hotline for other possible workarounds. -Davis Moore Hur wrote: > Thankyou > > i think you are right...possibly memory conflict......i would check BRAM > size ....(if this is a way to check "memory conflict" --: ) > > by the way, in base system wizard (and microblaze reference guide), we > can choose 8K, 16K, 32K...BRAM size... > > Question is that > can we set BRAM size 12KB ? > (base address 0000 0000 - 0000 3fff) > > thankyou again > > regards > > DerekSimmons@FrontierNet.net wrote: > > I don't have experience with this platform but from the information you > > provided, I would conclude it is a memory conflict. > > > > Why: The error message indicates that it could be from either an 'out > > of memory condition' or a 'memory conflict'. You have stated that you > > have set memory at 3 Gb. In the memory message it said that it is using > > 1.95 Gb. Therefore I would conclude it is some kind of memory conflict > > sense it is using less memory than you have allocated. Have you checked > > for a conflict? > > > > Hur wrote: > > > >>dear > >> > >>In EDK6.3 XPS, microblaze netlist generation, > >> > >>Following 'out of memory' error occurred. > >>Memory is 3GB, (sufficient enough, i think) > >> > >>Someone who has experience like me, how did you manage this problem? > >> > >>---------------------------------------------------------- > >>ERROR:Portability:3 - This Xilinx application has run > >>out of memory or has encountered a memory conflict. > >>Current memory usage is 2044740 kb. Memory problems > >>may require a simple increase in available system > >>memory, or possibly a fix to the software or a special > >>workaround. To troubleshoot or remedy the problem, > >>first: Try increasing your system's RAM. > >>Alternatively, you may try increasing your system's > >>virtual memory or swap space. If this does not fix > >>the problem, please try the following: Search the > >>Answers Database at support.xilinx.com to locate > >>information on this error message. If neither of the > >>above resources produces an available solution, please > >>use Web Support to open a case with Xilinx Technical > >>Support off of support.xilinx.com. As it is likely > >>that this may be an unforeseen problem, please be > >>prepared to submit relevant design files if necessary. > >> > >>make: *** [implementation/microblaze_0_wrapper.ngc] > >>Error 19 > >>--------------------------------------------------------- > >> > >>thx > >> > >>regards > > > >Article: 77997
>I sense confusion here... > >It appears to me that you are mixing up the address space of >your microblaze design and the address space of the computer >on which you are compiling your target design. > >Unfortunately, the error message is referring to the latter and not the >former. The computer on which you are compiling the design has run >out of memory. Try increasing your computer's memory if possible. >Some platforms have different memory limits. (Example: >WinXP usually reserves 1GB for OS and 2GB for applications.) Well, I'm confused too. Why does a compiler need so much memory? All sorts of systems get compiled on boxes with much less memory than 2GB. (My NetBSD/Arm box can compile it's kernel in 32 MB.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 77998
cedric wrote: > hi, > I'm working with ISE6.3.03i > I want to run my design at 160MHZ. So I put this contraints on my .ucf > file : > Clk = 6.25ns > Offset in = 6.25 ns; > Offset out = 6.25 ns > In my place end route report, I have 'All constraints are met". But > when I run my design wih ModelSim some Hold and Setup error occur. So > I watch the timing report (Post Place And Route). I have something > like that : > > setup hold > ARST 4.683 3.136 > ENI -0.455 3.489 > SRST 3.786 3.514 > WRCFG 1.424 4.196 > .... ... ... > > Why setup or hold could be negative? > > How could I have a better control to my design? > > thanks Cedric, Check out ftp://ftp.xilinx.com/pub/documentation/misc/timingcsts6i.pdf -NewmanArticle: 77999
I'm probably going to attempt a distructive test on a PLD to determine its function. I'm wondering if anyone has tried this, and with what success? I found this: "An important architectural feature that is found on virtually all PLDs is not shown on logic diagrams. This feature is the security fuse. Normally, the fuse pattern programmed into a PLD can, like a PROM, be read and displayed or copied by programming hardware. Devices with a security fuse, however, provide the ability to disable this read function. This allows the design to be somewhat secure from attempts to copy or reverse engineer it. In reality, it's relatively easy to shave the top off of a bipolar PLD and examine the programmed fuses with a microscope. For bipolar PLDs, then, would be copiers are merely inconvenienced. Erasable CMOS PLDs are considerably more secure, since it's very difficult, if not impossible, to determine their function from examination." From http://www.ee.cooper.edu/courses/course_pages/past_courses/EE151/PLD1/ Anyone here ever "shave" a chip for examination? I have access to a video microscope at the university. I also have a DV camcorder with DV in, so I could take the pictures, post them, and then beg for more help. ;) Any suggestions? I would be shaving the top off of some 16R8/4 chips. Would heating them to around 250-300F for a while help? Shaving the tops down while hot? I have access to 48 micron resolution digital x-ray equipment, but no microfocus x-ray tubes at the moment, so I don't think I would get good enough resolution by X-raying the chips. I could try just for fun, These old PALs just might have large enough internals. Here is a shot of a PCMCIA card, about 50% full resolution. If I did some gemoetric magnification and used a different LUT, I might be able to see something, but I seriously doubt it. http://www.cmosxray.com/X-rays/newX-rays/4x4/4x4x-rays%20extra/board.JPG Now I'm a little more curious about the x-rays. I think I;ll go rip apart a 286 motherboard for a PAL and do some tests this weekend. :) I eventually want to rewrite all of the equations for speed, but getting a 100% copy of the OEM work was the goal. Grant
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