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Göran Bilski <goran.bilski@xilinx.com> wrote in message news:<cv294c$bmv3@cliff.xsj.xilinx.com>... > Since both processors starts at address 0, they will start to execute the same > initialization code. > You need to use a FSL port with different constant signals for each MicroBlaze. Dear Mr. Bilski, sorry for the intromission. Just a question: how you can declare a FSL port with constant signals without defining a custom FSL core? Thank you very much!Article: 79801
Prescalers are mostly used to increase the max frequency resolution. What is it you are after? Peter AlfkeArticle: 79802
Kevin, I refers to 6.3i speed files, but our own FAEs also noted that the files are either hidden, or missing. OK, so I read the PR and believed it was true immediately. Sorry. I am sure they will post the new speeds files today or tomorrow, however. I saw them, and saw the review, so I know they are there. I also know they are a requirement (must have). Austin Kevin Brown wrote: > Austin, > > The PR says the speed files have been released, but they are nowhere to > be found on Xilinx's website. > > Do you have a URL for 6.3i speed files, or does this PR refer to ISE > 7.1i? > > -Kevin >Article: 79803
Symon, One caution about micro-vias: I saw a design where the bridge to connect the top via to the micro via made the plane even worse! If it looks like swiss cheese, then it probably is about that effective. Micro vias are one tool to improve matters, but they have to be carefully used. Austin Symon wrote: > Hi Austin, > Thanks for your reply! I must say it's good to see Xilinx are taking this > issue seriously. As you say, the silicon performance improvments necessitate > these package improvements. I totally agree that the package can screw up > the whole thing. The tales of woe on CAF from folks trying to design with > PQ208s show that! > My concern was that the package pinout can make it hard to design a PCB > layout which has good SI. Power vias turning ground planes into Swiss cheese > and all. Ah well, it's about time I did a board with an extra microvia > layer.... > Cheers mate, Syms. > >Article: 79804
Hi, That is simple. In the .mhs file if I want to assign a constant value of 1 to fsl port 0 and also to make it always ready, I just add this to the MicroBlaze block. PORT FSL0_S_DATA = 0b00000000000000000000000000000001 PORT FSL0_S_CONTROL = 0b0 PORT FSL0_S_EXISTS = 0b1 Göran TheMightyShaman wrote: > Göran Bilski <goran.bilski@xilinx.com> wrote in message news:<cv294c$bmv3@cliff.xsj.xilinx.com>... > >>Since both processors starts at address 0, they will start to execute the same >>initialization code. >>You need to use a FSL port with different constant signals for each MicroBlaze. > > > Dear Mr. Bilski, sorry for the intromission. Just a question: how you > can declare a FSL port with constant signals without defining a custom > FSL core? > > Thank you very much!Article: 79805
Hi, If you don't want to express the constant value as binary, you can also do this. PORT FSL0_S_DATA = 0x00000001 Göran Göran Bilski wrote: > Hi, > > That is simple. > In the .mhs file if I want to assign a constant value of 1 to fsl port 0 > and also to make it always ready, I just add this to the MicroBlaze block. > > PORT FSL0_S_DATA = 0b00000000000000000000000000000001 > PORT FSL0_S_CONTROL = 0b0 > PORT FSL0_S_EXISTS = 0b1 > > Göran > > TheMightyShaman wrote: > >> Göran Bilski <goran.bilski@xilinx.com> wrote in message >> news:<cv294c$bmv3@cliff.xsj.xilinx.com>... >> >>> Since both processors starts at address 0, they will start to execute >>> the same initialization code. >>> You need to use a FSL port with different constant signals for each >>> MicroBlaze. >> >> >> >> Dear Mr. Bilski, sorry for the intromission. Just a question: how you >> can declare a FSL port with constant signals without defining a custom >> FSL core? >> >> Thank you very much!Article: 79806
morpheus wrote:
> I'm kinda new in the business so this question may be very rookie.
> Anyways, I was wondering if all synchronous designs need to be state
> machine based designed or the synchronous behaviour can be modelled
> using multiple clocked processes like always (in Verilog) blocks
> activated by clock to do the same thing.
A synchronous design entity (module)
contains one or more
clocked processes (always blocks).
A clocked process that updates an
enumerated local variable rather than
a vector or integer is sometimes called
a state machine. A single clocked process
can also update multiple process variables.
-- Mike Treseler
Article: 79807"Rob Barris" <rbarris@mac.com> schrieb im Newsbeitrag news:rbarris-048FF4.23270823022005@news.newsguy.com... > I have a simple binary FSK demodulator circuit based on the old 74HC297 Ahh, my beloved PLL ;-)) > DPLL, a divide-by-4 counter, and a flip flop. I'm interested in seeing > how many such circuits I could pack into a cheap FPGA like one of these: > but I'm not sure where to start. I'm just trying to figure out a > ballpark number, i.e. "one copy will just barely fit" or "seems like you > should be able to get five copies in there with room to spare". Just have a look at the inside schematics of the 297. There you see serval counter (K, ID counter). Count the FlipFlops required for the Countners. In a CPLD, you have 1 FlipFlop in every macrocell. If you really want to put it into a FPGA, even the smallest can hold a dozen of them. > Is this a common kind of problem - translating old-school discrete chip > designs into FPGA? I did a lot of googling for resources along this > vein but didn't come up with much. More or less. Regards FalkArticle: 79808
"Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:cvjoo2$48r$1@nobel.pacific.net.sg... <snip> > MK, > > I am a big advocate of keeping marketing and PRs out of the > news group. But I must admit, that the way Austin did it, is > the way I would like for all non technical items to be posted > here: short link. > > It is obvious from the link that it is a PR NEWS article, and > you can skip it if it does not interest you. > > I think we are wasting more bandwidth by having this non > technical "complain" thread than Austins original post. > > Keep it up Austin ! <snip> It would be nice to have something closer to the "original" source by linking to the news at Xilinx.com. Why go to Yahoo? To add credibility? It's a news release!Article: 79809
Hi all, I try to make a system with a chipscope in it. I want to try it to know if this tools what we think they suppose to do. So here what i have done: 1 - create a new system with a microblaze in it. 2- debug to none 3- memory blok 8K 4- i juste take the default peripheral in the rest of the wizzard 5-put the chiscope_icon 6- put the chipscope_ila 7- try to make the bitstream and the result: ERROR:NgdBuild:455 - logical net 'ilmb_LMB_BE<0>' has multiple drivers. The possible drivers causing this are: pin G on block XST_GND with type GND, pin O on block chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/chipscope_ila_0/i_no_d/u_il a/u_dout with type LUT3 I don't know how to correct this error. Do I have to change something else in the ilmb ? regards JonathanArticle: 79810
John_H, That is where I found it. Austin John_H wrote: > "Rudolf Usselmann" <russelmann@hotmail.com> wrote in message > news:cvjoo2$48r$1@nobel.pacific.net.sg... > <snip> > >>MK, >> >>I am a big advocate of keeping marketing and PRs out of the >>news group. But I must admit, that the way Austin did it, is >>the way I would like for all non technical items to be posted >>here: short link. >> >>It is obvious from the link that it is a PR NEWS article, and >>you can skip it if it does not interest you. >> >>I think we are wasting more bandwidth by having this non >>technical "complain" thread than Austins original post. >> >>Keep it up Austin ! > > <snip> > > It would be nice to have something closer to the "original" source by > linking to the news at Xilinx.com. Why go to Yahoo? To add credibility? > It's a news release! > >Article: 79811
blackduck wrote: > Actually the problem is as you said, 250 filters are giving me at time > n 250 different values, then i need to get the addition of those 250 > values at time n+1, and this new value conforms an input for a > comparator. Each data is a 32 bits unsigned integer, which is generated > by a lowpass filter at 300MHz, is in fact the impulse response of such > a filter. As you say, carry save adders may be the best way. It is still a lot of logic, and will take some number of FPGAs to do. You probably won't get them by time n+1, but you can pipeline it so that you can get a new result out every clock cycle. An N bit carry save adder turns three N bit numbers into two N bit numbers. Before you do that, you should be sure that it is significantly faster than the carry chain adder in your FPGA. At 300MHz you might get only one set of adders per pipeline stage, though maybe more. Assuming it is one, each stage reduces the numbers by a factor of (2/3). log(250)/log(1.5)=14 In the end, you should end up with a 40 bit sum, so some of the adders will be 40 bits long. If you can do it with carry chain adders log(250)/log(2)=8, so eight levels of adders. If the carry chain adders will run at 300MHz, pipelining those is probably the best way to do it. (Given the FFs in each CLB.) It may take up to 14 clock cycles but you will get one result out each cycle. Find a book with a name similar to "Architecture of Pipelined computers", probably from the 1970's or 1980's, or look up the IBM 360/91 or Cray-1. -- glenArticle: 79812
A while back, I tried adding chipscope to an existing PPC design, and it broke the design. I ended up using the ChipSope Inserter tool instead, and was happy with the results. As a first attempt, I would use the inserter method. - Newman "Jonathan Dumaresq" <jdumaresq@cimeq.qc.ca_nospam> wrote in message news:e9oTd.46341$6f.18104@charlie.risq.qc.ca... > Hi all, > > I try to make a system with a chipscope in it. > > I want to try it to know if this tools what we think they suppose to do. > > So here what i have done: > > 1 - create a new system with a microblaze in it. > 2- debug to none > 3- memory blok 8K > 4- i juste take the default peripheral in the rest of the wizzard > 5-put the chiscope_icon > 6- put the chipscope_ila > 7- try to make the bitstream > > and the result: > > ERROR:NgdBuild:455 - logical net 'ilmb_LMB_BE<0>' has multiple drivers. > The > > possible drivers causing this are: > > pin G on block XST_GND with type GND, > > pin O on block > > chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/chipscope_ila_0/i_no_d/u_il > > a/u_dout with type LUT3 > > I don't know how to correct this error. > > Do I have to change something else in the ilmb ? > > regards > > Jonathan > > > >Article: 79813
On 24 Feb 2005 06:17:15 -0800, "Newman" <newman5382@yahoo.com> wrote: > >I heard the EDK 6_3 Eval CD's have started to ship. > >- Newman I wrote Xilinx a couple of days ago , and asked if they would ship an ISE 6.3 eval along with the edk 6.3 eval , for all of us that have gotten ISE 6.2 with our starterkit , its my impression you need ISR 6.3 to use EDK 6.3. The ansver was that they just ship the EDK ....... Thats seems a bit silly , now i have to try to get a new eval (its free) and pay shipment , even though they could just have slipped it into the edk shipment. CarstenArticle: 79814
Christof For Uni's, Xess boards are great as they are cheap well specified and well supported. Also you can get a Diligent board free from Xilinx. Cost per Flip Flop is not usually the critical issue. Tom "Christof" <cpaar@crypto.rub.de> wrote in message news:7aaba7e2.0502221415.6548b962@posting.google.com... > For a university project we are looking for FPGA boards which offer > the best possible cost/CLB ratio. We are interested in realizing a > system with a large number (possibly hundreds) FPGAs running in > parallel. Both single FPGA or multiple FPGA boards are an option as > long as the price per logic function is "optimum". > > Thanks a lot, ChristofArticle: 79815
"Stephen Maudsley" <news2@sjmaudsley.fsnet.co.uk> schrieb im Newsbeitrag news:ASSY1782D514B@assayer.co.uk... > Like you I suspect that there is some data folding somewhere - at the moment > this device has an 80 Giga samples/second input - should be able to make the > coffee as well... Or maybe its just a miscommunication. Maybe the OP just needs a FIR with 250 TAPs running @ 300 MHz. OK, 300 MHz is quite fast, but a FIR can be nicely pipelined, so that each MAC unit just needs to add 2 numbers within 1 clock cycle. Regards FalkArticle: 79816
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> schrieb im Newsbeitrag news:cvl3q9$rpl$1@gnus01.u.washington.edu... > blackduck wrote: > > > Actually the problem is as you said, 250 filters are giving me at time > > n 250 different values, then i need to get the addition of those 250 > > values at time n+1, and this new value conforms an input for a > > comparator. Each data is a 32 bits unsigned integer, which is generated > > by a lowpass filter at 300MHz, is in fact the impulse response of such Aha, but this filter does not output 250 samples every clock, its just 1 sample, isnt it? Otherwise, how will you just handle the transfer of 250x32 = 8000 Bit every 300 MHz clock cycle?? Not even thinking off adding them up in one clock cycle. Regards FalkArticle: 79817
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:386nsrF5kj96gU2@individual.net... > > "glen herrmannsfeldt" <gah@ugcs.caltech.edu> schrieb im Newsbeitrag > news:cvl3q9$rpl$1@gnus01.u.washington.edu... > > blackduck wrote: > > > > > Actually the problem is as you said, 250 filters are giving me at time > > > n 250 different values, then i need to get the addition of those 250 > > > values at time n+1, and this new value conforms an input for a > > > comparator. Each data is a 32 bits unsigned integer, which is generated > > > by a lowpass filter at 300MHz, is in fact the impulse response of such > > Aha, but this filter does not output 250 samples every clock, its just 1 > sample, isnt it? Otherwise, how will you just handle the transfer of 250x32 > = 8000 Bit every 300 MHz clock cycle?? With a lot of pins? :-) Alun HarfordArticle: 79818
Falk Brunner wrote: (snip) > Or maybe its just a miscommunication. Maybe the OP just needs a FIR with 250 > TAPs running @ 300 MHz. OK, 300 MHz is quite fast, but a FIR can be nicely > pipelined, so that each MAC unit just needs to add 2 numbers within 1 clock > cycle. The source wasn't mentioned, but it makes sense that it would be an FIR filter. If there are already 250 multipliers then the adders shouldn't be much more work. A 250 stage pipeline should be simpler than the pipelined adder tree to add 250 numbers. Though the first use of carry-save adders I knew about was pipelined multipliers. It is possible that they are the outputs from the multiplier before they are added together. Also, it may be that 250 cycle latency is too long. More information about the system would help. -- glenArticle: 79819
I have been looking at the idea of implementing the microcontroller function into the FPGA using either Microblaze or NiosII. Does anyone have experience with these two products?How good is the software development environment. Does it include breakpoints and examination of register and memory variables? I do appriciate to tell me your experience with Microblaze and NiosII.Article: 79820
governer@gmail.com wrote: > Hi all > Does anyone know what is the cheapest 3.3V CPLD available? > My desing uses 31 macrocells, and 33 I/O. Currently using Xilinx > XC9536XL available for around US$0.70 a piece (for 100k quantities). > The design is pretty slow GCK~2MHz. I need 100k+ quantities. > Thanks > ZK Look also at the Lattice ispMACH4032, and the Atmel ATF1502ASV, and maybe Coolrunner but the pure 3.3V may be a problem... -jgArticle: 79821
Hi,
My goal is to use XPower to estimate the average and the peak power for
a given run of a system with at least a reasonable level of accuracy.
Tools used are:
Xilinx Platform Studio 6.2.03i
Xilinx Project Navigator 6.2.03i
ModelSim SE 5.7g
In order to test out the framework for evaluating power (Xpower), I have
designed a Microblaze-based system with a software containing simple
multiplication of two numbers. The whole system along with its
simulation model was generated using XPS.
I am using the post-place&route simulation model to generate the VCD
file. The system is triggered with its external inputs clk and rst
(using a testbench.vhd) and simulation is run till the software (that
was hard-coded in bram_init.vhd) produced the expected output. The
commands used to add signals (before simulation) to VCD are as follows:
------------------------------------------------------------
vcd file system.vcd
vcd add testbench/uut/*
vcd add testbench/uut/microblaze_0/*
vcd add testbench/uut/microblaze_0/microblaze_0/*
vcd add testbench/uut/microblaze_0/microblaze_0/iopb_interface_i/*
vcd add testbench/uut/microblaze_0/microblaze_0/dopb_interface_i/*
vcd add testbench/uut/microblaze_0/microblaze_0/decode_i/*
vcd add testbench/uut/microblaze_0/microblaze_0/data_flow_i/*
vcd add testbench/uut/microblaze_0/microblaze_0/byte_doublet_handle_i/*
vcd add testbench/uut/bram_block_0/*
vcd add testbench/uut/bram_block_0/bram_block_0/*
vcd add testbench/uut/lmb_bram_if_cntlr_0/*
vcd add testbench/uut/lmb_bram_if_cntlr_0/lmb_bram_if_cntlr_0/*
vcd add
testbench/uut/lmb_bram_if_cntlr_0/lmb_bram_if_cntlr_0/pselect_mask_lmb/*
vcd add testbench/uut/lmb_bram_if_cntlr_1/*
vcd add testbench/uut/lmb_bram_if_cntlr_1/lmb_bram_if_cntlr_1/*
vcd add
testbench/uut/lmb_bram_if_cntlr_1/lmb_bram_if_cntlr_1/pselect_mask_lmb/*
vcd add testbench/uut/opb_mdm_0/*
vcd add testbench/uut/opb_mdm_0/opb_mdm_0/*
vcd add testbench/uut/opb_mdm_0/opb_mdm_0/mdm_core_i1/*
vcd add testbench/uut/opb_timer_0/*
vcd add testbench/uut/opb_timer_0/opb_timer_0/*
vcd add testbench/uut/lmb_v10_0/*
vcd add testbench/uut/lmb_v10_0/lmb_v10_0/*
vcd add testbench/uut/lmb_v10_0/lmb_v10_0/por_srl_i/*
vcd add testbench/uut/lmb_v10_0/lmb_v10_0/por_ff_i/*
vcd add testbench/uut/lmb_v10_1/*
vcd add testbench/uut/lmb_v10_1/lmb_v10_1/*
vcd add testbench/uut/lmb_v10_1/lmb_v10_1/por_srl_i/*
vcd add testbench/uut/lmb_v10_1/lmb_v10_1/por_ff_i/*
vcd add testbench/uut/opb_v20_0/*
vcd add testbench/uut/opb_v20_0/opb_v20_0/*
vcd add testbench/uut/opb_v20_0/opb_v20_0/por_srl_i/*
vcd add testbench/uut/opb_v20_0/opb_v20_0/por_ff_i/*
vcd add testbench/uut/opb_v20_0/opb_v20_0/opb_arbiter_i/*
vcd add testbench/uut/bufgp_0/*
vcd add testbench/uut/ibuf_1/*
------------------------------------------------------------
Then I tried running XPower with the generated VCD file with '-v -a'
option. It reported the following:
WARNING:Power:760 - Only 10% of the register output signals have been set.
WARNING:Power:762 - Only 12% of the design signals have been set.
WARNING:Power:763 - Only 6% of the design signals toggle.
INFO:Power:556 - Estimate is inaccurate based on analysis of the design,
user input and characterization data.
------------------------------------------------------------
XPower generated the following power numbers but with an inaccurate
confidence level.
------------------------------------------------------------
Power summary: I(mA) P(mW)
----------------------------------------------------------------
Total estimated power consumption: 930
Peak Power consumption: 16818
---
Vccint 1.50V: 400 600
Vccaux 3.30V: 100 330
---
Clocks: 140 210
Logic: 88 132
Signals: 22 33
Inputs: 0 0
---
Quiescent Vccint 1.50V: 150 225
Quiescent Vccaux 3.30V: 100 330
Startup Vccint 1.5V: 400
Startup Vccaux 3.3V: 100
---
Package power limits, ambient 25C: 5455
250 LFM: 8451
500 LFM: 10345
750 LFM: 12245
Thermal summary:
----------------------------------------------------------------
Estimated junction temperature: 35C
250 LFM 32C
500 LFM 30C
750 LFM 30C
Ambient temp: 25C
Case temp: 35C
Theta J-A range: 11 - 11C/W
---
Max ambient at junction max of 85C: 75C
250 LFM 78C
500 LFM 80C
750 LFM 80C
Decoupling Network Summary: Cap Range (uF) #
----------------------------------------------------------------
Capacitor Recommendations:
Total for Vccint : 44
470.0 - 1000.0 : 1
4.70 - 10.00 : 2
0.470 - 2.200 : 5
0.0470 - 0.2200 : 8
0.0100 - 0.0470 : 14
0.0010 - 0.0047 : 14
---
Total for Vccaux : 8
470.0 - 1000.0 : 1
0.0470 - 0.2200 : 1
0.0100 - 0.0470 : 2
0.0010 - 0.0047 : 4
---
------------------------------------------------------------
My questions are the following:
(1) How to achieve a confidence level of at least "reasonable" if not
"accurate"?
Observation: A file called "systemfailed.txt" was also generated
reporting "activity not set" error messages for a lot of signals which I
can see in the VCD file to have changed values. The error messages were
like (Signal "microblaze_0/microblaze_0/Decode_I/of_PipeRun_s_I" has not
had its activity set.)
(2) My clock frequency is 50 MHz. There were several warnings reported
of the kind: "WARNING:Power:91 - Can't change frequency of net sys_clk
to 5000.00Mhz." I don't know what to infer from there?
Following warnings were also generated:
------------------------------------------------------------
r:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to 0.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
5000.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net sys_clk to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net bufgp_0/IBUFG to 50.00Mhz.
WARNING:Power:91 - Can't change frequency of net conn_0_bram_clk to
50.00Mhz.
parsing completed in: 2 mins 33 secs
WARNING:Power:760 - Only 10% of the register output signals have been set.
WARNING:Power:762 - Only 12% of the design signals have been set.
WARNING:Power:763 - Only 6% of the design signals toggle.
WARNING:Power:760 - Only 10% of the register output signals have been set.
WARNING:Power:762 - Only 12% of the design signals have been set.
WARNING:Power:763 - Only 6% of the design signals toggle.
------------------------------------------------------------
I am repeating my questions here in case you have missed:
(1) How to achieve a confidence level of at least "reasonable" if not
"accurate"?
Observation: A file called "systemfailed.txt" was also generated
reporting "activity not set" error messages for a lot of signals which I
can see in the VCD file to have changed values. The error messages were
like (Signal "microblaze_0/microblaze_0/Decode_I/of_PipeRun_s_I" has not
had its activity set.)
(2) My clock frequency is 50 MHz. There were several warnings reported
of the kind: "WARNING:Power:91 - Can't change frequency of net sys_clk
to 5000.00Mhz." I don't know what to infer from there?
Any clue to solve the problems with XPower will be highly appreciated.
Thanks and Regards,
Partha.
Article: 79822spartan wrote: > I have been looking at the idea of implementing the microcontroller > function into the FPGA using either Microblaze or NiosII. Does anyone > have > experience with these two products?How good is the software development > environment. Does it include breakpoints and examination of register and > memory variables? I do appriciate to tell me your experience with > Microblaze and NiosII. > > Hi, The report in http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf might come handy to you at this point. Regards, Partha.Article: 79823
Hi, We are using a virtex4 FPGA to prototype a DSP processor to be implemented in an ASIC. We are using the ISE flow and everything works fine except that we can't prototype at full speed. We are only able to run at about 65MHz, which is far from the 150MHz target. The longest combinationnal path is in the MAC, which contains a 28x28 multiplier followed by a 56x56 adder. I created the multiplier and the adder using Core Generator. Is there a way to speed this up? The virtex4 have those Xtreame DSP slices, but I can't find a way to to make good use of them, since our datapath is so large. Thank you, DavidArticle: 79824
gretzteam wrote: > We are using a virtex4 FPGA to prototype a DSP processor to be > implemented in an ASIC. We are using the ISE flow and everything works > fine except that we can't prototype at full speed. We are only able to > run at about 65MHz, which is far from the 150MHz target. The longest > combinationnal path is in the MAC, which contains a 28x28 multiplier > followed by a 56x56 adder. I created the multiplier and the adder > using Core Generator. > Is there a way to speed this up? The virtex4 have those Xtreame DSP > slices, but I can't find a way to to make good use of them, since our > datapath is so large. Virtex4 has 18x18 multiplier hardware. Your 28x28 may be made from them, but you need to pipeline it, and also a pipeline stage before the adder. I will guess that gets to 150MHz, but you will have to try it to find out. -- glen
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