Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Engineering Guy wrote: > Andy Peters wrote: > >> I'm sure others have this problem ... >> >> Is there a tool that'll let one view and hopefully print a schematic >> done in the old Xilinx F2.1i schematic tool? The new stuff doesn't >> want to know about the old stuff, and worse is that you can't even >> install 2.1i on an XP machine. (Yeah, that'll teach me to upgrade.) >> >> I don't want to do anything with this schematic other than view it. >> I'm doing a new board sorta based on an old design, and the new design >> will of course be in VHDL rather than as a schematic. >> >> Ideas? >> >> -a >> > > > Aldec's tool Active-HDL has capability of importing the Foundation > schematics and entire projects. The import utility not only allows > printing, but also importing these files into their format, maintain and > even convert into an HDL design that can be targeted for any > family/device. They show this capability on their website: > http://downloads.aldec.com/Previews/Presentations/IP_Core.html > > eg Oops sorry, wrong link: http://downloads.aldec.com/Previews/Presentations/Active-XE_Edition.htmlArticle: 82501
hi i m a student working in quartus II environment.i wnated to design my own byteblaster can anybody help me out.i have gone through the altera byteblaster II download cable .will the schematci given there work.it will be a great help to me if anyone of u could help me out thanksArticle: 82502
"Stephane" <stephane@nospam.fr> schrieb im Newsbeitrag news:d3jggu$kpo$1@ellebore.extra.cea.fr... > Antti Lukats wrote: > > "Stephane" <stephane@nospam.fr> schrieb im Newsbeitrag > > news:d3j43r$e32$1@ellebore.extra.cea.fr... > > > >>Fcclk max = 100 MHz > >> > >>bitstream of VLX25 = 7.4 Mbit > >> > >>SelectMAP port width = 32 bits > > > > > > NO, 8 bits > > > > > > > I don't agree with you: here are the 32 configuration data bits: > > PAD209 X27Y127 IOB_X1Y127 F14 1 IO_L1P_D31_LC_1 those are Local Clock, the SelectMAP is 8 bit wide !!!! > PAD210 X27Y126 IOB_X1Y126 F13 1 IO_L1N_D30_LC_1 > PAD211 X27Y125 IOB_X1Y125 F12 1 IO_L2P_D29_LC_1 > PAD212 X27Y124 IOB_X1Y124 F11 1 IO_L2N_D28_LC_1 > PAD213 X27Y123 IOB_X1Y123 F16 1 IO_L3P_D27_LC_1 > PAD214 X27Y122 IOB_X1Y122 F15 1 IO_L3N_D26_LC_1 > PAD215 X27Y121 IOB_X1Y121 D14 1 IO_L4P_D25_LC_1 > PAD216 X27Y120 IOB_X1Y120 D13 1 IO_L4N_D24_VREF_LC_1 > PAD217 X27Y119 IOB_X1Y119 D15 1 IO_L5P_D23_LC_1 > PAD218 X27Y118 IOB_X1Y118 E14 1 IO_L5N_D22_LC_1 > PAD219 X27Y117 IOB_X1Y117 C11 1 IO_L6P_D21_LC_1 > PAD220 X27Y116 IOB_X1Y116 D11 1 IO_L6N_D20_LC_1 > PAD221 X27Y115 IOB_X1Y115 D16 1 IO_L7P_D19_LC_1 > PAD222 X27Y114 IOB_X1Y114 C16 1 IO_L7N_D18_LC_1 > PAD223 X27Y113 IOB_X1Y113 E13 1 IO_L8P_D17_CC_LC_1 > PAD224 X27Y112 IOB_X1Y112 D12 1 IO_L8N_D16_CC_LC_1 > PAD225 X27Y79 IOB_X1Y79 AA14 2 IO_L1P_D15_CC_LC_2 > PAD226 X27Y78 IOB_X1Y78 AB14 2 IO_L1N_D14_CC_LC_2 > PAD227 X27Y77 IOB_X1Y77 AC12 2 IO_L2P_D13_LC_2 > PAD228 X27Y76 IOB_X1Y76 AC11 2 IO_L2N_D12_LC_2 > PAD229 X27Y75 IOB_X1Y75 AA16 2 IO_L3P_D11_LC_2 > PAD230 X27Y74 IOB_X1Y74 AA15 2 IO_L3N_D10_LC_2 > PAD231 X27Y73 IOB_X1Y73 AB13 2 IO_L4P_D9_LC_2 > PAD232 X27Y72 IOB_X1Y72 AA13 2 IO_L4N_D8_VREF_LC_2 > PAD233 X27Y71 IOB_X1Y71 AC14 2 IO_L5P_D7_LC_2 > PAD234 X27Y70 IOB_X1Y70 AD14 2 IO_L5N_D6_LC_2 > PAD235 X27Y69 IOB_X1Y69 AA12 2 IO_L6P_D5_LC_2 > PAD236 X27Y68 IOB_X1Y68 AA11 2 IO_L6N_D4_LC_2 > PAD237 X27Y67 IOB_X1Y67 AC16 2 IO_L7P_D3_LC_2 > PAD238 X27Y66 IOB_X1Y66 AC15 2 IO_L7N_D2_LC_2 > PAD239 X27Y65 IOB_X1Y65 AC13 2 IO_L8P_D1_LC_2 > PAD240 X27Y64 IOB_X1Y64 AD13 2 IO_L8N_D0_LC_2 > > >>so the minimum reconfiguration time for this part should be a little bit > >>more than 7.4/100/32 = 2.3ms > >> > >>correct? > > > > > > NO, see above > > > > > >>Is the same CCLK freq sustainable thru ICAP? > > > > > > usually is ICAP way slower than max CCLK > > Very interesting! Any figure? > there is very little numbers on V4 ICAP but usually the ICAP is way slower than selectmap, reason unknown anttiArticle: 82503
Paul Hartke wrote: > http://support.xilinx.com/xlnx/xil_tt_faq.jsp?iLanguageID=1&sProduct=MXE+III#139 > > Q11 Can MXE III simulate the Xilinx PPC405 and Gigabit I/O SWIFT Models? > No -- to simulate SWIFT models, you will need a SWIFT-compliant > simulator such as ModelSim SE, ModelSim PE, Synopsys VCS, or Cadence > NC-Sim. Riviera and Active-HDL from Aldec also support the SWIFT models as well. > > stockton wrote: > >>Dear All, >> >>Is the answer to the following question, "You Can't!" and does this >>mean that there is such a word as "can't"? >> >>Question: How can one simulate the Rocket I/O MGT block in ModelSim >>XE? >> >>Cheers >> >>SimonArticle: 82504
Stephane wrote: > Antti Lukats wrote: > > "Stephane" <stephane@nospam.fr> schrieb im Newsbeitrag > > news:d3j43r$e32$1@ellebore.extra.cea.fr... > > > >>Fcclk max = 100 MHz > >> > >>bitstream of VLX25 = 7.4 Mbit > >> > >>SelectMAP port width = 32 bits > > > > > > NO, 8 bits > > > > > > > I don't agree with you: here are the 32 configuration data bits: > > <snip> > > >>so the minimum reconfiguration time for this part should be a little bit > >>more than 7.4/100/32 = 2.3ms > >> > >>correct? > > > > > > NO, see above > > > > > >>Is the same CCLK freq sustainable thru ICAP? > > > > > > usually is ICAP way slower than max CCLK > > Very interesting! Any figure? > > > > > Antti > > > > >From the Virtex-$ Configuration Guide (UG071) page 33: The SelectMAP configuration interface (Figure 2-11) provides an 8-bit bidirectional data bus interface to the Virtex-4 configuration logic that can be used for both configuration and readback. (For details, refer to Chapter 8, "Readback and Configuration Verification.") Regards, John McCaskillArticle: 82505
I'm using a VII Pro in a current project which requires the use of the RocketIO. This runs on 2.5V and I've selected a regulator, capacitors etc. in accordance with the RIO UG. Can I run other parts of the chip using the same regulator or should the RIO be considered special enough to warrant its own regulator and I need a 2nd 2.5V regulator for Vcco, Vccaux etc.? TIA, Rog.Article: 82506
Nemesis wrote:
> Hi all,
> I'm trying to test a filter I implemented with Xilinx ISE 6.1, so I
> created a testbench waveform. I'd like to import the input waveform from
> an ASCII file because the Pattern Generator can create only simple
> patterns.
>
Try something like this:
-- Copyright (c) 2003-2005 by Aldec, Inc. All rights reserved.
--
------------------------------------------------------------------------------------
--
-- Created on Wednesday 2005-04-13, 19:37:24
--
------------------------------------------------------------------------------------
-- Details:
-- Type: Clocked file stimulus
-- Data width: 16
-- Radix of values stored in the file is binary
-- Clock input CLK sensitive to rising edge
-- Clock enable input CE active high
-- Output Q
------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {file_stim_clkd} architecture {file_stim_arch}}
library IEEE;
use IEEE.std_logic_1164.all;
entity file_stim_clkd is
port(
CLK : in std_logic;
CE : in std_logic;
Q : out std_logic_vector(15 downto 0)
);
end entity;
--}} End of automatically maintained section
library IEEE;
use STD.textio.all;
use IEEE.std_logic_textio.all;
architecture file_stim_arch of file_stim_clkd is
constant file_name : string(1 to 12) := "stimulus.txt";
file stimulus : text open READ_MODE is file_name;
begin
reader : process
variable line_read : line;
variable signal_val : std_logic_vector(15 downto 0);
begin
processing : while not endfile(stimulus) loop
readline(stimulus, line_read);
read(line_read, signal_val);
wait until (CE='1' and rising_edge(CLK));
Q <= signal_val;
end loop processing;
report "Reached the end of the file:" & file_name & '.'
severity NOTE;
file_close(stimulus);
wait;
end process reader;
end architecture;
Article: 82507Hi, ALL! Recently one of my friends faced very strange problem. He had the MicroBlaze CPU in his design running with 50MHz clock speed. He also had external SDRAM module and his application was executing out of external SDRAM memory. During first few benchmark tests he realized that it takes about 24 clock cycles to access memory :( This means that cool embedded 50MHz MicroBlaze CPU runs slower than poor external 8MHz AVR. After my advice he enabled the cache within MicroBlaze, but application execution speed did not increased significantly. As he described later, this was one of hand-on samples from EDK. May be the sample is not optimized for performance and very simplified, but net performance of 2MHz processor is not even close to advertised by Xilinx :( Could any one give any comment on that? Regards, Vladimir S. MirgorodskyArticle: 82508
you must keep them seperate. The UG states this.Article: 82509
On Wed, 13 Apr 2005 03:44:48 GMT, Kelly Hall <khall@acm.org> wrote: >A Chinese F-8 and a US EP-3 collided during an intercept; the F-8 was >lost and the EP-3 performed an emergency landing at Hainan airfield. A >fairly standard cock-up between great powers. And I'm certain that it wasn't deliberate just to hand bogus equipment to the Chinese. (Excuse me, somebody's knocking on my door.) -- #include <standard.disclaimer> _ Kevin D Quitt USA 91387-4454 96.37% of all statistics are made up Per the FCA, this address may not be added to any commercial mail listArticle: 82510
Hello, Is there a way to do performance monitoring on the PPC405 in the Virtex II Pro? I am specifically interested in cache hits. I have wedged my own device between the CPU's instruction and data PLB interfaces and can currently get cache misses. But I need to find a way to determine cache hits of an application running under an operating system. If it was stand alone I could figure that information out by the number of load and store instructions, but this is an operating system with context switches, interrupt handlers, etc. Is there a way to gather this information? There did not seem to be any performance monitoring registers as seen with newer PowerPC and x86 systems. Can the trace port be used to passively monitor execution for load/store instructions? Thank you, TonyArticle: 82511
Hi Clemens, Here are the replies to your questions. "Unlike the MAX+PLUS=AE II software and earlier versions of the Quartus II software, Quartus II software versions 2.1 and later do not support pre-compiled libraries. Was there a special reason (of course there was :P) to drop this feature? " We replaced the original VHDL and Verilog front-end in Quartus with a solution that couldn't support the pre compiled library feature, buth otherwise provided us with very robust language support, than what was present in prior versions of Quartus. "When I write "my_lib" to File -> File Properties -> Library for the packages I want to be part of "my_lib" things work as desired. But the vhdl "library" is not reflected in the file system like new directory or similar. Am I right in the assumption that the library mechanism only allows to group elements in libraries within one single project and not to generate a library that then can be passed around and used in other projects _as Library_?" You are correct. The Library field simply specifies the logical namespace for the design units in a file. Quartus does not support precompiled libraries, where the software would parse the design files and dump the parse trees into a specific directory, much like Modelsim. Instead, Quartus II parses design files on each invocation to quartus_map.exe; it doesn't store a representation of the parse trees on disk. "A last question: Is the library name I entered (as described above) as proberty of a VHDL file in any way related to libraries listed in Assignments -> Settings -> User Libraries? " No, it isn't. User Libraries are directories in which Quartus II searches for project source files. The naming of the feature is a bit unfortunate and historic. It should've been named Include Directories. Hope this helps, Subroto Datta Altera CorpArticle: 82512
Andy Peters wrote: > I'm sure others have this problem ... > > Is there a tool that'll let one view and hopefully print a schematic > done in the old Xilinx F2.1i schematic tool? The new stuff doesn't > want to know about the old stuff, and worse is that you can't even > install 2.1i on an XP machine. (Yeah, that'll teach me to upgrade.) > > I don't want to do anything with this schematic other than view it. > I'm doing a new board sorta based on an old design, and the new design > will of course be in VHDL rather than as a schematic. > > Ideas? > > -a I'm running Xilinx Foundation 4.1i on Windows XP (SP1). It will read (and convert) 2.1i schematics. I also run ISE 6.1i on the same machine and can switch back and forth (but not run both simultaneously) by changing the Xilinx environment variable. Unfortunately Xilinx and Aldec have parted ways, so I don't know how you can get a copy of foundation 4.1i now if you don't already have it. Version 4.1i also has the ability to output (structural) VHDL from your schematics, but it's not very readable and you'll need to be sure your new environment has the equivalent library components if you want to build from the VHDL.Article: 82513
> > > >> I'm sure others have this problem ... > >> > >> Is there a tool that'll let one view and hopefully print a schematic > >> done in the old Xilinx F2.1i schematic tool? The new stuff doesn't > >> want to know about the old stuff, and worse is that you can't even > >> install 2.1i on an XP machine. (Yeah, that'll teach me to upgrade.) > >> > >> I don't want to do anything with this schematic other than view it. > >> I'm doing a new board sorta based on an old design, and the new design > >> will of course be in VHDL rather than as a schematic. > >> > > Aldec's tool Active-HDL has capability of importing the Foundation > > schematics and entire projects. The import utility not only allows > > printing, but also importing these files into their format, maintain and > > even convert into an HDL design that can be targeted for any > > family/device. They show this capability on their website: > > http://downloads.aldec.com/Previews/Presentations/IP_Core.html > > > Oops sorry, wrong link: > http://downloads.aldec.com/Previews/Presentations/Active-XE_Edition.html I have this same problem. The new Foundation can import back to version 4. Because of a lawsuit between Aldec and Xilinx, they can not ship older versions of the Foundation tools. The newest Aldec tools can't seem to import the 2.1 project. However, I was able to import the version 2.1 into version 3.1 and then read the whole project with the new Aldec tools. What a pain.Article: 82514
http://opencollector.org/history/freecore/Build%20your%20own%20ByteBlaster!.htm try this site. Or altera practacally gives away the schematic in the byteblaster manual. http://www.altera.com/literature/ug/ug_bbii.pdf Google is your friend :)Article: 82515
Hello group. Regrettably, I just installed 7.1 in my computer in order to try the implementation of one of my designs in the SP3E and V4 chips. As a first test, I targeted it to the same XC3S100 device I was using in 6.3 in order to make some comparisons. After some minutes and to my dismay, I was surprised that my design doesn't fit in the XC3S100 any more! 6.3 synthesized the design perfectly in ~550 slices, but now 7.1 wants more than 900 slices for it. Implementation with the same constraints is also around 25MHz slower. I checked the synthesis report and the main difference is that MUXes went from 28 to 52 in a totally different arrangement: 6.3: # Multiplexers : 28 12-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 8 16-bit 4-to-1 multiplexer : 2 1-bit 2-to-1 multiplexer : 14 4-bit 2-to-1 multiplexer : 2 8-bit 2-to-1 multiplexer : 1 7.1: # 1-bit 4-to-1 multiplexer : 16 # 1-bit 8-to-1 multiplexer : 2 # 16-bit 4-to-1 multiplexer : 27 # 16-bit 8-to-1 multiplexer : 4 # 3-bit 4-to-1 multiplexer : 1 # 4-bit 4-to-1 multiplexer : 2 I am also getting the following PACKER Warning I had never heard before: "Lut X driving carry Y can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough". Does somebody has an explanation for this? I can't believe things are so different. Maybe there are new "features" I am not aware of? Regards. -- PabloBleyerKocik pablo /"Reliable software must kill people reliably." @bleyer.org / -- Andy MickelArticle: 82516
Rudolf Usselmann <russelmann@hotmail.com> writes: > Unfortunately I am using a "unsupported OS" (FC3) ... > So I guess I am out of luck using 7.1 64 bit ... > > I have tried making sure all xilinx environment variables > are not set, and that the installation directory is empty - > I am still getting seg. fault ... Strange, I'm using FC3 and it works for me, with one inconsequential problem. It needed older versions of some libraries before it would load, but after I installed those it was fine. I posted about that on March 14: http://groups-beta.google.com/group/comp.arch.fpga/msg/4b592cb14bad823fArticle: 82517
Hi, I'm looking for a freeware or low cost program do document and illustrate the signal processing flow in my FPGA design. I'd like to use building blocks like adders, multipliers, memory, busses etc. What do you guys use to make some nice looking pictures? I don't want to spend days learning Corel Draw or something huge like that. Thanks, ReinierArticle: 82518
Does it really? So I should have one 2.5V regulator for the RIO and another regulator for the 2.5V Vccaux etc.? I didn't realise. Thanks, Rog. <jason.stubbs@gmail.com> wrote in message news:1113416138.970557.20730@l41g2000cwc.googlegroups.com... > you must keep them seperate. The UG states this. >Article: 82519
Vladmir, Interesting data point. How much did his performance increase after enabling caches? First, check to make sure that you have compiler optimization enabled. This does make a hugh difference in optimizing your software code (2-3x in some instances). I would suggest using the latest EDK 7.1 GNU compiler here. Second, in EDK 7.1 a new MCH_OPB_SDRAM memory controller was released that connects to the Xilinx CacheLink interface of MicroBlaze v4.0. This also greatly improves performance when using caches. Finally, you may want to use tools like xil_profile to see where the processor is spending a lot of its time. You may be able to improve the performance by enabling hardware features such as multiplier, divider or barrel shifter. Cheers, Shalin- v_mirgorodsky@yahoo.com wrote: > Hi, ALL! > > Recently one of my friends faced very strange problem. He had the > MicroBlaze CPU in his design running with 50MHz clock speed. He also > had external SDRAM module and his application was executing out of > external SDRAM memory. During first few benchmark tests he realized > that it takes about 24 clock cycles to access memory :( This means > that cool embedded 50MHz MicroBlaze CPU runs slower than poor external > 8MHz AVR. After my advice he enabled the cache within MicroBlaze, but > application execution speed did not increased significantly. > > As he described later, this was one of hand-on samples from EDK. May be > the sample is not optimized for performance and very simplified, but > net performance of 2MHz processor is not even close to advertised by > Xilinx :( > > Could any one give any comment on that? > > Regards, > Vladimir S. Mirgorodsky > -- ------------------------------ Shalin Sheth Embedded Applications Engineer General Products Division Spartan-3 Generation FPGAs http://www.xilinx.com/spartan3 http://www.xilinx.com/spartan3e ------------------------------Article: 82520
Pablo, Have you logged this into the hotline as a case? Best way to address new software glitches is to report them. It might be a bug, it might be a new feature. Only way to find out is to look. You can help us just by logging it in. Same amount of work as this email posting, maybe less. Austin Pablo Bleyer Kocik wrote: > Hello group. > > Regrettably, I just installed 7.1 in my computer in order to try the > implementation of one of my designs in the SP3E and V4 chips. As a first test, > I targeted it to the same XC3S100 device I was using in 6.3 in order to make > some comparisons. After some minutes and to my dismay, I was surprised that my > design doesn't fit in the XC3S100 any more! 6.3 synthesized the design > perfectly in ~550 slices, but now 7.1 wants more than 900 slices for it. > Implementation with the same constraints is also around 25MHz slower. I checked > the synthesis report and the main difference is that MUXes went from 28 to 52 > in a totally different arrangement: > > 6.3: > # Multiplexers : 28 > 12-bit 2-to-1 multiplexer : 1 > 16-bit 2-to-1 multiplexer : 8 > 16-bit 4-to-1 multiplexer : 2 > 1-bit 2-to-1 multiplexer : 14 > 4-bit 2-to-1 multiplexer : 2 > 8-bit 2-to-1 multiplexer : 1 > > 7.1: > # 1-bit 4-to-1 multiplexer : 16 > # 1-bit 8-to-1 multiplexer : 2 > # 16-bit 4-to-1 multiplexer : 27 > # 16-bit 8-to-1 multiplexer : 4 > # 3-bit 4-to-1 multiplexer : 1 > # 4-bit 4-to-1 multiplexer : 2 > > I am also getting the following PACKER Warning I had never heard before: "Lut > X driving carry Y can not be packed with the carry due to conflict with the > common signal requirement between the LUT inputs and the Carry DI/MAND pins. > This would result in an extra LUT for a feedthrough". Does somebody has an > explanation for this? > > I can't believe things are so different. Maybe there are new "features" I am > not aware of? > > Regards. >Article: 82521
Reinier wrote:
> Hi,
>
> I'm looking for a freeware or low cost program do document and
> illustrate the signal processing flow in my FPGA design. I'd like to
> use building blocks like adders, multipliers, memory, busses etc. What
> do you guys use to make some nice looking pictures? I don't want to
> spend days learning Corel Draw or something huge like that.
>
> Thanks,
> Reinier
OpenOffice has a good drawing tool ("Drawing"). You can even export directly
to several image formats, PDF and SWF (Flash).
http://www.openoffice.org
Cheers.
--
PabloBleyerKocik
pablo /"Reliable software must kill people reliably."
@bleyer.org / -- Andy Mickel
Article: 82522No. Are you gonna have a separate regulator for every single RIO you use? Of course you can use the same regulator, but you should consider isolating the noise from different (i.e. each RIO, Vccaux, Vcco) sections of your design. You might consider using a ferrite bead or two. www.murata.com Syms. "Roger" <enquiries@rwconcepts.co.uk> wrote in message news:fRe7e.21205$il.15556@newsfe5-win.ntli.net... > Does it really? So I should have one 2.5V regulator for the RIO and another > regulator for the 2.5V Vccaux etc.? I didn't realise. > > Thanks, > > Rog. > > <jason.stubbs@gmail.com> wrote in message > news:1113416138.970557.20730@l41g2000cwc.googlegroups.com... > > you must keep them seperate. The UG states this. > > > >Article: 82523
I started building a VHDL analysis tool tentatively called VhdlArch. http://www.confluent.org/wiki/doku.php?id=vhdlarch Currently VhdlArch only checks syntax, but soon type-checking and elaboration will be enabled. Any bug reports are appreciated! -TomArticle: 82524
greenplanet wrote: > Dear all, > > I would like to make use of the XAPP333 vhdl codes provided by Xilinx > on my Spartan 2E. It's an I2C bus controller, and I would like to make > it to run at slave mode all the time. What should I do? > And also, I don't use it with a microcontroller, so I wonder the > microcontroller interface is necessary!? > > Thanks I haven't looked at the XAPP333 code, but I2C slaves are much simpler than master so I generally roll my own. You don't need a microcontroller for this. My slave controller doesn't include the registers or the I/O buffers. It responds to a single 7-bit address and allows subaddressing to 256 locations similar to the operation of a 24C02 EEPROM. Rather than running asynchronously it uses a higher frequency clock to sample both SDA and SCL and debounce / deglitch them due to the slow rise times. Module inputs are SDA and SCL, the high-frequency clock, and an 8-bit data readback bus (for I2C read). Outputs are the subaddress (8-bits), SDA drive (high when SDA should be driven low by the FPGA), read/write direction, write pulse (to load external registers), and read pulse (for read side-effects). If you only need a single 8-bit register, the subaddress can be used as your register by disabling the auto-increment. If you have a lot if internal registers that need readback, you can instantiate (or infer) RAM to reduce the necessary readback multiplexing. Obviously read-only registers need to be multiplexed onto the readback bus. This particular version does not support clock-stretching (in case you have slow peripherals such as external DRAM). I originally wrote the code in ABEL, but I have a Verilog version (no VHDL). Write me directly if you want a copy to see how it works. The Verilog could have been more concise but it was really a manual translation from the ABEL.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z