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austin wrote: > Well, > > Since I don't know anything about 3E (I'm in APD, not GPD), I'll leave > them to comment on the speeds files. > > But, I have been burned before by folks who are not who they seem, and > as posting anonomously is everyone's right, but I don't have to look on > an anonomous posting as being from a legitimate source. And I don't > have to reply to it either. > > Austin Are we saying this posting comes from an anti Xilinx source, because he/she chooses to reduce hacking, spam etcArticle: 82751
I usually just have a look at previous posts if I don't recognize a name to see where they are coming from (rather than posting from). on Mar 11, 2:00 pm by George Mercury -another post on Compact Flash seems to be in line, unless he's a really dubious type laying out cover story then following with a dagger, nah. I also thought gmail was only beta so is not generally available to new users right now. regards I also use a dead yahoo account but doesn't seem to matterArticle: 82752
On Sun, 17 Apr 2005 12:51:44 -0700, Peter Alfke wrote: > I know that Austin's Sunday-morning concern is valid, and it stems from > previous incidents, where unfriendly people, (sometimes referred to as > Competitors) have started anonymous mudslinging campaigns. It's so easy > to do, and hard to spot. > None of us says that this is the case with George Mercury (at least he > posts a reasonable name), but anonymity is known to be an invitation to > mischief. > That's all. > Peter Alfke > PS: Austin and I always give our company affiliation. But sometimes we > are too lazy to type, or we want to demonstrate that this is personal > opnion, like this one. But nobody will ever accuse us of hiding... Peter,Austin, What does it matter if the OP is a shill or a legitimate poster? It's a simple question, is the 3E slower than the 3 or not? It's faster, slower, not fully characterized yet, are all legitimate answers. Even if the OP is attempting to slander the part all you have to do to dispel is claim is to post an answer.Article: 82753
David wrote: > There are ISE Foundation and ISE Webpack versions for Red Hat Enterprise > Linux 3.0 How strict is this port? Has anybody managed to run these > tools on Fedora or Mandrake Linux (now Mandriva), or any other Linux > variant? If so, how well did it work? I like being able to specify that it should use my Internet Explorer proxy settings... :o) I got it running in Debian (something close to sarge release). I found some instructions for getting the driver working with the 2.6 kernel, but they didn't work (looked as though I was actually building a usb driver instead of a parport driver). Incidently, the GUI actually behaves nicer running when running the Win32 version under WINE than using the Motif based version. Sigh. MartinArticle: 82754
On Sun, 17 Apr 2005 00:31:04 +0000, Phil Tomson wrote: > In article <d3s0co$4mj$1@lnx107.hrz.tu-darmstadt.de>, > Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >>Phil Tomson <ptkwt@aracnet.com> wrote: >> >>> Well, it turns out the the ISE GUI is unusable for me - it takes up to >>> several minutes to respond to mouse clicks. >> >>> However, I'd actually prefer to be able to script the whole thing. I know >>> that a while back someone posted a link to a webpage that showed how to >>> run the Xilinx tools from the command line but now I can't find it even >>> via goodle. >>> Anyone got the link? >> >>Loo at the <projectname>.cmd_log file after a successfull run of the >>GUI. You see all commands executed. > > Well, I haven't had a successful run of the GUI yet. I'll have to look > at it on a Windows machine at school. > > BTW: is it possible to set up the project without the GUI? I'm assuming > it's just some sort of text file (the project file). > > Phil I have a tool called HDLmaker that generates hierarchical Verilog, Xilinx, Synplify, and Precision projects, XST scripts, ModelSim,NCSim and VCS scripts. It also includes a library of csh scripts for running the tools. http://www.polybus.com/hdlmaker/users_guide/Article: 82755
Exsultation takes their show on the road and sets up courses in Ottawa and Toronto, contact them to see when their next Toronto event is. Jason "zilinxchip" <fakeemailaddress@fakespam.com> wrote in message news:pan.2005.04.17.19.18.54.880352@fakespam.com... > On Sun, 17 Apr 2005 10:52:25 -0400, Jason Berringer wrote: > > > Try: > > > > http://www.exsultation.com > > > > They have a good service, I took the week long course when I was starting > > out. Very useful, and definitely worth the money. > > > > Jason > > > Thanks very much Jason. > > Is there any other that you guys know of near Toronto. > > The only one I knew of was NAICS www.Naics.ca which no longer seems to > be in operation. I've tried to contact the Professor there Prof. Samary > Baranov to no avail. I feel his program is (was) excellent. Anyone know > how I can get a hold of him or if he's teaching FPGA some place else? > > Please let me know if you guys know of any other courses in or near > Toronto. > > Thank you.Article: 82756
Duane Clark wrote: > Did the drivers get reloaded after rebooting? That is, does "lsmod" show > xpc4drvr and windrvr6? I had loaded them manually, but I didn't notice that the device number had changed. Using 'install_windrvr6 windrvr6' does it properly. Anyway, it all works now, thanks. As a bonus, turning off my distributed.net background task has made the GUI run at normal speed. LJWArticle: 82757
Duane Clark wrote: > I found that behavior if I have, for example, setiathome running in the > background. Even renicing seti to priority 19 did not help. I would > suggest checking for processor intensive tasks running in the background. Thanks, that led me to stop the distributed.net background task, and the GUI went from sluggish (though only just usable) to quite snappy. LawrenceArticle: 82758
I'm interfacing a 2kx8 15ns CMOS SRAM (IDT6116SA15TP) to an Altera EPM7128SLC84-15 CPLD to implement a very simple CPU. Data and program will be stored in the SRAM which is pre-loaded via JTAG using JAM STAPL. My problem is the CPLD output buffer enable / disable delays (tZX / tXZ) which - being of the order of 7ns - are going to cause data bus contention. I'm driving the lpm_bustri OE signal and the SRAM /OE pin from (opposite senses) of the same logic. It takes the CPLD 7ns to tri-state the data bus, and the SRAM starts driving it 0ns (zero nanoseconds) after /OE is asserted. At the moment, all my RAM control signals (address, /oe, /we) change together - albeit a few nS after the rising clock edge - and the data bus tri-states a further 7ns behind them. One way to bring things into line might be to delay the other signals through LCELLs; but that would use up macrocells, and Help says not to use LCELL for delays. Is there another (better) way? BTW my clock frequency is 20 MHz.Article: 82759
To put it bluntly: Some Altera employees have in the past used this newsgroup for anonymous deceptive marketing inuendos (no, no, neither Mr Greenfield nor Paul Leventis would of course ever stoop so low. With them we can have an open and fruitful exchange). I heard that their management has ordered to stop that kind of nonsense. But it pays to be on the alert... It's just too easy to start a rumor which then "blossoms" into a 50-post thread. Peter AlfkeArticle: 82760
Mac <foo@bar.net> writes: > In my experience, the only postings which list specific salaries are the > postings by recruiters. I don't think most of those are real jobs. The > recruiters are just trying to collect resumes. One of the recruiting web sites in Silicon Valley runs amusing radio ads making fun of the other recruiters. Someone calls in to a recruiter and asks about a job that has a listing with a code "MU", and is told that it stands for made up. The ensuing conversation is something like: "So it's not a real listing?" "Oh, the listing is real, but the job doesn't exist." "What about this other one with the code 'BS'?" [pause...] "Oh, that must be from our old coding protocol." When I've dealt with recruiters, there were always real jobs associated with the listings I inquired about. But maybe that's not universally true. EricArticle: 82761
In article <1113761592.889108.25670@f14g2000cwb.googlegroups.com>, Marc Randolph <mrand@my-deja.com> wrote: > >Phil Tomson wrote: >> In article <d3s0co$4mj$1@lnx107.hrz.tu-darmstadt.de>, >> Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >> >Phil Tomson <ptkwt@aracnet.com> wrote: >> > >> >> Well, it turns out the the ISE GUI is unusable for me - it takes >up to >> >> several minutes to respond to mouse clicks. >> > >> >> However, I'd actually prefer to be able to script the whole thing. > I know >> >> that a while back someone posted a link to a webpage that showed >how to >> >> run the Xilinx tools from the command line but now I can't find it >even >> >> via goodle. >> >> Anyone got the link? >> > >> >Loo at the <projectname>.cmd_log file after a successfull run of the >> >GUI. You see all commands executed. >> >> Well, I haven't had a successful run of the GUI yet. I'll have to >look >> at it on a Windows machine at school. >> >> BTW: is it possible to set up the project without the GUI? I'm >assuming >> it's just some sort of text file (the project file). > >Howdy Phil, > > It used to be. The GUI group appears to have gone to binary project >file, at least on Windows version of ISE 7.1i - that move alone has >almost driven me away from using the VHDL flow, back to using the edif >flow. Bizarre. While the rest of the world is going to text formats like XML (even Microsoft's Visual Studio.NET now store project files as editable XML.) Xilinx decides to move to a binary format? Can anyone from Xilinx comment on the rationale for doing this? > Add the broken library support in the 7.1i VHDL flow, and it's >really case closed. Stuff like this really drives home the fact that >the developers must not use or view the tools in the the same way as >their users do. Apparently... The ability to script flows is really quite important to a lot of folks. From what you're saying they've removed that possibility. What is the 'broken library support' issue? Maybe we need someone to do for the FPGA design tools world what John Cooley (DeepChip) has done for the ASIC tools world - when stuff like this happens he takes the tool vendors to task and they listen to him. PhilArticle: 82762
In article <d3uipi$bvg$1@ucsnew1.ncl.ac.uk>, Martin Ellis <me_ncl@hotmail.com> wrote: >David wrote: > >Incidently, the GUI actually behaves nicer running when running the Win32 >version under WINE than using the Motif based version. Sigh. > I think I'm about to try running the Win32 version under Wine - pretty sad that their Linux version is so crappy. You'd think they'd have better understanding of the Linux platform than this - maybe Xilinx should hire some of us? ;-) Hopefully, Xilinx is working dumping this WindU crap for a better native toolkit like Qt (actually, they could do both their Windows AND Linux versions using Qt - no need for two different toolkits or a translator). Also (HINT, HINT) Xilinx needs to either statically link their binaries or they should ship the required shared libs with the package. Their download is already ~350MB, doing this would only add maybe 20MB and it would allow ISE to run on pretty-much any Linux distro out there. I'm not saying that they need to do testing on every Linux distro out there (that would be a major headache) - they could still claim that it's only supported on RedHat, but the large numbers of us who are no longer running RedHat could run their tools with much less hassle. PhilArticle: 82763
Hi everyone, > On 13 Apr 2005 06:21:03 -0700, "Mohammed A Khader" <am.imak@gmail.com> wrote: >>I am new to FPGA architecture. And so am I: yet another hobbyist starting out with the Spartan-3 board - and having a great time so far. >>To know the what does LUT means I came >>across few good articles posted in this group. >>But still not completely clear about it. [-8<-] Snipped a good explanation by Mr. Freidin I think I can wrap my head around the concept of the LUT allright, but the problem I'm having is that I can't find where in the Xilinx WebPack software I get to determine the contents of the LUT. I'm using the schematic capture method so far (while trying to decide whether I should learn VHDL or Verilog or both or something different alltogether). My current 'project' is simply converting the switch-inputs as BCD to 7-segments, but I've also got a binary-to-(packed)-BCD converter on the drawingboard. LUTs are great for both applications, and I have the schema all drawn up and ready to program, but I don't know where and how in the workflow I get to enter the actual contents of the LUT. Any hints on this (most likely very trivial) question would be much appreciated. Regards, Paul Boven. P.s.: any chance of a Solaris WebPack? My day-job is herding Sun machines, and that's what I run at home, too... Currently using a laptop from work for playing with the Spartan, but the boss will want to have that back soon.Article: 82764
While programming using Microblaze, I used a scanf function to read data from an input port. But I get a compilation error saying that the local memory is full. As an alterrnative to using printf, there is a xil_prinf function available. Is tere a similar function available as an alternative to scanf? Where will I get a list of all such Xilinx Specific Functions for programming Microblaze? Thanks, JohnArticle: 82765
Phil Tomson wrote:
> In article <1113761592.889108.25670@f14g2000cwb.googlegroups.com>,
> Marc Randolph <mrand@my-deja.com> wrote:
>>Howdy Phil,
>>
>> It used to be. The GUI group appears to have gone to binary project
>>file, at least on Windows version of ISE 7.1i - that move alone has
>>almost driven me away from using the VHDL flow, back to using the edif
>>flow.
>
>
> Bizarre. While the rest of the world is going to text formats like XML
> (even Microsoft's Visual Studio.NET now store project files as editable
> XML.) Xilinx decides to move to a binary format? Can anyone from Xilinx
> comment on the rationale for doing this?
There are solid version control, and user support, reasons for using
an ASCII project file, that can be shared between GUI and command line
flows.
It also has operational benefits : You use the GUI for what it is good
at ( one off set-up ), and the command line when speed and
removal-of-operator-error are important.
It can also save money - in this example, a user could set up in a
borrowed Windows GUI, then run Linux command line, knowing the
results will be (hopefully) the same.
Where I have seen moves to binary project (and design!) files in the
past, that has been driven by paranoia, and an effort to reduce
portability to the "others".
History shows that the minus side of this move, outweighed any plus
side. Fundamental rule: Do not penalise the legitimate users!
Seems to be two possible causes :
a) A novice was put in charge of the project file decision
and/or
b) The paranoia quotient really is going up at Xilinx
[see other posts ?]
Seems there are a lot of stumbles in the V7.1 release ?
-jg
Article: 82766In article <4262f6e4$1@clear.net.nz>, Jim Granville <no.spam@designtools.co.nz> wrote: >Phil Tomson wrote: >> In article <1113761592.889108.25670@f14g2000cwb.googlegroups.com>, >> Marc Randolph <mrand@my-deja.com> wrote: >>>Howdy Phil, >>> >>> It used to be. The GUI group appears to have gone to binary project >>>file, at least on Windows version of ISE 7.1i - that move alone has >>>almost driven me away from using the VHDL flow, back to using the edif >>>flow. >> >> >> Bizarre. While the rest of the world is going to text formats like XML >> (even Microsoft's Visual Studio.NET now store project files as editable >> XML.) Xilinx decides to move to a binary format? Can anyone from Xilinx >> comment on the rationale for doing this? > > There are solid version control, and user support, reasons for using >an ASCII project file, that can be shared between GUI and command line >flows. > It also has operational benefits : You use the GUI for what it is good >at ( one off set-up ), and the command line when speed and >removal-of-operator-error are important. > > It can also save money - in this example, a user could set up in a >borrowed Windows GUI, then run Linux command line, knowing the >results will be (hopefully) the same. > > > Where I have seen moves to binary project (and design!) files in the >past, that has been driven by paranoia, and an effort to reduce >portability to the "others". > > History shows that the minus side of this move, outweighed any plus >side. Fundamental rule: Do not penalise the legitimate users! > > Seems to be two possible causes : >a) A novice was put in charge of the project file decision >and/or >b) The paranoia quotient really is going up at Xilinx > [see other posts ?] But what would they be paranoid about? Are they afraid that Altera will create a Xilinx to Altera project converter or something? Even if they did so, would it really be that big of a deal? The benefits of having a user-editable ASCII project file (which you outline) seem to greatly outweigh this risk. > >Seems there are a lot of stumbles in the V7.1 release ? > Apparently. PhilArticle: 82767
print(), putnum(), and xil_printf() are the only three I am aware of. The list is in the documentation where you'd expect it to be: http://www.xilinx.com/ise/embedded/oslibs_rm.pdf (page 22) Paul fpga00@gmail.com wrote: > > While programming using Microblaze, I used a scanf function to read > data from an input port. But I get a compilation error saying that the > local memory is full. > > As an alterrnative to using printf, there is a xil_prinf function > available. Is tere a similar function available as an alternative to > scanf? Where will I get a list of all such Xilinx Specific Functions > for programming Microblaze? > > Thanks, > JohnArticle: 82768
Depending on what you are trying to accomplish, "Hardware in the Loop"
might be useful to you:
http://www.xilinx.com/products/software/sysgen/hw_loop.htm
http://www.xilinx.com/publications/xcellonline/xcell_47/xc_sysgen47.htm
Never used it myself, but thought I'd mention it anyhow...
Paul
kittyawake@gmail.com wrote:
>
> hi,
> I am trying to figure out how i can send data to the microblaze from
> outside the FPGA board.I thought if i can print something on the
> hyperterminal using printf,i should be able too read something from the
> hyperterminal using scanf?i wanted to try this out..but i am not able
> to compile my code.I have written a small code :
> ******************************************************************
> #include "xparameters.h"
> #include "xbasic_types.h"
>
> Xuint32 input;
>
> main()
> {
> xil_printf("input data /n/r");
> scanf("%d", input);
> xil_printf("inputted data was= %d/n/r",input);
> while(1);
> }
> *******************************************************************
> When i compile this code,i get the following error
> ****************************************************************
> mb-ld: region ilmb_cntlr is full (microblaze_0/code/executable.elf
> section .bss_stack)
> mb-ld: region ilmb_cntlr is full (microblaze_0/code/executable.elf
> section .bss_stack)
> make: *** [microblaze_0/code/executable.elf] Error 1
> Done
>
> I have 64KB of local memory.Any idea why am i getting this error?
> Does anyone know any better way of inputting data to the fpga?
> thanx.
Article: 82769EETimes salary review 2004 http://www.eet.com/showArticle.jhtml?articleID=30900112Article: 82770
Ben, I learn something new everyday. It turns out it is a DSL line (valid). OK. So now I fall back on my previous comment that I already made: I don't know. Is 3E faster or slower than 3? Just don't know. Will have to wait til tomorrow for the GPD person to post, as I am presuming he is not watching today. If folks are looking for blazing speed, then I suggest they look at Virtex 4. The Spartan team is all about value (lowest cost). If you have already targeted a Spartan 3, and are moving to 3E because of the IO vs CLB cost benefits, then I am sure the FAE's and tools are there to support you. AustinArticle: 82771
Dan Henry wrote: > kittyawake@gmail.com wrote: Hi Dan, Can you give us some more specific details how to do it (or anyone that knows ;-)? It would be a great help. Thanks, -HTArticle: 82772
Hello, I'm currently working on a project and I am at the stage where I'm ready to work on the PCB layout. For development I was using the Digilent Spartan IIE development board (http://www.nuhorizons.com/services/development/Xilinx/SpartanIIE/SpartanIIEBoard.html) and would use the six pin JTAG connector with the Nuhorizons JTAG cable (http://www.nuhorizons.com/products/digilent/jtag-cable.html) to program and test my design on the chip. This worked fine for testing purposes, but I then realized I'd have to store the program in a memory chip (using the SPROM connector). After going over the schematics and the datasheet for the development board, I am immensely confused as to how the programming file generated by the Xilinx ISE is used and programmed onto the FPGA. I would like to know exactly how this process works and what FPGA pins and external devices are needed for functionality. If anyone can help me out or point me to a place where I can figure it out on my own it'd be greatly appreciated. Thanks!Article: 82773
Can someone please tell me how to make a multi-page schematic in Altera's Quartus II software? I can't seem to find anything on this in the documentation. How is connectivity handled between the pages?... just by the net or node name? Thank you!! LenArticle: 82774
The Quartus schematic editor supports single page schematics. There is no limit to the size of a single page. Further abstraction, can be obtained by the use of hierarchy and symbols to connect across hierarchy boundaries. Hope this helps, Subroto Datta Altera Corp. "Len" <LeonardGabrielson@adelphia.net> wrote in message news:1113794842.776313.319400@o13g2000cwo.googlegroups.com... > Can someone please tell me how to make a multi-page schematic in > Altera's Quartus II software? I can't seem to find anything on this in > the documentation. > > How is connectivity handled between the pages?... just by the net or > node name? > > Thank you!! > Len >
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