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Hello,
I need an FPGA chip which fulfills the following constraints:
-- it has at least 64 IO lines;
-- it is not very fast, 133MHz is the highest possible internal frequency;
-- it contains about 500--1000 LE;
-- very important: it can directly communicate with 5V TTL devices,
this means that its inputs are 5V-tolerant, or better: its V_io = 5V;
-- the software can be easily obtained and is cheap or even free,
so perhaps only Altera and Xilinx should be considered as possible
vendors;
-- it is relatively cheap;
-- built-in configuration memory would be a great feature (because of
piracy).
What would you recommend me?
Best regards
Piotr Wyderski
Article: 83801Piotr Wyderski wrote: > Hello, > > I need an FPGA chip which fulfills the following constraints: > > -- it has at least 64 IO lines; > -- it is not very fast, 133MHz is the highest possible internal > frequency; > -- it contains about 500--1000 LE; > -- very important: it can directly communicate with 5V TTL devices, > this means that its inputs are 5V-tolerant, or better: its V_io = 5V; > -- the software can be easily obtained and is cheap or even free, > so perhaps only Altera and Xilinx should be considered as possible > vendors; > -- it is relatively cheap; > -- built-in configuration memory would be a great feature (because of > piracy). > > What would you recommend me? > > Best regards > Piotr Wyderski > 5V tolerant and cheap are mutual exclusive. You can use series resistors to make the input 5V tolerant or use some "Quick Switches" in series. Regards ThomasArticle: 83802
plz touch me more detail if u need the following ip. brahms_view@yahoo.it **************************************************************** 1>Ethernet MAC: 10M/100M/1G/10G 2>USB:1.1/2.0/OTG/PHY/stack 3>JPEG2000 4>PCI/PCI-X/PCI-AHB 5>SATA 6>SDMMC 7>1394 and PHY 8>silicon ocean:mp3 9>motion jpeg 10>ARC605 DSP 11>ARM PL110(LCD controller)/PL080(DMA controller)/PL176(Universal Memory Controller)/PL130 (smartcard) 12>8051/CAN/Z80/6811/AMBA/PCMCIA/T1E1/IEEE/1284/G711/G726/8086/80186/68000 13>MPEG4 14>802.11a/b/g 15>PCI-Express and PHY **************************************************************** note: 1> all core are silicon proven and verilog 2> they are not free.Article: 83803
> I want to start learning VHDL (or VERILOG) and FPGA programming. I have >ISE 6.1 and some FPGA board. Where is the best place to start? I am an >experienced C/C++ programmer. >What I need to develop a simple code in VHDL (or VERILOG)? "code" is an interesting word. Yes, VHDL and VERILOG are programming languages, but you are really trying to design hardware. If you don't know the basics of hardware, that's probably the place to start. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 83804
More precisely: CE in (Xilinx) FPGAs is always implemented by recirculating data back from Q to D. Not really any clock gating, for reasons that have been amply explained in this ng. Peter AlfkeArticle: 83805
Piotr, Very observant question. For atmospheric upsets, it is a relatively easy process to change all memory cells to SERT or DICE single upset hardened cells, with an increase in area as you go from 6T cells to 12T and 16T cells in the ASMBL columnar architecture which is actually trivial to do. But who will pay for this? Without the ASMBL architecture, it requires a complete relayout. If there are ways to design that result in the desired system FIT rate, one must comapre the costs of the extra logic with the costs of hardening the design (hard IP vs. soft IP). I believe the answer is a judicious combination of both: make the basic FIT rate better, and also provide some degree of hardening without incurring too much cost. Austin Piotr Wyderski wrote: > Austin Lesea wrote: > >> The ASIC DFF's, logic, etc. are also a fantastic neutron detector: >> the resulting hardness of the Virtex 4 is on par with, and better than >> a full custom 90nm ASIC doing the same task! > > > BTW, is it possible to order a special, rad-hard version of > a modern medium-complexity FPGA chip, say, comparable > with Cyclone 1C3? Would it mean a complete redesign of > the chip internals or is it relatively simple? > > Best regards > Piotr Wyderski >Article: 83806
"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> writes: > I need an FPGA chip which fulfills the following constraints: > -- it has at least 64 IO lines; > -- it is not very fast, 133MHz is the highest possible internal frequency; > -- it contains about 500--1000 LE; > -- very important: it can directly communicate with 5V TTL devices, > this means that its inputs are 5V-tolerant, or better: its V_io = 5V; > -- the software can be easily obtained and is cheap or even free, > so perhaps only Altera and Xilinx should be considered as possible > vendors; > -- it is relatively cheap; > -- built-in configuration memory would be a great feature (because of > piracy). Xilinx Spartan 2 for all but the last requirement. The last two requirements are mutually exclusive.Article: 83807
the news group need login in? Is the account of XILINX or webcase? thanks a lot!Article: 83808
In article <1115431720.831954.308900@f14g2000cwb.googlegroups.com>, alfke@sbcglobal.net says... > More precisely: > CE in (Xilinx) FPGAs is always implemented by recirculating data back > from Q to D. > Not really any clock gating, for reasons that have been amply explained > in this ng. Just to be clear, the flip-flops inside the Xilinx parts use the same MUX structure to feed data back, and the CE really toggles the SEL line on the MUX? Thanks. HW.Article: 83809
try to compute float point data in my program, but i can't add the libm.a, who can help me?Article: 83810
"Pete" <padudle@sandia.gov> wrote in message news:4278ffe3$1@news3.es.net... > Hello > > I noticed the University of Queensland distribution of uClinux for the > Xilinx Microblaze soft processor core. > > Does anyone know of an open source embedded linux distribution for the PPC > 405 cores in V2Pro and V4? > > Thank you, > > Pete > > From a few posts in the microblaze uclinux mail list __________________________________________________________________________________ "We are working with the PPC on virtex2p. You do not need Monta Vista Linux. All you need is denx eldk: http://www.denx.de/twiki/bin/view/DULG/ELDK And the penguin ppc linux distribution: http://www.penguinppc.org/kernel/#developers (we are using the 2.4 Kernel) To get started: http://www.klingauf.de/v2p/index.phtml might be helpful. The PPC (ML300 board) is support in the standard kernel.org kernel since v2.6.10. Or http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html I've already used these helpful references to get a Linux kernel running on the PowerPC405 on the Digilent XUP-V2Pro board. I'm new to ucLinux but it doesn't appear to be much more complicated than the ucLinux steps. X running on the ML300 w/PPC? Yes - it was quite a painful build process, but I got it running. Obviously MontaVista has, too."____________________________________________________________________________________________AlexArticle: 83811
I had a similar problem. When I switched to an external power supply instead of using a PC PS2 port, the problem went away. Marc. "Sean Durkin" <smd@despammed.com> wrote in message news:427b642f@news.ginko.net... > Hi folks, > > this is starting to drive me nuts: > > I use a Xilinx Parallel Cable IV to program some big FPGAs (big as in > V2P70 and the like). Now Impact and Chipscope always open this cable in > "Compatibility Mode", meaning it is used as a Parallel Cable III and > takes FOREVER to download a bitstream. No matter what I do, no matter > what settings for the parallel port I use, it keeps getting detected as > a Parallel Cable III. This is a problem we've been having constantly for > years now... on some machines it works fine, on some it doesn't, and on > some others it sometimes works but sometimes doesn't. > > The only certain thing is that it never works on the machine I am > currently working on when I have a lot of testing to do and big bitfiles > to download. > > Now, I've googled my eyes out for this, read all the answer records, > tried everything mentioned there and everything I could think of: > > - I tried all possible BIOS-settings for the parallel port: ECP, EPP, > bidirectional, different DMA-channels, different IRQs; you name it, I've > tried it > > - I tried uninstalling the cable drivers from Xilinx, reinstalling new > ones. I tried uninstalling the entire ISE, making sure there's nothing > left in the Windows-Drivers-Dir, reinstalling ISE. I've tried every > ISE-version from 4.2 to 7.1 without success. I've tried doing a fresh > install on a freshly installed Windows, nothing. > > Now we bought one of the new platform cables for USB, works much better, > but those are expensive and we have probably half a dozen "Parallel > Cable IVs" in use. > > Any pointers, any hints? > > cu, > SeanArticle: 83812
Brijesh wrote: > > I know that we can vary the drive strength of the Virtex outputs and > control the rise time. This just for my understanding of things. > > Using a capacitor to ground to slow the rise time feels like a very > wrong thing to do. But I am not able to convince others why its a bad > practise? > > It's bad in practice -- however to slow the rise & fall time of an edge one can accomplish this a number of ways -- I assume you need to slow the edge down (irrespective of the signal frequency 100Khz vs 100Mhz) is that you are noticing some Signal Integrity issues such as reflections or crosstalk. If so the real answer would be to terminate your transmission properly to eliminate any SI issues with your fast driver. See Howard Johnson's (Black Magic) book on SI or visit IDT, TI or other IC manufacturers website and look for the app notes on SI, ground bounce, crosstalk etc... they have some nice primers on SI. Too slow edges down - use source series terminators, an RC filter at the source, a source series resistor with a PI filter, ferrite bead, adjust the slew of the driver in the FPGA, choose a slower IO standard in the FPGA, so on and so forth ... Good luck .... JoeGArticle: 83813
Well, still need help if anyone has advice. I may be able to get things going if I know what to enter for the "Simulation Libraries Path" under the "Project Options" dialog. Assuming I have BFM stuff installed and ready to go, I found the bfmsim folder generated for my IP with the XPS project that is supposed to allow me to test it out. Now, where should these paths (EDK library and Xilinx library) lead? Thanks... JoeyArticle: 83814
johnp wrote: > I hope one of the Xilinx gurus can help me out here... > > I've got a design that uses multiple V2Pro parts receiving > a common high speed clock. The clock is well laid out to > equalize trace lengths and is differential. I also have > the ability to cleanly start/stop the clock. > > I'd like to use the CLKIN_DIVIDE_BY_2 option on the DCMs in > the V2Pro parts to cut the rate down, but I'd like to make sure > that the CLK0 outputs of the DCMs in the different parts come > up in phase. > > For this design, I'd hook the CLK0 output to the DCM feedback > pin in each FPGA. > > If I stop the input clock, reset the DCMs in each part, then > start the input clock again... > a) Will the input dividers of the DCMs be in phase? > b) After the DCMs achieve lock, will the CLK0 outputs of > the DCMs in the different parts also be in phase? Howdy John, I know that the phase is not deterministic for the CLKDV output, and I'd strongly suspect the same for the input divider. The only (not so good) way to get what you want is to have some monitoring logic which resets the DCM until it has the correct phase - which of course, means it needs to somehow have visability into what the correct phase is supposed to be. I believe the only straight forward way of doing what you want is to do the divide before the fanout. The next, not nearly so good way, is to drive the global clocks of all the devices with the 2x clock, but use a board wide clock enable on all your logic. Just thinking out loud here. Hmmm... anyone ever used a BUFG enable/mux as a clock enable? Good luck, MarcArticle: 83815
I am not too swift with the newgroup stuff in general, so I always access through Google. Go to google and click the 'groups' link. You can find this group easily that way and google has options for joining. I know there are fancier 'old school' ways to go about it, but this is what I do--the group doesn't have anything in particular to do with Xilinx or webcases. Hopefully not too many folks will snicker at my use of google for news groups! JoeyArticle: 83816
You got it ! PeterArticle: 83817
On Fri, 6 May 2005 19:42:11 -0700, jack <mlpei@emails.bjut.edu.cn> wrote: >the news group need login in? Is the account of XILINX or webcase? thanks a lot! You can access the group (as you already have) via the xilinx gateway, or you can use another gate way, such as the Google groups one that many people use, or you can have direct access through your ISP, or through a usenet news service. Via Xilinx and Google is free, via your ISP may be no additional charge over what you already pay, and usenet services cost a few $ per month. It is all described here: http://www.fpga-faq.org/FAQ_Posting.htm Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 83818
"jack" <mlpei@emails.bjut.edu.cn> wrote in message news:ee8e144.-1@webx.sUN8CHnE... > try to compute float point data in my program, but i can't add the libm.a, > who can help me? Try adding -lm at the end of your linker statement. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 83819
Duane Clark ha scritto: >> Hi and thanks for the new files, >> worked on it again yesterday and now it still doesn't run properly but >> at least now when I write a 16 bit value the system stalls (before it >> couldn't write anything from 32 bit to 8 bit: I always got back 0), so >> it's clear that something as changed (although I don't know if for the >> better :) ). I'll see if finally I could make it work! >> > > Well, I'll admit to only using with 32 bit values. There may very well > be problems with other data widths, though I expect a fix would not be > terribly difficult. That is definitely something that would be a lot > easier to check in simulation rather than hardware. Yep, in fact it would be great just to make it work with 32 bit values for now, so we could have another (big) pool of memory to work with. And after, if time permits, we could very well try to fix it also for other data widths with test & simulation in the university lab. I'll post the MHS of the test-design I made which gives zero with 32 bits value and stalls with 16 bit values. The only modifications I made to the core in this last test are the elimination of the ext in/out ports from plb_dimm.vhd (declaring them as signal and tying the in to 0), and after double checking the connections you made within you MHS and system_top, I just replicated them with the XPS flow. To check if it was a problem with the flow, I also tried with the projnav flow of course, but the only difference regarding the dimm core between the autogenerated system_stub and your system_top is the presence of an addictional buffer on the DM signals (which aren't on your system_top) and on the clocks signal different from DDR_CLK0 (buffers are placed as a standard on all external in/out by EDK when you export the project to projnav). I'm trying to see if it can work with the XPS flow because it would be interesting for other people in the lab to be able to use the core just importing it in EDK... You can notice psin, psindec and DDR_RST signal tied to zero directly in the MHS, and I veryfied that this work since exporting the MHS to projnav gives the correct translation in the system_stub.vhd. Any suggestion and ideas? Thank you very much!!! PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = IN PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_DQ_pin = fpga_0_SDRAM_64Mx16_SDRAM_DQ, VEC = [0:31], DIR = INOUT PORT fpga_0_SDRAM_64Mx16_SDRAM_BankAddr_pin = fpga_0_SDRAM_64Mx16_SDRAM_BankAddr, VEC = [0:1], DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_Addr_pin = fpga_0_SDRAM_64Mx16_SDRAM_Addr, VEC = [0:11], DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_DQM_pin = fpga_0_SDRAM_64Mx16_SDRAM_DQM, VEC = [0:3], DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_CASn_pin = fpga_0_SDRAM_64Mx16_SDRAM_CASn, DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_RASn_pin = fpga_0_SDRAM_64Mx16_SDRAM_RASn, DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_Clk_pin = fpga_0_SDRAM_64Mx16_SDRAM_Clk, DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_WEn_pin = fpga_0_SDRAM_64Mx16_SDRAM_WEn, DIR = OUT PORT fpga_0_SDRAM_64Mx16_SDRAM_CSn_pin = fpga_0_SDRAM_64Mx16_SDRAM_CSn, DIR = OUT PORT fpga_0_SDRAM_64Mx16_emc_disable_flash_pin = net_vcc, DIR = OUTPUT PORT fpga_0_SDRAM_64Mx16_emc_disable_sram_pin = net_vcc, DIR = OUTPUT PORT fpga_0_SDRAM_64Mx16_emc_disable_buffer_pin = net_vcc, DIR = OUTPUT PORT fpga_0_SDRAM_64Mx16_emc_disable_sysace_pin = net_vcc, DIR = OUT PORT sys_clk_pin = dcm_clk_s, DIR = IN PORT sys_rst_pin = sys_rst_s, DIR = IN PORT DDR_AD = plb_dimm_0_DDR_Addr, DIR = OUT, EDGE = RISING, VEC = [0:12] PORT DDR_BA = plb_dimm_0_DDR_BankAddr, DIR = OUT, EDGE = RISING, VEC = [0:1] PORT DDR_CASB = plb_dimm_0_DDR_CASn, EDGE = RISING, DIR = OUT PORT DDR_CKE = plb_dimm_0_DDR_CKE, DIR = OUT, EDGE = RISING, VEC = [0:1] PORT DDR_CSB = plb_dimm_0_DDR_CSn, DIR = OUT, EDGE = RISING, VEC = [0:1] PORT DDR_DM = plb_dimm_0_DDR_DM, DIR = OUT, EDGE = RISING, VEC = [0:7] PORT DDR_DQ = plb_dimm_0_DDR_DQ, DIR = INOUT, EDGE = RISING, VEC = [0:63] PORT DDR_DQS = plb_dimm_0_DDR_DQS, DIR = INOUT, EDGE = RISING, VEC = [0:7] PORT DDR_RASB = plb_dimm_0_DDR_RASn, EDGE = RISING, DIR = OUT PORT DDR_WEB = plb_dimm_0_DDR_WEn, EDGE = RISING, DIR = OUT PORT DDR_CLKB_0 = plb_dimm_0_DDR_Clkn_0, EDGE = RISING, DIR = OUT PORT DDR_CLKB_1 = plb_dimm_0_DDR_Clkn_1, EDGE = RISING, DIR = OUT PORT DDR_CLK_0 = plb_dimm_0_DDR_Clk_0, EDGE = RISING, DIR = INOUT PORT DDR_CLK_1 = plb_dimm_0_DDR_Clk_1, EDGE = RISING, DIR = OUT BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE DPLB = plb BUS_INTERFACE IPLB = plb BUS_INTERFACE JTAGPPC = jtagppc_0_0 PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT CPMC405CLOCK = cpmc405clock END BEGIN ppc405 PARAMETER INSTANCE = ppc405_1 PARAMETER HW_VER = 2.00.c BUS_INTERFACE JTAGPPC = jtagppc_0_1 END BEGIN jtagppc_cntlr PARAMETER INSTANCE = jtagppc_0 PARAMETER HW_VER = 2.00.a BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 BUS_INTERFACE JTAGPPC1 = jtagppc_0_1 END BEGIN proc_sys_reset PARAMETER INSTANCE = reset_block PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Ext_Reset_In = sys_rst_s PORT Slowest_sync_clk = sys_clk_s PORT Chip_Reset_Req = C405RSTCHIPRESETREQ PORT Core_Reset_Req = C405RSTCORERESETREQ PORT System_Reset_Req = C405RSTSYSRESETREQ PORT Rstc405resetchip = RSTC405RESETCHIP PORT Rstc405resetcore = RSTC405RESETCORE PORT Rstc405resetsys = RSTC405RESETSYS PORT Bus_Struct_Reset = sys_bus_reset PORT Dcm_locked = dcm_0_lock END BEGIN plb_v34 PARAMETER INSTANCE = plb PARAMETER HW_VER = 1.02.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT PLB_Clk = sys_clk_s END BEGIN opb_v20 PARAMETER INSTANCE = opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT OPB_Clk = sys_clk_s END BEGIN plb2opb_bridge PARAMETER INSTANCE = plb2opb PARAMETER HW_VER = 1.01.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_NUM_ADDR_RNG = 1 PARAMETER C_RNG0_BASEADDR = 0x81000000 PARAMETER C_RNG0_HIGHADDR = 0x8100ffff BUS_INTERFACE SPLB = plb BUS_INTERFACE MOPB = opb PORT PLB_Clk = sys_clk_s PORT OPB_Clk = sys_clk_s END BEGIN opb_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 19200 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 100000000 PARAMETER C_BASEADDR = 0x81000000 PARAMETER C_HIGHADDR = 0x8100ffff BUS_INTERFACE SOPB = opb PORT OPB_Clk = sys_clk_s PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END BEGIN plb_sdram PARAMETER INSTANCE = SDRAM_64Mx16 PARAMETER HW_VER = 1.00.e PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1 PARAMETER C_PLB_CLK_PERIOD_PS = 10000 PARAMETER C_SDRAM_TMRD = 2 PARAMETER C_SDRAM_TCCD = 1 PARAMETER C_SDRAM_TRAS = 50000 PARAMETER C_SDRAM_TRC = 100000 PARAMETER C_SDRAM_TRFC = 100000 PARAMETER C_SDRAM_TRCD = 20000 PARAMETER C_SDRAM_TRRD = 20000 PARAMETER C_SDRAM_TRP = 20000 PARAMETER C_SDRAM_TREF = 64 PARAMETER C_SDRAM_CAS_LAT = 2 PARAMETER C_SDRAM_COL_AWIDTH = 9 PARAMETER C_SDRAM_BANK_AWIDTH = 2 PARAMETER C_SDRAM_AWIDTH = 12 PARAMETER C_SDRAM_DWIDTH = 32 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x01ffffff BUS_INTERFACE SPLB = plb PORT PLB_Clk = sys_clk_s PORT SDRAM_CLK_in = sys_clk_s PORT SDRAM_DQ = fpga_0_SDRAM_64Mx16_SDRAM_DQ PORT SDRAM_Addr = fpga_0_SDRAM_64Mx16_SDRAM_Addr PORT SDRAM_DQM = fpga_0_SDRAM_64Mx16_SDRAM_DQM PORT SDRAM_WEn = fpga_0_SDRAM_64Mx16_SDRAM_WEn PORT SDRAM_CSn = fpga_0_SDRAM_64Mx16_SDRAM_CSn PORT SDRAM_CASn = fpga_0_SDRAM_64Mx16_SDRAM_CASn PORT SDRAM_RASn = fpga_0_SDRAM_64Mx16_SDRAM_RASn PORT SDRAM_Clk = fpga_0_SDRAM_64Mx16_SDRAM_Clk PORT SDRAM_BankAddr = fpga_0_SDRAM_64Mx16_SDRAM_BankAddr END BEGIN plb_bram_if_cntlr PARAMETER INSTANCE = plb_bram_if_cntlr_1 PARAMETER HW_VER = 1.00.b PARAMETER c_plb_clk_period_ps = 10000 PARAMETER c_baseaddr = 0xffff0000 PARAMETER c_highaddr = 0xffffffff BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port BUS_INTERFACE SPLB = plb PORT PLB_Clk = sys_clk_s END BEGIN bram_block PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port END BEGIN plb_dimm PARAMETER INSTANCE = plb_dimm_0 PARAMETER HW_VER = 1.11.a PARAMETER C_MEM0_BASEADDR = 0x40000000 PARAMETER C_MEM0_HIGHADDR = 0x47ffffff PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 0 PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_NUM_CLK_PAIRS = 2 PARAMETER C_FAMILY = virtex2 PARAMETER C_INCLUDE_ECC_SUPPORT = 0 PARAMETER C_DDR_TMRD = 2 PARAMETER C_DDR_TWR = 15000 PARAMETER C_DDR_TWTR = 1 PARAMETER C_DDR_TRAS = 40000 PARAMETER C_DDR_TRC = 65000 PARAMETER C_DDR_TRFC = 75000 PARAMETER C_DDR_TRCD = 20000 PARAMETER C_DDR_TRRD = 15000 PARAMETER C_DDR_TREFC = 70000000 PARAMETER C_DDR_TREFI = 7800000 PARAMETER C_DDR_TRP = 20000 PARAMETER C_DDR_CAS_LAT = 3 PARAMETER C_DDR_DWIDTH = 64 PARAMETER C_DDR_AWIDTH = 12 PARAMETER C_DDR_COL_AWIDTH = 9 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_PLB_CLK_PERIOD_PS = 10000 BUS_INTERFACE SPLB = plb PORT DDR_Rst = 0b0 PORT Clk90_in = plb_dimm_0_Clk90_in PORT DDR_Addr = plb_dimm_0_DDR_Addr PORT DDR_BankAddr = plb_dimm_0_DDR_BankAddr PORT DDR_CASn = plb_dimm_0_DDR_CASn PORT DDR_CKE = plb_dimm_0_DDR_CKE PORT DDR_Clk90_in = plb_dimm_0_DDR_Clk90_in PORT DDR_Clkn_0 = plb_dimm_0_DDR_Clkn_0 PORT DDR_Clkn_1 = plb_dimm_0_DDR_Clkn_1 PORT DDR_Clk_0 = plb_dimm_0_DDR_Clk_0 PORT DDR_Clk_1 = plb_dimm_0_DDR_Clk_1 PORT DDR_Clk_fb = plb_dimm_0_DDR_Clk_fb PORT DDR_CSn = plb_dimm_0_DDR_CSn PORT DDR_DCM_Locked = plb_dimm_0_DDR_DCM_Locked PORT DDR_DCM_Reset = plb_dimm_0_DDR_DCM_Reset PORT DDR_DM = plb_dimm_0_DDR_DM PORT DDR_DQ = plb_dimm_0_DDR_DQ PORT DDR_DQS = plb_dimm_0_DDR_DQS PORT DDR_RASn = plb_dimm_0_DDR_RASn PORT DDR_WEn = plb_dimm_0_DDR_WEn PORT PLB_Clk = sys_clk_s PORT PLB_DCM_Locked = dcm_0_lock END BEGIN ddr_clocks PARAMETER INSTANCE = ddr_clocks_0 PARAMETER HW_VER = 1.00.a PORT ref_clk = dcm_clk_s PORT ddr_dcm_rst = plb_dimm_0_DDR_DCM_Reset PORT sys_rst_n = net_vcc PORT plb_opb_clk = sys_clk_s PORT cpmc405clock = cpmc405clock PORT clk90_in = plb_dimm_0_Clk90_in PORT ddr_clk_fb = plb_dimm_0_DDR_Clk_fb PORT ddr_clk90_in = plb_dimm_0_DDR_Clk90_in PORT ddr_clk_locked = plb_dimm_0_DDR_DCM_Locked PORT plb_opb_locked = dcm_0_lock PORT psen = 0b0 PORT psincdec = 0b0 ENDArticle: 83820
Bob Perlman schrieb: > I avoid capacitors on digital lines because [...] (3) the capacitor is often used to > cover up an underlying design problem, <rant> You mean like in this design: http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html Were they put in capacitors behind the drivers to cover up a race condition in the programmer software? </rant> Kolja SulimmaArticle: 83821
Why not use Linux for the PPC.. its a standard port :-) Simon "Alex Gibson" <news@alxx.net> wrote in message news:3e32ceFvc1cU1@individual.net... > > "Pete" <padudle@sandia.gov> wrote in message news:4278ffe3$1@news3.es.net... > > Hello > > > > I noticed the University of Queensland distribution of uClinux for the > > Xilinx Microblaze soft processor core. > > > > Does anyone know of an open source embedded linux distribution for the PPC > > 405 cores in V2Pro and V4? > > > > Thank you, > > > > Pete > > > > > > From a few posts in the microblaze uclinux mail list > ____________________________________________________________________________ ______ > "We are working with the PPC on virtex2p. You do not need Monta Vista Linux. > All you need is denx eldk: http://www.denx.de/twiki/bin/view/DULG/ELDK > And the penguin ppc linux distribution: > http://www.penguinppc.org/kernel/#developers > (we are using the 2.4 Kernel) > To get started: http://www.klingauf.de/v2p/index.phtml might be helpful. The > PPC (ML300 board) is support in the standard kernel.org kernel since > v2.6.10. Or > http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html > > I've already used these helpful references to get a Linux kernel running on > the PowerPC405 on the Digilent XUP-V2Pro board. I'm new to ucLinux but it > doesn't appear to be much more complicated than the ucLinux steps. > X running on the ML300 w/PPC? Yes - it was quite a painful build > process, but I got it running. Obviously MontaVista has, > too."_______________________________________________________________________ _____________________Alex > >Article: 83822
Thomas Rudloff wrote:
> 5V tolerant and cheap are mutual exclusive.
Well, it is undoubtedly true if we consider all modern devices,
but here the chip can be a little outdated -- it will work as an
IDE interface (UltraDMA 133, two channels) and perform some
auxilary tasks. The power consumption is not very important.
Does it help?
> You can use series resistors to make the input 5V tolerant
Not at this speed, I think. A column of some LVX translators
(74LVX245, for example) would be much better, but the board
sould be as small as possible, so I don't want this approach.
> use some "Quick Switches" in series.
Hm, what are they?
Best regards
Piotr Wyderski
Article: 83823Thanks. Where can I get a good and free simulator one? I know that good ones aren't free but please advise one that is free and better than others! Best regards "Mike Treseler" <mike_treseler@comcast.net> wrote in message news:3e27pdFs9bgU1@individual.net... > ma wrote: >> What I need to develop a simple code in VHDL (or VERILOG)? > A VHDL (or VERILOG) simulator. > >> How should I compile route and place and.. ? > Don't worry about that until your simulation is OK. > >> How can I see the output? > On the simulation waveforms. > > -- Mike TreselerArticle: 83824
Piotr Wyderski wrote: > Thomas Rudloff wrote: > >> 5V tolerant and cheap are mutual exclusive. > > > Well, it is undoubtedly true if we consider all modern devices, > but here the chip can be a little outdated -- it will work as an > IDE interface (UltraDMA 133, two channels) and perform some > auxilary tasks. The power consumption is not very important. > Does it help? > >> You can use series resistors to make the input 5V tolerant > > > Not at this speed, I think. A column of some LVX translators > (74LVX245, for example) would be much better, but the board > sould be as small as possible, so I don't want this approach. > >> use some "Quick Switches" in series. > > > Hm, what are they? > > Best regards > Piotr Wyderski > Have a look at http://www.idt.com/?id=34 the "Quick Switches" were invented by "Quality Semiconductor". There should be an App Note how to use them as bus translator. Maybe a CPLD instead of an fpga may be a better choice in your case. Regards, Thomas
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