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"cas7406@yahoo.com" <cas7406@yahoo.com> wrote in message news:<1114271914.892049.115680@z14g2000cwz.googlegroups.com>... > Andre, > > I think what you are missing are the constraints. Have set your Tco, > fmax, Setup and Pin Assignment constraints? Use either the preference > file (.prf) or the Pre-Map Preference Editor to set your constraints. > Also TN1050 can help you out. > > rgds, > > cristian Hi Cristian, yes I have set the constraints for all the other signals which do not come out the DATAPATH template. In the Timing Analysis these signals (for example the address bus for DDR) do have the same tCO. I have constrained DQ and DQS in the PREFERENCE EDITOR under "In/Out Clock" whereas the other signals are constrained under "Cell Attributes". But the constraints for DQ and DQS do have no effect on the tCO. Rgds AndréArticle: 83151
Hi Andrew, > If you know of any common or good ways to model asynchronous systems in > Simulink, please let me know. We'd love to infer that from the Simulink > model during Synplify DSP synthesis. Xilinx SysGen seems to support it using two subsystems as you suggest as a solution. http://www.xilinx.com/products/software/sysgen/app_docs/user_guide_Chapter_10_Section_3_Subsection_85.htm (or http://tinyurl.com/drfds) Cheers, DaveArticle: 83152
Hi Jason,
You can also use Precision (2005 and later) to infer synchronous memory. The
code below is what I used on my core although I am not sure this is the
approved template.
-- Actel Synchronous Memory
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity ssram is
port(
clk : in std_logic;
din128 : in std_logic_vector (127 downto 0);
addr : in std_logic_vector (3 downto 0);
we : in std_logic;
dout128 : out std_logic_vector (127 downto 0)
);
end ssram ;
architecture rtl of ssram is
type mem_type is array (15 downto 0) of std_logic_vector(127 downto 0) ;
signal mem : mem_type;
begin
singleport : process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
mem(conv_integer(addr)) <= din128;
else
dout128 <= mem(conv_integer(addr));
end if ;
end if;
end process singleport;
end architecture rtl;
Regards,
Hans.
www.ht-lab.com
"Jason Zheng" <xin.zheng@jpl.nasa.gov> wrote in message
news:d43ojt$on9$1@nntp1.jpl.nasa.gov...
> Is there an easy to use Actel's internal ram without going to coregen? I'm
> concerned about compatibility issues if I have to use coregen.
>
> thanks in advance.
Article: 83153According to what the manuals say, you need a debugger to do this. I am using the XPS from Xilinx for the develpoment purposes. In this tool, there is the XMD and a Program Debugger with which you can download the program !! Just connect -> download-> run. "Peter" <pbs@mortician.dk> wrote in message news:ee8dc08.-1@webx.sUN8CHnE... > Hi, > > I'm using the ML 401 development board configured with the "reference design" provided by Xilinx. I need to download a rather large c++ program but unfortunately it cannot fit into the bram of the design. I know that I should place the program data in the 64 mb external memory. Is there an "easy" way to do this? > > thanksArticle: 83154
I'm trying to use a montavista kernel on a ml310 but when I run it, I always have the same error even if I follow the xilinx instructions. In fact when booting h*the kernel the ml310 freeze and the opb led turns to red. I can't find where is the problem. can you help me? thanks a lotArticle: 83155
Duane Clark ha scritto: > Oh, and while at it, I included a simple testbench in the same > directory. The files bd_test.vhd and bd_test_siml.vhd are separate tests > that do slightly different things. You compile one or the other into the > testbench. The top level testbench file is bd_top.vhd. Hi Duane, thank you again!!! If there is anything I could do for you... These files are really helpful! Tomorrow I'll be back in the lab (today it's holyday here :) ) and I'll test everything, so I will be able to tell you if I made him. Meanwhile, thank you very much!Article: 83156
XPower says I need a completely mapped NCD file to get started. I dont have anything from the FPGA designer that I can use yet. Can I do anything without requiring the NCD file? JasonArticle: 83157
Unfortunately, you can't use webpack with this board, so you have to buy an ISE license, right? (I am a student also, but having to get an ISE license is kind of a damper). -ArlenArticle: 83158
true Uzytkownik "tom" <tom1@launchbird.com> napisal w wiadomosci news:1113942836.716708.188290@f14g2000cwb.googlegroups.com... > VhdlArch-0.1.1 is now available. Still only handles syntax checking, > but includes several bug fixes (thanks for the feedback!). > > http://www.confluent.org/wiki/doku.php?id=vhdlarch > > -Tom >Article: 83159
rgebru wrote: > Hi Gabor, > > > Thanks for the reply. I'm actually having problems with the > programming part. Especially displaying the 10bit 2's complement > temperature readings on my 4 seven segment display. I'm trying to > convert them into binary but for some reason it's not working very > well. Do you have a suggestion of how I should read them in? I'm not > using the negative temperature readings and I'm only interested in > temperatures up to 90deg so I can displaly the actual temp on two > displays and the temperature you want to set on the other 2 displays. > thanks so much for your suggestions! > > Ruth First of all, you want to convert from binary to BCD (2's complement is straight binary when the numbers are positive). Then from BCD to seven-segment. There are several ways to convert binary to BCD. If you had to do it really fast (1 clock cycle) you could use the brute force method using block RAM (1024 x 13) as a look-up table. Since your data is coming in serially at a relatively low clock rate, I assume you don't need to do this. If you have an internal clock running at least 1024 times your sampling rate, the simplest serial method is to load a binary counter with the binary value, then count it down to zero while counting up on a BCD counter (3 divide-by-ten counters in a carry chain). The conversion time would depend on the temperature but the algorithm is simple. An intermediate method takes fewer clock cycles but is a little more tricky. It involves shifting the binary input one bit at a time into a shift register and then performing a "decimal adjust after add" which involves adding a 6 to any digits that either carry out (in the shift register this means 1 in the low bit of the next digit up) or end up with a value greater than 9 after the shift. If you don't pipeline the two operations you'd use 2 clock cycles per input bit for this method or 20 cycles in your case. The shifter / adder would need to be 13 bits long to hold the BCD number. Other methods include serial subtraction of decimal powers (i.e. subtract 1,000 and if there's no borrow, add one to the most significant digit, after a borrow add back 1,000 and then do the same with 100 and the next digit down) or a series of division / remainder operations (i.e. divide by 1,000 and put the result in the high digit, divide the remainder by 100 and put the result in the next digit, divide the second remainder by 10...). Finally converting BCD to 7-segment is a simple look-up table. There should be lots of examples of this around.Article: 83160
Dear Jonathan, thank you very much for your input, it helps me a lot in understanding the problem. I will dive deeper into the algorthims now. As for the rough hardware estimates, I understood you that if we want to do object detection with resulting variable-sized data structures, we should go for an FPGA with embedded CPU. I will probably come back to you later, when I have a deeper understanding of the problem and possible solutions. Thank you very much so far, Christian -- Jonathan Bromley wrote: > On Mon, 18 Apr 2005 11:47:37 +0200, "C. Peter" > <die_les_ich_nicht@gmx.net> wrote: > > > >>- there are 4 ccd cameras with 1024 pixel which are read out each by 1 >>FPGA (Spartan) > > > Line scan cameras, then. OK. As you say below, they usually > produce data slightly faster than typical video-compatible > area cameras. > > >>- those FPGAs behind the CCD cameras send out byte arrays. We aim at >>producing about 60 MByte/sec >> >>- our part now is to read those byte arrays (all 4) and do edge detection >>on it. This has to be done in real-time. > > > If the edge detection is one-dimensional, in the direction of the line > scan, this is very easy indeed and would fit in even the cheapest > modern FPGA. However, if your edge detection needs 2-D processing > as I guess it does, then you need to store recent video lines and > you will certainly need lots of bandwidth to internal memory because > you need access to more than one line to process each pixel. > > >>- if this is too heavy we could imagine doing the edge detection separate >>for each of the 4 data streams (still in real-time), although this would >>result in significantly more work to be done in consecutive steps. > > > It depends on the edge detection algorithm. Something simple like > a 4-point Sobel would cause no trouble at all. Edge detectors with > more complex branching algorithms (Canny?) would be much trickier. > > >>- The parameters of the edge detectors must be configurable in near real-time. > > > In itself this is unlikely to be a problem. You have several > dead pixel times at the end of each line; during this time you > can copy parameters, from a RAM where they've been written by > software, into the registers where they will be used. > > >>- The output of our FPGA(s) is a figure for number and size of identified >>objects of interest. > > > So presumably you are not only edge detecting, but also keeping > track of those edges and inferring object outlines from them? > That kind of task typically creates variable-sized data > structures, which don't map on to FPGA implementation very > well unless there are other application-specific constraints > that you can exploit in the algorithm design. Depending on > the exact nature of the object-finding, this may be good work > for a small embedded CPU (Microblaze etc) in the FPGA. > > >>Well now, do you still think it is feasable? Would a Spartan 3 do it or is >>a Virtex needed (one with DSP slices)? > > > You'll need to be much more specific about the edge detection and > discrimination algorithms. Things like how many multipliers > (if any) are needed by the area convolution operations. > > We, and many other organisations, would be in a good position to > help with specifics of implementation - but there's no way you > can start to estimate required hardware resources until you > have a clear description of the required algorithms. Only then > can you begin to bash the algorithms into an FPGA-friendly form > and start allocating hardware to them.Article: 83161
Hi all, we face a strange problem with our synchronized reset signal coming from the ISA-Bus. It seems that some part of the logic is not functioning correctly after reset-release. However I'am not shure. I would like to implement a digital debounce logic for this reset signal, and for this reason I would like to have part of the logic on reset-ed ONCE after power-up and configuration. Is there a way to connect to this internal power-up reset signal, or shall I leave the reset connection of such a debounce block always negated by connecting it to permanent '0', for a active '1' reset? Best Regards Markus ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups ----= East and West-Coast Server Farms - Total Privacy via Encryption =----Article: 83162
Does the plot show a functional or a timing simulation ? Rgds AndréArticle: 83163
Hi, Can any1 tell me what exactly is microblaze or in particulat what do we mean by the term "soft processor" ?? If i have to work on some thing or implement some thing on say virtex 2 board , do i have to use microblaze every time or can i just skip micro blaze part and do some simple implementations without it ?? Hope any1 can give me a simple answer to this .... thanksArticle: 83164
mb wrote: > Hi, > > Can any1 tell me what exactly is microblaze or in particulat what do > we mean by the term "soft processor" ?? A processor implemented in a FPGA by using the programmable logic inside the fpga. > If i have to work on some thing or implement some thing on say virtex > 2 board , do i have to use microblaze every time no or can i just skip > micro blaze part and do some simple implementations without it ?? you can skip > Hope any1 can give me a simple answer to this .... sure > thanks no problem SylvainArticle: 83165
Simon wrote: > If you do manage it, let me know! At *last* a development board with a > DIMM socket on it. Oh frabjous day. Callooh! Callay! He chortled in his > joy :-)) > > Why it's such a rare item is beyond me - it takes 123 signals to put a > generic 184-pin DIMM socket on-board... With the BGA parts having > upwards of 300 (566 in this case) signals available, and RAM being so > ridiculously cheap (in DIMMs!), and with the EDK becoming more popular > you'd have thought a DIMM socket would be commonplace... Horses for > courses I suppose :-( There are other Virtex-II Pro boards that have been available for sometime with a DDR-DIMM on it, including the ML310 from Xilinx which uses the same FPGA (XC2VP30) and has appeared in a number of posts here in comp.arch.fpga http://www.xilinx.com/ml310 EdArticle: 83166
ALuPin wrote: > Does the plot show a functional or a timing simulation ? It's a post-map simulation But I don't think the functional error of the design is a problem in the implemented version (but anyway I would like it to simulate perfectly, for future faster implementation (only running 50/7 MHz on real design)). Thanks for helping Preben HolmArticle: 83167
Preben Holm wrote: > Hi, > > > I wonder why this results in undefined values for some time: > > ---------------------------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > -- Uncomment the following lines to use the declarations that are > -- provided for instantiating Xilinx primitive components. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity trigger_level is > Port ( clk : in std_logic; > prescale : in std_logic; > din : in std_logic_vector(7 downto 0); > level : in std_logic_vector(7 downto 0); > rf : in std_logic; > hold : in std_logic; > trig : out std_logic); > end trigger_level; > > architecture Behavioral of trigger_level is > type samples_buffer is array(9 downto 0) of > std_logic_vector(7 downto 0); > > signal samples : samples_buffer; > begin > > process(clk) > begin > if rising_edge(clk) and prescale = '1' and hold = '0' then > -- no reset circuit (not needed) for reducing the number of > slices to 1 instead of 5 > for i in 9 downto 1 loop > samples(i) <= samples(i-1); > end loop; > samples(0) <= din; > end if; > end process; > > > process(clk) > begin > if rising_edge(clk) then > if (rf = '1') then --- falling edge > if (samples(0) < level and samples(9) > level) then > trig <= '1'; > else > trig <= '0'; > end if; > elsif (rf = '0') then --- rising edge > if (samples(0) > level and samples(9) < level) then > trig <= '1'; > else > trig <= '0'; > end if; > else > trig <= '0'; > end if; > end if; > end process; > > end Behavioral; > ---------------------------------- > > > The design should be a trigger for an oscilloscope, and I think I have > an error in my design here! The trouble is that I get triggers where I > shouldn't! (or my presampler probably doesn't work, but I think this > simulation told me where the error was!) > > The simulation "error" is viewable on my website: > http://www.interrupt.dk/sim.jpg > > The trigger is a level/edge trigger that should activate on rising and > falling edges! > > > > And like allways: Thanks for helping > > Preben Holm Looks like it's a functional simulation. Are you sure you don't drive trig from the test bench _also_ ??? or don't you drive trig by two sources ? btw : you should adopt a more robust coding style : use async reset, do not mix enable and clock in the same test etc...Article: 83168
Acceed See wrote: > Ziggy, > > For this board, can buyer specify a Spartan 3 1000K FPGA? > On this page, it mentioned the board can accomodate three types of FPGA, > http://www.digilentinc.com/Products/Programmable.cfm > but on the actual page, this information is missing. > http://www.digilentinc.com/info/S3Board.cfm > > Thank you for your attention. > > > Donno, but im sure they would respond to an email. Personaly i was interested in the Virtex-2, as its got 2 real PPC cores. Could have lots of fun with that * drool *.. The S3 board does have a 1M option now, you see it in the shopping cart. And in reality that is what im going to be getting, unless i can find a way to be declared a student.. Its like only 120 or so with the 1M upgrade, much more affordable to a simple hobbiest like myself.Article: 83169
mb wrote: > Hi, > > Can any1 tell me what exactly is microblaze or in particulat what do > we mean by the term "soft processor" ?? > > If i have to work on some thing or implement some thing on say virtex > 2 board , do i have to use microblaze every time or can i just skip > micro blaze part and do some simple implementations without it ?? > > Hope any1 can give me a simple answer to this .... > > thanks Soft Processor = a cpu implemented in programmable logic. Nope, you are not stuck with the MBlaze. its just one of many, or you can roll your own from scratch. Check out opencores.org for others that are already done for you..Article: 83170
> Looks like it's a functional simulation. Post-map (but only for the single module) I haven't really found out how to write a testbench that "looks" into a single module of a whole design - the module should work stand alone. > Are you sure you don't drive trig from the test bench _also_ ??? > or don't you drive trig by two sources ? Yes I'm sure. > btw : you should adopt a more robust coding style : > use async reset, do not mix enable and clock in the same test etc... Async reset? Why not sync reset? And you mean if rising_edge(clk) and hold = '1' then ... end if; is worse than if rising_edge(clk) then if hold = '1' then ... end if; end if; Thanks for your expertise! Preben HolmArticle: 83171
Hi Info, I forgot that the lcd_tick should only be period long... that was the problem :( Does this function for generating lcd_tick out of a 10m and 250k clock look good? I havent tested it yet on the board, but it works in the simulator... process (clk_250k,clk_10m) variable temp: bit; begin if clk_250k='1' and rising_edge(clk_250k) then lcd_tick<= '1'; temp:='0'; elsif temp='0' and rising_edge(clk_10m) then temp := '1'; elsif falling_edge(clk_10m) and temp='1' then lcd_tick <= '0'; temp:='0'; end if; end process; regards, BenjaminArticle: 83172
As I understand we are using the program WinCUPL to produce .JED files
for GAL22V10 microcontrollers. I appologize for any misused
terminology and see that it's not really debugged at all.
This is the working code I have been given. As I understand it
defines states and has a clear sequence where one state moves to
another depending on the three inputs. Now, several of the states
are redundant to create the time lag that is supposed to occur before
the 'go' light appears.
Name Lab9C;
Device G22V10;
Format j;
/*Input Definitions */
pin 1 = clock;
pin 2 = a;
pin 3 = b;
pin 4 = r;
/* Output definitions */
pin 19 = go;
pin 20 = wina;
pin 21 = winb;
pin [15..18] = [Q3..Q0];
Field Lab_9_Game_Design = [Q3..Q0];
$define S0 'b'0000
$define S1 'b'0001
$define S2 'b'0010
$define S3 'b'0011
$define S4 'b'0100
$define S5 'b'0101
$define S6 'b'0110
$define S7 'b'0111
$define S8 'b'1000
$define S9 'b'1001
$define SA 'b'1010
/* Logic equations */
sequence Lab_9_Game_Design {
PRESENT S0
IF !a & !b & !r
NEXT S0;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S1;
IF a & !b & !r
NEXT S1;
PRESENT S1
IF !a & !b & !r
NEXT S2;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S2;
IF a & !b & !r
NEXT S2;
PRESENT S2
IF !a & !b & !r
NEXT S3;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S9;
IF a & !b & !r
NEXT SA;
PRESENT S3
IF !a & !b & !r
NEXT S4;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S9;
IF a & !b & !r
NEXT SA;
PRESENT S4
IF !a & !b & !r
NEXT S5;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S9;
IF a & !b & !r
NEXT SA;
PRESENT S5
IF !a & !b & !r
NEXT S6;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S9;
IF a & !b & !r
NEXT SA;
PRESENT S6
IF !a & !b & !r
NEXT S7;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S9;
IF a & !b & !r
NEXT SA;
PRESENT S7
IF !a & !b & !r
NEXT S8;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S9;
IF a & !b & !r
NEXT SA;
PRESENT S8
OUT go;
IF !a & !b & !r
NEXT S8;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT SA;
IF a & !b & !r
NEXT S9;
PRESENT S9
OUT wina;
IF !a & !b & !r
NEXT S9;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT S9;
IF !a & b & r
NEXT S1;
IF a & !b & !r
NEXT S9;
IF a & !b & r
NEXT S1;
IF a & b & !r
NEXT S9;
IF a & b & r
NEXT S1;
PRESENT SA
OUT winb;
IF !a & !b & !r
NEXT SA;
IF !a & !b & r
NEXT S1;
IF !a & b & !r
NEXT SA;
IF !a & b & r
NEXT S1;
IF a & !b & !r
NEXT SA;
IF a & !b & r
NEXT S1;
IF a & b & !r
NEXT SA;
IF a & b & r
NEXT S1;
}
For my version (which does not work) of the lab I used only four
states, trying to use less states to simplify my program. I also
attempted to use a FIELD to define the inputs sets (again, I
appologize if I'm not using the correct terms, we were taught this by
the instructor very informally). When I program a chip with this and
wire it up the GO light and the WinA light are both on almost
constantly. Since no state of my program has two OUTs at the same
time I am very confused.
Name Lab9A;
Device G22V10;
Format j;
/* This is Lab 9 */
/* Inputs */
Pin 1 = Clock;
Pin 2 = InA;
Pin 3 = InB;
Pin 4 = Reset;
/* Outputs */
Pin 15 = WinA;
Pin 14 = WinB;
Pin 16 = GoL;
Pin [17..19] = [Q3..Q1];
/* State Assignment */
FIELD Game = [Q3..Q1];
$Define Start 'b'000
$Define Wait 'b'001
$Define GoTime 'b'010
$Define AWins 'b'011
$Define BWins 'b'100
FIELD mode = [Reset,InB,InA];
Zippo = mode:[0,3];
ItsA = mode:1;
ItsB = mode:2;
StartIt = mode:[4..7];
/* Logic */
Sequenced Game{
Present Start
IF Zippo NEXT Start;
IF ItsA NEXT Start;
IF ItsB NEXT Start;
IF StartIt NEXT Wait;
OUT !WinA, !WinB, !GoL;
Present Wait
IF Zippo NEXT GoTime;
IF ItsA NEXT BWins;
IF ItsB NEXT AWins;
IF StartIt NEXT GoTime;
OUT !WinA, !WinB, !GoL;
Present GoTime
IF Zippo NEXT GoTime;
IF ItsA NEXT AWins;
IF ItsB NEXT BWins;
IF StartIt NEXT GoTime;
OUT !WinA, !WinB, GoL;
Present AWins
IF Zippo NEXT AWins;
IF ItsA NEXT AWins;
IF ItsB NEXT AWins;
IF StartIt NEXT Wait;
OUT WinA, !WinB, !GoL;
Present BWins
IF Zippo NEXT BWins;
IF ItsA NEXT BWins;
IF ItsB NEXT BWins;
IF StartIt NEXT Wait;
OUT !WinA, WinB, !GoL;
}
I have attempted to rewrite my code a variety of ways and always the
same faulty output occurs. If we throw switches (connected to InA
and InB) we can get the WinA and WinB outputs to blink sometimes in a
way they are generally supposed to. However, why are they blinking?
If the Reset switch is not thrown the code should not loop at all.
I suspect that I have used bad or sloopy sintax somewhere in my
program (this would be considered a program, correct?) and as a
result my chip does not know how it should act.
If my description of the lab output is inadaquate I can go and run my
program again and take better notes. I'm hoping that my error would
be obvious to a more skilled programmer.
Where does my program fail where the working code succeeds?
Thanks again for the help.
Article: 83173Even I had the same problem when I was using my own cross compiler ..but when I used the cross compiler from Montavista ..everything worked fine ...May be u may give that a shot -- Parag BeerakaArticle: 83174
Thanks! But, I was almost sure that I had read that a floating point adder was much more expensive (in terms of slices or CLBs) than a floating point multiplier since it needed to normalize one of the operands. Was I wrong about this?
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