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I tried just the Linux Kernel alone ( 2.4.26) and it worked for me -- ParagArticle: 84401
Can anybody recommend a decent DDR2 development board with a Xilinx FPGA ? I have the TED board here and that seems to be very useless ... Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84402
Try the ">>" button in the upper right corner "Geogle" <georgevarughese@indiatimes.com> wrote in message news:1116392539.922971.178880@g49g2000cwa.googlegroups.com... > Just wondering if it is possible to detach the schematic > viewer from the main ise window. (in 7.1i or so.) > Also is it possible to configure a third party tool for > viewing the schematic ? > > I know that it is possible to configure the text editor. > But is it possible for the schematic viewer too ? > > Thanks, > George >Article: 84403
Hello, If you haven't done so already, please file a support case with the Xilinx hotline. Make sure to specify what version of the IP core you are using, and it would probably help if you also submitted a schematic of your board. Eric Crabill "Andreas Loew" <fpgahardware@gmx.net> wrote in message news:ee8e58f.-1@webx.sUN8CHnE... > Hi, we recently bought the PCI Express Endpoint Core from Xilinx and implemented it into a Virtex 2 Pro 50 device. > > We have some experience with MGT connections and never had problems. > > But up to now we could not get the core running. We expect that the core will be detected by the BIOS of our PCI Express PC - but nothing happened. > > We could measure a stable reset pulse at boot-up of the PC. We expect that the signal trn_lnk_up_n will go high during link training and then goes low to indicate link up. But this signal stays low all the time. > > BTW: We heard that the Spread-Spectrum feature of some mainboards is critical, but as far we can measure there is no modulation of the 100MHz mainboard provided clock. > > Does anybody here have any experience with the usage of PCIexpress in FPGA ? Any suggestions welcome ! > > Regards AndreasArticle: 84404
Rudi, ML451 V4 memory development pcb? Austin Rudolf Usselmann wrote: > > Can anybody recommend a decent DDR2 development board > with a Xilinx FPGA ? > > I have the TED board here and that seems to be very useless ... > > Thanks, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84405
This is why you will get paid the big bucks!!! Now figure how much you need to make serial or registered to accomplish the task. I bet some registering but not completely a serial approach will work. gmArticle: 84406
So I've got the whole VHDL thing down, but I've still got some problems understanding how to set up timing constraints. I've got a 50 MHz oscillator that I use two DCMs to turn into three clocks, 40 MHz @ 0<, 40 MHz @ 180<, and 20 MHz @ 0<. The master clock for all the logic is the first of the 40 MHz clocks. But for some reason I can't get the Constraints Editor to accept this as a clock, and so I can't base any timing constraints off of it. How do I get it to? The other two clocks handle some trivial amount of logic, but mainly serve as clocks to external hardware. Some of them have been getting switched around on the output ports as I try to tweak down the timing, so I often have combinational logic like: out_clock_1 <= internal_clock; out_clock_2 <= internal_clock; where out_clock 1 and 2 are ports on the top-level entity. How do I convince XST to keep the name internal_clock for this signal, such that I can know what to try to set constraints on?Article: 84407
Bit wide shifts are slowing you down....
Are you implementing the CORDIC as a beautifully pipelined hardware datapath
or are you doing this in software?
CORDIC should be able to run easily at 150 MHz+ if I recall correctly. If
he doesn't respond quickly here, look for Ray Andraka's CORDIC information
in his paper entitled:
A Survey of CORDIC Algorithms for FPGAs
at
http://www.andraka.com/papers.htm
<m_oylulan@hotmail.com> wrote in message
news:1116414961.535018.32730@g49g2000cwa.googlegroups.com...
> Hello,
>
> I'm trying to write a CORDIC macro for a polar transmitter FPGA design.
> I've used the parallel approach, but when I do a timing estimation the
> longest delay path is through the CORDIC routine, and limits the
> maximum clock rate of the whole design to about 40MHz. Other parts of
> the design on the same board need to run at much faster rate so I'm
> considering using a bit-serial version.
>
> As I understand it, the bit-parallel implementation has low latency and
> therefore high throughput, but because of the the word-wide shifts it
> clocks at a slower rate. Conversely, the bit-serial
> routine has a high latency and low throughput rate, but allows the
> board to run at a faster clock rate. Is this right?
>
> My question is:
>
> In the bit-serial implementation, you still need to perform the shift
> operation on the entire word to select the right bit to send to the
> bit-serial adder/subtractor, so how does this solve the problem of a
> slow clock rate due to the shift operation?
>
> Thanks,
>
> Mees
>
Article: 84408Rob Gaddi wrote: > So I've got the whole VHDL thing down, but I've still got some problems > understanding how to set up timing constraints. > > I've got a 50 MHz oscillator that I use two DCMs to turn into three > clocks, 40 MHz @ 0<, 40 MHz @ 180<, and 20 MHz @ 0<. > > The master clock for all the logic is the first of the 40 MHz clocks. > But for some reason I can't get the Constraints Editor to accept this as > a clock, and so I can't base any timing constraints off of it. How do I > get it to? The easy way around the constraints editor is to edit the UCF file manually and add a line like: NET "my_clock_net" PERIOD = 25 ns HIGH 50.0%; > > The other two clocks handle some trivial amount of logic, but mainly > serve as clocks to external hardware. Some of them have been getting > switched around on the output ports as I try to tweak down the timing, > so I often have combinational logic like: > > out_clock_1 <= internal_clock; > out_clock_2 <= internal_clock; > > where out_clock 1 and 2 are ports on the top-level entity. > > How do I convince XST to keep the name internal_clock for this signal, > such that I can know what to try to set constraints on? If you're putting out clocks on pins, you should be aware that the best way to get from a global clock route to a pin output buffer is by way of the DDR flip-flop. You must instantiate these, but that pretty much gets around the problem of losing your global clock net name. I usually use FDDRRSE to generate output clocks with D0 logic high, D1 logic low, C0 internal_clock, C1 NOT internal_clock (or 180 degree internal_clock if you have it from the DCM). R and S ports can be logic low. I've found that when you take a clock signal on a global net and attach it to more than one non-clock load, the place and route software will use a single point to get from the global net to the first non-clock load and then use (high-skew) local routing resources to route to the other loads.Article: 84409
"Rob Gaddi" <rgaddi@bcm.YUMMYSPAMtmc.edu> wrote in message news:d6g5jd$7aa@gazette.corp.bcm.tmc.edu... > > I've got a 50 MHz oscillator that I use two DCMs to turn into three > clocks, 40 MHz @ 0<, 40 MHz @ 180<, and 20 MHz @ 0<. > You'll save yourself a lot of trouble, and 2 DCMs, by making one clock at 80MHz, and using enables for the 3 clock domains you mention. > > The master clock for all the logic is the first of the 40 MHz clocks. > But for some reason I can't get the Constraints Editor to accept this as > a clock, and so I can't base any timing constraints off of it. How do I > get it to? > One way is to use the Floorplanner or the FPGA editor to see what the net name is. > > The other two clocks handle some trivial amount of logic, but mainly > serve as clocks to external hardware. Some of them have been getting > switched around on the output ports as I try to tweak down the timing, > so I often have combinational logic like: > > out_clock_1 <= internal_clock; > out_clock_2 <= internal_clock; > > where out_clock 1 and 2 are ports on the top-level entity. > Don't feed clocks out like that. If you do, the phase relationship between the external clock and the internal clock depends on routing delays. Use the DDR IOB FFs to get clocks out, the timing is far better defined this way as the global clock only connects to clock inputs of FFs, and so never has to venture onto the normal routing. Figure 2 of XAPP265 shows how to do this for CLOCKOUT. > > How do I convince XST to keep the name internal_clock for this signal, > such that I can know what to try to set constraints on? > Get the name of the net as described above and put it in the UCF file. Cheers, Syms.Article: 84410
Comments following. "Berty" <wooster.berty@gmail.com> wrote in message news:1116266759.025667.48250@g47g2000cwa.googlegroups.com... > I'm not aware of any book that gives good explanation however I can > suggest a simple solution. > > Write a simple code and I do mean simple like 2 bit counter or > something like this which you know how the logic should have been done > if you had to draw it using gates and FF's. > > Now synthesis and place and route it and open the floorplaner or fpga > editor or even better both and see that you recognize what it what and > so on. > > Than try to move it to be where you want it to be and see what was > added to the constrain editor (Once you move thing around you can ask > the tool to save the needed constrain in the constrain file) > > Look on the constrain file and see if it make sense to you. > > Now come the fun part, try remove some of those constrain and see what > happen. As you will notice some constrain are nice but not necessarily > needed at least on many case while other do. > > Now that you feel more comfortable make another simple design like > maybe state machine with 2 bits or something else, synthesis place and > route and see what you got. > Than add constrain to put the FF for example where you want and than > synthesis and place and route it and see if they moved to the place you > ask them to move. > > Only after you got comfortable with the small design go the your main > design as in big design you have so much wiring going all over as well > as less space to move thing not to mention when you move one thing you > might be hurting something else and than need to fix another problem > and before you know you will see that sometime to fix one problem you > need to generate two new and fix them as well. > > You might want also later to play with logic lock to tell the tool in > what area to put your state machine and so on, but always try it first > with small design where you can see what happen and not get > "overwhelmed" due to other part which make it difficult to figure > what it what and where until you get accustom. > > Have fun. > > Berty's general comment corresponds to a key part of solving the critical path: isolate it. Several times where I had trouble meeting critical timing (generally due to the tool's inability to map and/or place things well), I would break out that portion of the design (figuratively, by removing other constraints, or literally, by creating a test design just containing the portion of interest), and play with location and timing constraints. The smaller design, or loosely constrained design, routes MUCH faster, and you can iterate. In the process, I found out the the Xilinx 4k series (XL, XLA?) had a VERY fast input to output path, if you just needed an inverter. However, you had to choose the correct IOB groupings--the pins not only had to be close, there couldn't be any unbonded IOs between them. I also found that left-to-right was different from right-to-left for adjacent CLBs. These and other design tricks were learned over the years by experimenting; it's how you learn to get the most performance out of the parts (along with reading the App notes and data sheets, and following the relevant newsgroups, etc.) You tend to leave some significant performance on the table if you just press "Run" and hope for the best. JasonArticle: 84411
I am trying to use a 3rd party IP core I2S_OPB as a peripheral in my microblaze hw design. When using the Create/Import Peripheral wizard I an getting error that it cannot find my library. I think I am tripping over a file structure issue. Where should I put my I2S_OPB_package file in order for both the XST (or synplisity) & "Create/Import" to see it ? I have tied "move to library", but only lets me move to the verilogone, when my files are all int vhdl. Any thoughts ? Thanks. JKArticle: 84412
It appears to be a BGA install problem. I have the one board loaded up with a test program that toggles all the I/Os so I can probe around on the board and test the BGA installation. One of the I/Os that is supposed to be toggling is just an open circuit. When I squeeze the board and the BGA between my fingers it becomes a closed circuit and I get my square wave out. When I let go it goes open again. It just so happens that the /PROG pin is another one of these open circuits. If I squeeze the board and BGA and hit my reset button, the FPGA reboots itself. If I'm not squeezing the button does nothing. I am going to assume that the other board that I can't even get to program has the same problem, just with more opens under the chip. On that one I can see the JTAG TDI signal going into the FPGA is toggling but the TDO out of the FPGA is always high. I guess it could be a board manufacture problem, with the vias not working right and having intermittent connections in them. I doubt it though. Sigh. I hate BGAs.Article: 84413
Antti-
XMD does not currently support the USB cable. Support will come in an
upcoming 7.1 service pack. You should use the PC4 for now.
-Michael
Antti Lukats wrote:
> Hi Dear Xilinx and users of Xilinx FPGA devices,
>
> Q: is it possible to use:
>
> 1) Xilinx ISE/EDK 7.1 all latest service packs
> 2) Xilinx platform usb cable (pld updated by impact 7.1)
> 3) target device Xilinx V4 LX25
> 4) EDK XMD (I think I tried all variants of them!)
>
> All the above are Xilinx latest and greatest!
>
> To my understanding its not possible to get them to work, XMD fails to
> connect or crash terminates no matter what I use.
>
> I have a fresh new dual CPU PC workstation (with NO PARALLEL port), I
> assumed that to be ok, as Xilinx has now the new and better usb cable. I
> have at my use:
>
> 1) original Xilinx Cable III - 1 pcs
> 2) amontec cable emulating Cable III - 1 pcs
> 3) Xilinx parallel Cable IV - 3 pcs
> 4) Xilinx usb cable - 2 pcs
>
> and all that hardware is piece of junk !!
> except amontec cable that I use regularly to program Atmel AVR's, as I can
> not use them as the XMD crashes for the system I need to use it for.
>
> I am really really really getting upset again over Xilinx EDK, the amount of
> time wasted with the fights with it!
>
> So the question, is it possible or not to use EDK 7.1 XMD, V4 and platform
> usb cable?
> [Y/N]
>
> An simple authoritave NO would be great help, I would not longer struggle
> then trying the impossible, of course if there is some trick to make it all
> work the better
>
> Antti
Article: 84414John, thanks for your answer. What you describe is pretty much what I did - I used FMAPs, LOCs, RLOCs and PROHIBITs to force PAR to do what I thought was best, but without comprehensive documentation about the switch matrix I never got beyond a certain performance. Needless to say that I spent far too much time on that. People at Xilinx have been very helpful, but the ultimate solution has yet to be found. What I experienced were ratios of flight time in the order of several hundred - on connections which looked very similar in the FPGA-editor. I'm still hoping to get a good solution for this problem. Cheers Gunter "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1116074876.5472.0@nnrp-t71-03.news.uk.clara.net... > There are particular routes from LUT output to particular LUT inputs that > are faster. You can get down about 10 pS from my memory. We did exactly > this on our CRC32 core which has multiple 3 levels of LUT and can run at > about 380 MHz in V2. To do this though you have to spend a lot of time in > FPGA Editor and going back and forward to get the timing. You get > different timings from a LUT o/p to different inputs of the next (same) > LUT so controlling which output links to which input gets you reduced > flight times. > > Starting from the simple end you can floorplan your LUT and roughly based > on spacial distance before going to the extremes I describe above. You can > also use the multiple place and route feature of the tools and that might > get you close enough. Another thing to try is setting your synthesiser for > area. Seems contractory but sometimes goes faster than speed optimisation. > Try all of these first then try the more difficult. > > John Adair > Enterpoint Ltd. - Home of Spartan-3 PCI Development Boards. > http://www.enterpoint.co.uk > > > "Gunter Knittel" <knittel@gris.uni-tuebingen.de> wrote in message > news:d631kk$clv$1@newsserv.zdv.uni-tuebingen.de... >> Hi, >> >> I'm trying hard to speed-optimize an arithmetic function >> on a VII 4000 - 4 device, using ISE 7.1. >> I have minimized the logic down to a few layers of 4-input >> LUTs. However, the routed design spends much more time >> on the wire than in the LUT. In particular, communication >> from one slice to the next in the same CLB through the Switch >> Matrix can be slow, sometimes in the order of 1ns. >> >> So my question is: is there no fast private communication between >> slices in the same CLB (other than shift and carry)? Is there any >> documentation available about the performance of the Switch Matrix, >> and how I should arrange the logic such that fastest interconnects >> can be made? >> >> Thanks a lot >> Gunter >> >> > >Article: 84415
Small addition, while using FPGA editor to find name or even to use as reference for constrain syntax is a good solution, it might be better if you can add a attribute to keep the signal name if possible as if not and the name keep get change every time you synthesis than you might need to redo what you do every single time you re-synthesis. If you can't keep the name due to any reason, one trick you might consider which can be useful in many times is if possible route the signal to a spare IO as IO keep there names. Have fun.Article: 84416
anyone interested?Article: 84417
"Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message news:c9mdnXx_EujE9RTfRVn-2w@rogers.com... > > we will be increasing the spec to 1.25 Gbps in an upcoming version of > Quartus II. > Paul, Does that mean in Stratix II I could run an internal clock at 625MHz and use the I/O DDR to move data out at 1.25Gbps? Thanks, Syms.Article: 84418
"Minimum" <brahms_view@yahoo.it> writes: > anyone interested? The FBI?Article: 84419
Hello All:
No, I didn't patch anything. Just the regular Mandrake 10.1
Powerpack install. Don't know if this procedure will work for the
Community Edition.
1) set your LD_LIBRARY_PATH to the Xilinx installation CD
LD_LIBRARY_PATH=/mnt/cdrom/platform/lin/bin/lin:$LD_LIBRARY_PATH
2) Install OpenMotif. I used this file:
http://rpmfind.net/linux/RPM/fedora/updates/3/x86_64/openmotif-2.2.3-6.FC3.1.i386.html
openmotif-2.2.3-6.FC3.1.i386.rpm
3) Install libcurl. It's located in the Mandrake install DVD.
You also have to make a softlink to libcurl.so.3.0.0 as libcurl.so.2:
ln -s libcurl.so.3.0.0 libcurl.so.2
This will get the installer working. After you install all three CDs,
run:
(assuming you installed ISE at /opt/Xilinx)
/opt/Xilinx/settings.sh
This script was't with execute permissions, so I had to chmod' it
Now, just run:
/opt/Xilinx/bin/lin/ise &
This should start ISE. I had one more 'glitch'. I couldn't create,
open, etc, any projects. If I tried to create a new project, ISE
would tell me "cannot create tem project at...". If you look at the
path it[ trying to create the project, it[ your own tmp
path, problably under you home dir. What gives? The solution is
simple, but very stupid. It's a ISE bug, obviously, unset the
'TMPDIR' environment variable. No, don try to point it to another
path, it's a ISE bug and even as root you get the error, so it's not
a permitions problem. So unset it:
unset TMPDIR
If i do:
$ export | grep TMP
you should read something like this:
declare -x GCONF_TMPDIR="/tmp"
declare -x TMP="/home/lsantos/tmp"
The important thing is NOT to have TMPDIR in this list. Exit and start
ISE again, obvioulsy with the same terminal you 'unseted´ the
variable. Voilá! ISE works. Although the simulator doesn't :-(, which
was my main reason to install ISE 7.1 in the first place, as I already
have ISE 6.3 worwing fine.
Article: 84420Hi all, I ahve a question to ask the public using EDK windows version. Suppose I create a BSP, where are the pao files stored, in Xilinx Techxclusive they have notified that it resides in Data folder of the bsp. I am using EDK 6.3 and i imported a peripheral which i created earlier. Somehow all i see in te folder is a system.ucf file, and no PAO or the MPD files. Any suggested places for thiese files to search into?? Thanks Chakra.Article: 84421
In article <1116360522.339918.256230@o13g2000cwo.googlegroups.com>, gallen <arlencox@gmail.com> wrote: >I'm sure this kind of things has come up in the past, but given that >things change, I'd like to throw this out there. > >Which simulators do people like to use for their HDL purposes? I've been using GHDL quite a lot lately. > >I have tried a couple of simulators and I was curious about peoples >recommendations. > >I have used Modelsim XE starter for my purposes (I am just a hobbyest >now), icarus verilog and GPL cver. I have used the built-in quartus >simulator as well. > >Also, I haven't really discussed VHDL. Which are best for this? I've >heard GHDL is pretty good. I'm not sure how 'feature complete' GHDL is (if you define 'feature complete' to mean language features). I haven't run into any problems lately (I'm currently using the latest 0.18 release), but that doesn't mean that problems don't exist. If you count a frontend GUI as part of being 'feature complete' then it's probably not what you're looking for. Personally, for my useage, a GUI often gets in the way. I prefer to write scripts or Makefiles to compile/simulate my designs, though, so for me it's a feature. Also, I've been doing some mixed-language modelling (part of my algorithm is writen in C and part in VHDL, the two communicate via pipes) so the fact that GHDL is just another frontend to GCC is a big plus since it's easy to write foreign models in C and link them to the testbench. The open source nature of GHDL is helpful for this mixed-language approach since I can always look at the source to figure out some of its internals if need be. > >I've mostly discussed free simulators, but I'm also interested in how >expensive simulators compare to the free sims The author of GHDL readily admits that it's not as fast as Modelsim (used to be considered the fastest VHDL simulator - is it still?). But GHDL is free, so if you have a cluster of machines simulating your designs you don't need to buy a license for each machine. And since PCs running Linux are way cheaper than ModelSim licenses, if you need better performance you can just add more PCs to your cluster. Also, I suspect that there is still a lot of room for performance improvements in GHDL - the author has been concentrating on features and bug fixes so far; he has said that he would concentrate more on performance later. PhilArticle: 84422
Hi Symon, There is a hard serializer/deserializer circuitry available for the left and right LVDS I/O banks. These SERDES blocks allow you to deserialize/serialize by any factor between 4 and 10x. For example, you could bring in a 4x data bus running at 312.5 Mhz. Or you can bypass the SERDES block and use the DDR registers for a 2x SERDES. Or bypass completely for 1x... but not at 1.25 Gbps. I don't know what speed the SERDES/DDR I/O clock can run at or will run at when we update this specification. I'm sure it will be published at the time. We also have dedicated Dynamic Phase Alignment (DPA) circuitry for source-synchronous applications. The DPA block enables you to eliminate channel-to-channel and clock-to-channel skew. It achieves this by selecting the best clock phase to use for each I/O pair, centering the sampling window in the eye. Regards, Paul Leventis Altera Corp.Article: 84423
"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:1116355048.275044.78030@o13g2000cwo.googlegroups.com... > Hi Alex, > > There are two Cyclone kits sold by partners of ours that are in the > same price range: > > Future $49 Cyclone/Nios II eval kit: > http://www.altera.com/products/devkits/partners/kit-future-badge.html > Altium $99 kit: > http://www.altera.com/products/devkits/partners/kit-alt-live-design.html > > With Cyclone II now available, I can assure you there will be low-cost > Cyclone II dev kits available in the near future. Sorry, but I can't > comment on exact dates. > I have an Altium Altera board(and a xilinx one) It doesn't come with any project file ready to use with Quartus and you have to work out the connections as well. Only annoyance is lack of config prom. The lack of Quartus project files means it is unsuitable for beginners unless they are using it with the Altium software. That future board is not even in the same league as the Spartan 3 starter kit. AlexArticle: 84424
my FPGA board is XILINX VIRTEX II pro of Memec Design, and the sdram controller IP core is OPB_SDRAM, I add the IP core when i generate a project at the BSB, I think it's wires are not wrong, BUT i don't know the flow of accessing SDRAM, can you help me ?
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