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"Nicolas Matringe" <nic_o_mat@msn.com> schrieb im Newsbeitrag news:1116938369.355985.65660@z14g2000cwz.googlegroups.com... > Right here > http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=21127&iLanguageID=1 > > Nico > Tanks! I feel so stupid, I really entered AR21127 into the search box, tried the answer browser and did not land on the correct page. I have some FX12 and FX20 silicon so I wanted to check out that AR ASAP. AnttiArticle: 84676
methi wrote: > Hi Aurash, > > These are the error messages: > > ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is invalid: > No such site on This basically tells you that there is no pin "P130" on your FPGA, which is understandable... Haven't seen any FPGAs with 130 rows/columns around lately :) You're trying to route the signal dig_video_out<3> to a pin that does not exist. Same with most of the other signals, your FPGA can't possibly have pins like that. Check your pin assigments again. cu, SeanArticle: 84677
what part/package are you targeting?
Aurash
Article: 84678Today i have tried to modify the parameters: CAS_LAT from 2 to 3,TREF from 64 to 32,and find this have nothing effect in the programm. Now i can assure the problem of reading or writing SDRAM has relation with the cpu. In the Powerpc, the operationt is all right,but in the Microblaze, the Wrong is inevitable, i need more advice, i need your help!Article: 84679
Adrian,
Reinventing the wheel? just use the ethernet controller (which has fifos
by the way, to cross the clock domains for the recovered ethernet clk to
OPB clock) and store the packets with DMA in SDRAM
Or
use a PC (software only) - if you are not going to process the packets
on the fly the PC will do.
Aurash
adrian wrote:
> Hi there,
>
> I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using
> Microblaze soft-core.
> My intention is to save packets recieved from the network in SDRAM for
> later process.
> I have been thinking of using a SDRAM FIFO to be able to process the
> packets after been saved in memory.
> As I am working with EDK 6.3 I was thinking of using a FIFO IP core to
> be used in SDRAM.
> Can this be done this way? EDK doesn't include any FIFO IP core on the
> predesigned cores.
> I also have thought of creating a FIFO with Xilinx COREGEN and then
> including the FIFO in my EDK project but I can'f figure the way of
> exporting the .vhd files created by COREGEN into my EDK project.
> Has anyone ever used a FIFO in external memory with positive results?
> Which is the best way to do this?
> Any advice will be appreciated since I am quite a newbie with FPGA's.
>
> Thanks in advance.
>
> Adrian Mora.
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84680"ivan" <ivan.fed@gmail.com> wrote in message news:1116760407.491379.25010@g47g2000cwa.googlegroups.com... > Hi, > > Thanks for all the inputs.I could compile the kernal successfully.But > when I download the same into the ML401 board with harware downloaded > from the site,XMD reports the error regarding address mapping.The > kernal comiled is supposed to load at location 0x8000_0000 and in the > hardware does not exist.How can I over-come this issue.Do anyone have a > compiled image for ML401 board.Both the .bit and .elf file. > > Any inputs at the earliest will be highly appreciated. > > Thanks & Regards, > Ivan > Tried asking on the uclinux microblaze email list ? link on http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/index.htmlArticle: 84681
"Rob Gaddi" <rgaddi@bcm.YUMMYSPAMtmc.edu> wrote in message news:d6i8cn$c5d@gazette.corp.bcm.tmc.edu... > Antti Lukats wrote: >> "Michael McGuirk" <michael.mcguirk@xilinx.com> schrieb im Newsbeitrag >> news:428BB131.1AB9E7E1@xilinx.com... >> >>>Antti- >>> XMD does not currently support the USB cable. Support will come in >>> an >>>upcoming 7.1 service pack. You should use the PC4 for now. >>>-Michael >> >> >> ok, thanks for rerply - on the PC where I need it I do not have parallel >> ports :( >> so I need to wait... >> >> Antti >> >> > I'm almost certain they make USB->parallel port adapters. Probably no > more than $20 or so from newegg. These only work with printers not much else.Article: 84682
Hi Aurash and Sean.. Thanks for helping me out.. I am using XC3S400_4TQ144.... There are totally 144 pins... And the connections have been made on the board..but the FPGA isnt programmed as yet... Thats what I was trying to do...program it...give the same pins to the variables in the UCF... Thanks, Methi..Article: 84683
Adrian, What you are describing sounds very much like XAPP536 which we also call Gigabit System Reference Design (GSRD) http://www.xilinx.com/gsrd There are two difference here, first it uses the PowerPC and not MicroBlaze, second it uses DDR-SDRAM instead of SDRAM. From a conceptual point of view though it can provide you with a good starting point and runs on a variety of platforms. I'm curious about one thing, since you are targeting a XC2VP7 device why are you planning on using MicroBlaze instead of the embedded PowerPC for this project? Ed adrian wrote: > Hi there, > > I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using > Microblaze soft-core. > My intention is to save packets recieved from the network in SDRAM for > later process. > I have been thinking of using a SDRAM FIFO to be able to process the > packets after been saved in memory. > As I am working with EDK 6.3 I was thinking of using a FIFO IP core to > be used in SDRAM. > Can this be done this way? EDK doesn't include any FIFO IP core on the > predesigned cores. > I also have thought of creating a FIFO with Xilinx COREGEN and then > including the FIFO in my EDK project but I can'f figure the way of > exporting the .vhd files created by COREGEN into my EDK project. > Has anyone ever used a FIFO in external memory with positive results? > Which is the best way to do this? > Any advice will be appreciated since I am quite a newbie with FPGA's. > > Thanks in advance. > > Adrian Mora.Article: 84684
Matthieu MICHON wrote:> > I experienced the same issue. It seems that the RPM implementation in > ISE 6.3 is kind of broken, and since the "Use RPMs" attribute is active > by default in the CSP Core Inserter, the design implementation is very > likely to fail with default settings. > > A simple turn-around is to un-check the "Use RPMs" attribute (located in > the Device panel of the CSP Core Interter). > Yep, I have ended up doing the same thing. It appears to me that the "Use RPMs" in 6.3 is broken.Article: 84685
As long as your reset is synchronous, you have a solid solution. Keep in mind there's a programming option to hold of operation of the FPGA until the DLLs are stable. If you *don't* engage this option, your reset ciruit should take care of everything for you. "Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:d6v8so$v3b$1@nobel.pacific.net.sg... <snip earlier quote> > Thanks for the feed back John and Peter. > > Quick follow up question: > > I have a reset block which prolongs the reset and does a few > other things. In addition to the Reset Button, I also take > the lock output from the DPLL that generates the clock to the > SoC. As long as there is no lock, I hold the system in reset, > and even after a lock for some more cycles. So perhaps my reset > should not be a problem after all ? If I assume that the lock > signal of a DPLL would be asserted some time AFTER configuration ?! > > Best Regards, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84686
Did you insert IOs when you synthesized the design (It could be the case
that tou dont have IBUFs OBUFS or IOBUFS connecting the actual signal
with your IO pad) ???or the mapper took out all your IO due to clock
missing (or constant in your HDL (trim out all your IOs) check the
detailed map report which shows all the signals optimised out.
Aurash
Article: 84687You should change your software programming style to using flowcharts for inputs instead. That way you can always have a graphical representation of your processes which are self-documenting. Plus, if you can get that method to catch on wil more developers, the client base for graphical revision control will increase and the dream of comparing schematic versions easily might be realized. If you prefer programming with text, look at Verilog (c-like in syntax to some degree) or VHDL (more complete in its rigorous approach). "Jansyn" <jansynf@worldnet.att.net> wrote in message news:2Utke.817631$w62.266903@bgtnsc05-news.ops.worldnet.att.net... > "Gary Pace" <xxx@yyy.com> wrote in message > news:5Kvje.113165$AE6.112367@tornado.texas.rr.com... > > > What am I missing ? What would be some examples of something better done > > in VHDL ? Are there examples of stuff that cannot be done in schematic ? > > Hello, > > I have never used a HDL, but I have an opinion anyway, this is usenet. > > I have a hardware and firmware (C and asm) background and recently > picked up an existing schematic based fpga design for modification. > My first fpga. > > What I miss most is the ability to compare the file I am looking at to > last weeks version, or the version that Joe modified. I have not found > a way to do that with schematics. I have gotten very used to this for > firmware. > > If there are any software types looking for a project, I would pay for > a tool to do this. > > Ben > >Article: 84688
Are there any Bresenham line drawing algorithms that are suitable for FPGA pipeline video streaming? In VHDL? b r a d @ a i v i s i o n . c o mArticle: 84689
Hi Aurash, My Map report is as follows: It doesnt show any removed signals.. How do I insert IO's when I synthesize the design?...Do u mean include them in the code?...If so , yes I have included them in the code(top level entity)... ------------------ Release 6.3.02i Map G.37 Xilinx Mapping Report File for Design 'top_1190_mem' Design Information ------------------ Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_1190_mem_map.ncd top_1190_mem.ngd top_1190_mem.pcf Target Device : x2s200e Target Package : pq208 Target Speed : -6 Mapper Version : spartan2e -- $Revision: 1.16.8.2 $ Mapped Date : Mon May 23 17:19:17 2005 Design Summary -------------- Number of errors : 21 Number of warnings : 0 Section 1 - Errors ------------------ ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. Section 4 - Removed Logic Summary --------------------------------- Section 5 - Removed Logic ------------------------- This is wat the Map report shows..... Thanks, MethiArticle: 84690
Designing a Eth Mac while have its own challenges it is not "too" difficult, however you need to consider two thing first - Base on how much experience you have it can take from few weeks to few years. What requirement you have for the Mac which can be as very simple or very complicated. For example even a simple question like do you need to support half duplex can add to the complexity not to mention learning etc. (Incase you are not familiar with Eth at all using the I2C you design there are as you now know several I2C controller, a slave only a master only a combination a master that support clock stretching, a master that support multi master, a master/slave that support 10 bit addressing, higher speed like 400K or 3.4M and so on, a simple slave you can probably finish in a day or two again depend on your experience however a complete full blast master with all the feature will take you a longer and of course the more features the more time you also spend on verification and building the verifiers) If this design is just for your own fun than go ahead if not do consider buying of the shelf Eth Mac there are plenty of flavor out there which will probably cost you less money and time than any other solution you can come with FPGA or cpu. Have Fun.Article: 84691
hi I generated my_system_ace.ace file using iMPACT for my design .bit file and I copied to the CF to configure the virtex4 FPGA on ML403 board. Bur I am getting error(Err led lights with red) when I selected my_system_ace.ace from the CF. any help please thanks byeArticle: 84692
Hi Antti, I agree with everything you said. I also encountered the ChipScope issue on a Virtex4 design with the ISE7.1 tools. Either disabling the "Use SRL16" or disabling the "Use RPM" provided a good workaround. One more problem I had to find out the hard way : if you are planning to use the new IDELAY feature in Virtex4 (e.g.for source-synchronous interfaces, or DDR/DDR2 interfaces as generated by the Xilinx MIG tool) you MUST have at least ISE7.1 SP2. And also if you are using IDELAY, you should (according to the user guide) also use the IDELAYCTRL block : but don't wait for the IDELAYCTRLRDY pin to go high (like the user guide says you should), because there's a bug in the bitgen tools that prohibit this. Maybe all this does not apply to your design, but if it does, this saves you a LOT of debugging time :-) best regards, Bart De ZwaefArticle: 84693
Antti Lukats wrote: (...) > the current major problem I have, seems only to be an issue of core inserter > in 6.3 (...) > Antti Hi Antti I experienced the same issue. It seems that the RPM implementation in ISE 6.3 is kind of broken, and since the "Use RPMs" attribute is active by default in the CSP Core Inserter, the design implementation is very likely to fail with default settings. A simple turn-around is to un-check the "Use RPMs" attribute (located in the Device panel of the CSP Core Interter). Hope this help ;) Matthieu (who also would be pleased to see native Mac OS X support for EDA tools)Article: 84694
are the pin names correct? because i thought in S3 they use a letter/number assignment and not p/nimber?Article: 84695
"zeeman_be" <zeemanbe@gmail.com> schrieb im Newsbeitrag news:1116951477.167113.5590@f14g2000cwb.googlegroups.com... > Hi Antti, > > I agree with everything you said. > I also encountered the ChipScope issue on a Virtex4 design with the > ISE7.1 tools. Either disabling the "Use SRL16" or disabling the "Use > RPM" provided a good workaround. > One more problem I had to find out the hard way : if you are planning > to use the new IDELAY feature in Virtex4 (e.g.for source-synchronous > interfaces, or DDR/DDR2 interfaces as generated by the Xilinx MIG tool) > you MUST have at least ISE7.1 SP2. And also if you are using IDELAY, > you should (according to the user guide) also use the IDELAYCTRL block > : but don't wait for the IDELAYCTRLRDY pin to go high (like the user > guide says you should), because there's a bug in the bitgen tools that > prohibit this. > Maybe all this does not apply to your design, but if it does, this > saves you a LOT of debugging time :-) > > best regards, > Bart De Zwaef > Hi many thanks! well I am still having problems, I was trying core gen not inserter hoping it does better job, it randomly worked, then I unchecked use RPM, regenarated but then my design did not work, then I unchecked use SRL and guess ? -- the design did not fit into V2-2000 !! my own design is 12% of the FPGA and one simple ILA core doesnt fit into the rest 88% !! uupsa! I am struggling to see if some combination is working for me AnttiArticle: 84696
Hi.. This is the way I have written the assignment in the UCF file..not sure if this is correct: for example: NET "dig_video_out<8>" LOC = "P113" | IOSTANDARD = LVTTL ; NET "dig_video_out<9>" LOC = "P112" | IOSTANDARD = LVTTL ; NET "dqm<0>" LOC = "P26" | IOSTANDARD = LVTTL | SLEW = FAST ; NET "dqm<1>" LOC = "P27" | IOSTANDARD = LVTTL | SLEW = FAST ; NET "pal_ntsc" LOC = "P77" | IOSTANDARD = LVTTL ; NET "probe" LOC = "p78" ; NET "ref_27mhz" LOC = "P53" | IOSTANDARD = LVTTL ; NET "sd_clk" LOC = "P30" | IOSTANDARD = LVTTL | SLEW = FAST ; NET "sd_clk_en" LOC = "P32" ; NET "sd_cs" LOC = "P35" ; NET "sd_ram_address<0>" LOC = "P60" | IOSTANDARD = LVTTL | SLEW = FAST | PULLUP ; I havent written anything about the component instantiations... Thanks, MethiArticle: 84697
Nicolas, The output jitter spec on APEX 20KE devices is .35% of output period, but it is RMS, not peak-to-peak. The conversion from RMS to peak-to-peak depends on the desired bit error rate and the observation period. But if you are getting 800 ps total jitter, that is reasonable for a 73 ps RMS jitter. So the next question on your mind will be "How to reduce output jitter?" First off, examine your input jitter. The device spec is 2% of the input period peak-to-peak, so 333 ps peak-to-peak jitter is acceptable. However, reducing the input jitter can reduce your output jitter in some circumstances. The key factor is the frequency of periodic jitter components. The bandwidth of the APEX 20KE PLL is around 5 MHz, so jitter below that frequency will pass but jitter above that frequency will be attenuated. For example, if the 60 MHz input signal is modulated by a nearby 1 MHz signal, then that 1 MHz jitter will pass through the PLL. On the other hand if it the jitter is random jitter, or higher-frequency jitter, then the PLL will attenuate this jitter. To break this down to practical advice, take a look at the jitter of your clock source with a tool like an Agilent DCAJ, LeCroy SDA6000A, or Wavecrest. These can break down the jitter into deterministic and random components, and also can show you information about the frequency components of the jitter. For example if the clock is coming from an oscillator that is routed through another device like a CPLD you may be picking up some jitter there. The second thing to look at on the system is the board layout of the APEX device. The APEX devices have separate VCC and GND pins for each PLL, and these should be isolated from the VCC and GND used by the logic or IOs of the device. There's also a separate VCC and GND pin for the clock output, and again you may want to isolate these VCC and GND pins from other ones, otherwise noise on VCCIO will show up as jitter on the clock output. You can determine if these are the problem by looking at jitter with and without the logic and IOs toggling - if the jitter is worse with toggling then this would be a good place to look. App Note 115 on the Altera web site has some more details. http://www.altera.com/literature/an/an115.pdf Sincerely, Greg Steinke Altera Corporation gregs@altera.comArticle: 84698
Also note that jitter is transferred from the core, power, and IOs to the PLL. See out technical note: http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf Austin gregs@altera.com wrote: > Nicolas, > The output jitter spec on APEX 20KE devices is .35% of output period, > but it is RMS, not peak-to-peak. The conversion from RMS to > peak-to-peak depends on the desired bit error rate and the observation > period. But if you are getting 800 ps total jitter, that is reasonable > for a 73 ps RMS jitter. > > So the next question on your mind will be "How to reduce output > jitter?" > > First off, examine your input jitter. The device spec is 2% of the > input period peak-to-peak, so 333 ps peak-to-peak jitter is acceptable. > However, reducing the input jitter can reduce your output jitter in > some circumstances. The key factor is the frequency of periodic jitter > components. The bandwidth of the APEX 20KE PLL is around 5 MHz, so > jitter below that frequency will pass but jitter above that frequency > will be attenuated. For example, if the 60 MHz input signal is > modulated by a nearby 1 MHz signal, then that 1 MHz jitter will pass > through the PLL. On the other hand if it the jitter is random jitter, > or higher-frequency jitter, then the PLL will attenuate this jitter. > > To break this down to practical advice, take a look at the jitter of > your clock source with a tool like an Agilent DCAJ, LeCroy SDA6000A, or > Wavecrest. These can break down the jitter into deterministic and > random components, and also can show you information about the > frequency components of the jitter. For example if the clock is coming > from an oscillator that is routed through another device like a CPLD > you may be picking up some jitter there. > > The second thing to look at on the system is the board layout of the > APEX device. The APEX devices have separate VCC and GND pins for each > PLL, and these should be isolated from the VCC and GND used by the > logic or IOs of the device. There's also a separate VCC and GND pin for > the clock output, and again you may want to isolate these VCC and GND > pins from other ones, otherwise noise on VCCIO will show up as jitter > on the clock output. You can determine if these are the problem by > looking at jitter with and without the logic and IOs toggling - if the > jitter is worse with toggling then this would be a good place to look. > App Note 115 on the Altera web site has some more details. > http://www.altera.com/literature/an/an115.pdf > > Sincerely, > Greg Steinke > Altera Corporation > gregs@altera.com >Article: 84699
Hey, I want to make a very low frequency signal from a 100Mhz clk signal (since the rest of the logic has to work on this frequency) and i thought using a SRL16E as on-hot-signal shifter and then by placing them right i could easily divide the 100Mhz clk to very low frequencies and then bring it in a global clk net by using a clk buffer but when i do it i get the following warning (it works so this is just because i want to know what they mean with this warning): WARNING:Route - CLK Net:clk_pwm_OBUF may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. What do they mean with clk template? Thanks in advance, Greetz, Y
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