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you're right i got this SRL16E idea somewhere on the xilinx site (i remember reading something about it some months ago) and this seemed a good reason to give this idea a try since i need such slow signal (for very local logic + outside clk) ... and indeed there is no fixing mechanism ... i like the idea about the lfsr and the counter ... i'll check it out ... anyway thanks for your response ... kind regards "Peter Alfke" <peter@xilinx.com> wrote in message news:1117056428.983607.134130@g47g2000cwa.googlegroups.com... > Greetz, don't use the DLL or PLL, their division rate is much too > small. You seem to concatenate several SRL16s, each dividing by 16, so > that 5 LUTs divide by over a million. That probably means that you > ripple the clock, and end up with a very slow (=low-frequency) output > that has no clear phase relationship with your original 100 MHz. > Depending on your application that may or may not be acceptable. You > can also re-synchronize after each SRL16 and thus keep a tighter phase > relationship. > I worry about the functional stability of a 1-of-16 SRL16. > Theoretically it will recirculate a single1 forever. But what if it > loses its token, or what if it picks up another stray 1? There seems to > be no mechanism that fixes that automatically. I prefer circuits that > recover from a disaster. > I once looked at a 32-bit divider consisting of two SRL16s as LFSR > counters, and a 5-bit counter that detects the unique pattern of 32 > zeros. I think it fits into one CLB (4 slices = 8 LUT-FFs) > > Peter Alfke, Xilinx Applications >Article: 84776
You are correct. The "N" suffix does designate Altera's lead-free devices and our website does not explain this. I will make sure that this is corrected. Thanks for the input. John_H wrote: > From a search on Altera.com for RoHS, the "lead free" page (2nd hit) came up > with: > > A partial list of Altera's available lead-free devices is shown in Table 1. > Lead-free components are denoted by an "N" suffix at the end of the part > number, e.g., "EP1C12F324C6N". > > It's a sincere disappointment that the part numbering guide on their site > doesn't include the "N" i nthe "Suffixes" section. > > > "vax, 9000" <vax9000@gmail.com> wrote in message > news:d752cn$286$1@charm.magnus.acs.ohio-state.edu... > > Group, > > I am going to buy some EPM1270T144C5 from digikey.com but they listed > both > > EPM1270T144C5 and EPM1270T144C5N. Whats the difference? I searched > > google.com and altera.com but found nothing. > > > > Thanks > > > > vax, 9000Article: 84777
Hi Dave... > Gary, are you still listening? Like I said before: > "If you are considering learning VHDL (or Verilog), my advice is a > resounding YES; Do it, learn it." > > Austin, Austin..... > > More than two decades working with programmable logic and you are NOT > READY to suggest that learning VHDL or Verilog would enhance the skill > set of a schematic designer! You're putting words in my mouth that I didn't say or even remotely hint at! Of course someone working with programmable logic should, these days, learn an HDL. I never said differently, nor even addressed that issue. > I whole heartedly encourage Gary to "code in HDL"; he already uses > schematic entry and doesn't require any encouragement maintaining that > skill. I would too...but that isn't what I was commenting on, now was it? ;-) Regards, AustinArticle: 84778
I have tried to instantiate the Asynchronous FIFO core (v6) from Coregen, and it's been giving me trouble. First, I can't get it to produce a FIFO using distributed RAM (I wanted a 31-deep FIFO). When I try, it tells me there is a block RAM in the usage summary. If I try to open the core again after it's generated, it sometimes just beeps and exits (no error messages at all), sometimes it goes into the coregen wizard with "Block RAM" selected and the FIFO depth some enormous value like 65536. I am using ISE 6.3.03i, with the latest IP core updates installed. If it was a synch. FIFO, I have my own core, but I need an Async FIFO to cross clock domains and I dont want to waste a BRAM site. -JimArticle: 84779
Hi Mike, Thanks for answering... i'm aware of the IP encryption..... they will just give module definations... all others are encrypted... but since the designware utility that i have here can generate modules based on FPGA.. example Xilinx, maybe it come with an FPGA Compiler... first time using it actually.... some of my colleague have generated the IPs targetting it for Xilinx... and i think even manage to download it into the FPGA.... however it still did not work right... so this is the reason that i am wondering if there are other issues when using Synopsys Designware IPs in FPGA... so maybe the reason for the IPs inproper operation is because they misconnect some signals or something...or didn't make proper settings... and not the IP itself... can i assume this?? i just want to eliminate the many causes for this failure so i can devote more attention on the right fault... so my ultimate goal is to confirm that Synopsys Designware IPs can work with FPGA (Xilinx, etc) if using FPGA Compiler without any issue on the IP itself... is this an accurate deduction? really hope you, Mike or anyone who have experience in this area can advice me.. thanks so much in advance Best Regards, cromr "Mike Lewis" <this_is@bogus.ca> wrote in message news:<Kz0le.6597$dZ5.635010@news20.bellglobal.com>... > "Jon Beniston" <jon@beniston.com> wrote in message > news:1116594118.303249.206940@g49g2000cwa.googlegroups.com... > > Check out Synplicity's Synplify Proto. > > > > Cheers, > > Jon > > > > If the modules are encrypted ... which synopsys likes to do for its > designware > IP ... you will have to use a synopsys synthesis product such as fpga > compiler. > > MikeArticle: 84780
On Thu, 26 May 2005 06:30:05 +0000, Hw wrote: > Ok, > > I'm not designing an Ethernet MAC but I see that people now make FPGA > cores for this. > > I had a few "general" questions on how these might be implemented. > > 1. I know Ethernet bits flow across as Manchester encoded data. I see > that many of the cores run from a 25 MHz clock. > > How is the 125 Mbps (8/10 encoded data) serial stream generated without > some sort of clock multiplication? > The MAC interfaces to the phy using MII, which is a parallel bus. So all of your questions are not really applicable to the MAC. They are good questions vis-a-vis the phy, but (sensible) people don't generate phy's on FPGA's. ;-) [snip] > > Thank you. > H. --MacArticle: 84781
hi all, can anyone explain me how only one 2:1 mux is implemented in a 4-i/p look up table? Is it just the implementation of function O = A(/S) + B.S If this is the case then this implementation uses 3 i/p and only 8*1 locations. I don't know what i am guessing is correct. Please help if i am wrong.Article: 84782
Hi just a little thing: starting from 7.1 ISE abondoned the use of plain text project files, the new project files with .ISE extension are PKZIP compressed - that can cause an additional problem if ISE is not closed correctly as the ZIP archive could corrupted rendering it totally useless, ISE will refuse to open and use it. And there is no recovery, the project must be done from scratch - well its only the project file and can mostly easily be recreated, still if your computer (or ISE on it) can occasionally be doing crash, then I would say its a good idea to make manual backups of the ISE project files. Just in case. For me it was real surprise, I was working on project, configured the FPGA 'live' on the PCI board in the same computer, re-enabled the BARs run a test on that thing, it did froze the PC, well seing that the ISE project was corrupted after that was a bit scary. Well that the price you pay if you dont use plain text files, I really dont see any advantage that ISE now uses compressed project files that can not be manually edited, in previous releases I often did edit the .NPL files in text editor, thats not possible any more Antti BTW the word "ise" means in estonian language me(myself) so therotecial conversation Q: What was the reason for the crash? A: ISE (as Xilinx ISE) the answer (in estonian) would/could be understood that its YOUR fault. But its not our (the customers) fault if tools fail.Article: 84783
Hi, Thanks for the info, that pretty much answers most of the questions. We still could not find whether we can use JBits in Virtex4. I guess I will try this out and see if it works. -LoveArticle: 84784
No I didn't. Can you give me more details about this? Does this mean that the peripheral should support also bursts, or only bursts. What is the data width of the peripheral. At this moment it is 32 bits, should this be 64 bits? FrankArticle: 84785
Ben Twijnstra wrote:
>Hi Ray,
>
>
>
>>I don't have any shrink-wrapped off the
>>shelf IP for a general purpose Bresenham's implementation, but have
>>several implementations that are close that I could modify. These are
>>in VHDL for xilinx.
>>
>>
>
>If they're in VHDL, why would they only be for Xilinx? ;-)
>
>Ben
>
>
>
They have instanced primitives for performance as well as to enforce a
particular structure. Synthesis tools (both Synplify and XST are
notorious for this) frequently change how they infer things from version
to version. While designs where you are not particularly concerned
about maximum performance, minimum power or maximum density work fine
with 100% RTL, designs where you are pushing these corners cannot
tolerate the looseness of synthesized RTL. RTL synthesis also
frequently does not synthesize to specific FPGA structures such as
SRL16's in dynamic shift mode, dual port RAM etc. Finally, even on a
design that is strictly RTL, differences in FPGA structures and features
from different vendors make a design that is efficient in one become a
pig in the other. For example, the older Altera 10K and 20K families,
when used for arithmetic functions broke the logic into a pair of 3
luts, which meant that arithmetic in a single level was restricted to a
basic add, where Xillinx of the same vintage retained the 4 input
function for arithmetic. Xilinx carry chain structure has some quirks
that can force an arithmetic sturcture to two levels if not described
correctly, and the synthesizers have a hard time picking that out
(consider the case of an add followed by a mux: it can be done in one
level in xilinx, but the synths will not recognize that structure and
instead produce a design that uses two levels of logic). Often the
correct structure can be enforced, still in RTL, by breaking the
combinatorial function down and with judicious use of syn_keeps. Other
times, it is just easier to instance a component built up from primitives.
I've developed a rather extensive library of components, including
adders, registers as well as more complicated blocks like FFT's and
everything in between. This library is mostly instanced primitives with
placement attributes on it that save a tremendous amount of time in
floorplanning. By using this library, I also avoid the pushing on a
rope syndrome that often happens in speed critical rtl. In the case of
the Bresenham circuits, I'd have to look, but I think I had some srl16s
in there with dynamic addressing, as well as some placed adders.
Yes, in the optimum world, RTL only code would be the best way, but the
fact remains that synthesis is still far from perfect, especially when
it comes to dealing with the increasingly heterogenous arrays that are
today's FPGAs. For example, the DSP48 slice in Xilinx is only inferred
in it's basic form by the synthesis tools. You leave a heck of a lot of
performance on the table by not taking time to understand and force the
ideal implementation of circuits using them. Another V4 gotcha that the
synths don't seem to notice is that the SR pins on the flip-flops are
deadly slow. if you aren't careful about your coding, the synthesizer
gets cute using the resets in order to reduce the logic complexity at an
entirely unacceptable hit in performance.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84786A LUT is usually simply a SRAM in most FPGAs and the 4 inputs act as an address to give a single bit output. Synthesiser tools and backend tools convert your logic into an address and data mapping for your LUT logic and this gets loaded at configuration. Your inputs don't actually pass the input through the LUT like in an analogue mux but directly cause a relevant output to be generated. You can use only 3 inputs by either mirroring data with the 4th input having no effect or alternatively tying the spare input to a known value and building a 4 input function. Usually this is all handled by the tools for you and is only of concern if you start instantiating raw LUTs in your VHDL or Verilog. John Adair Enterpoint Ltd. - Home of MINI-CAN. Low Cost PCI Development Board. http://www.enterpoint.co.uk "CODE_IS_BAD" <Puneetsingh81@gmail.com> wrote in message news:1117172585.821372.94670@f14g2000cwb.googlegroups.com... > hi all, > can anyone explain me how only one 2:1 mux is implemented in a 4-i/p > look up table? Is it just the implementation of function O = A(/S) + > B.S > If this is the case then this implementation uses 3 i/p and only 8*1 > locations. I don't know what i am guessing is correct. Please help if i > am wrong. >Article: 84787
Thanks a lot Greg, though your answer comes a bit late since my client
has already accepted the product and decided to use an external PLL for
his application.
I am not a jitter specialist and I don't know exactly what peak-to-peak
and RMS jitter are.
Let's try to clarify a bit:
- RMS jitter is a mean value (probably something like the square root
of the sum of the squares of the differences between tehoretical period
and actual period)
- p2p jitter is the maximum difference between theoretical period and
actual period.
Am i right?
What we did is compare the 60MHz input with the 48MHz output (sync'ing
the scope was a bit of a nightmare but that's another matter :o) and we
saw looked a bit like that:
(look with a fixed-size font)
_______ _______
60MHz ___/ \_______/ \
_________ ____
48MHz __/ \\________//
Nicolas
Article: 84788Hi Jonathan, I just read the material about Flancter circuit. Since the short pulse is shorter than one clock cycle, it is impossible to connect the short pulse to SET_CE and RESET_CE. So I have to connect the short pulse to SET_CLK, and the system clock to RESET_CLK. Is this right? Thanks!Article: 84789
Hi... I wonder how to do timing simulation using ModelSim for Xilinx FPGA. I have finished functional simulation for my VHDL code. If somebody knows it, please let me know.Article: 84790
Thanks all for responses. In article <1117127547.037328.263220@g44g2000cwa.googlegroups.com>, wooster.berty@gmail.com says... > Manchester is generally speaking used only in Fiber and not over > cupper. > 100M from Mac to Phy let say using 25Mx4 > Than in the phy after the 4/5 bit encoding 25x4/5 =125 > Than after MLT3 125x2/3= ~83M. I see, so MLT3 is used for copper Ethernet. > Never the less as mention before you don't need to worry about the > encoding and frequency over the line as this is the phy responsibility > and not the MAC. Ok, understood, but I would like to understand how a PHY might decode 100 Mbps Ethernet copper (MLT3) and how it might handle Manchester data. This is more for my understanding than anything else. > However in my opinion a better way to sync if you have the option to do > it is to look for change. > The interesting thing in Manchester is that when you get something like > ....001 you have no clue about the past but you know for sure that the > last 2 digit is due to 0 in the source and you are now in sync. > Similar ......110 tell you the last two digits are due to 1 in the > source and you are now in sync. Can you explain the Manchester decoding a bit more? So if the source sends all 1's or all 0's as a sync. frame, then how exactly do you extract the clock/data? I'm assuming the local circuit is running at the data rate; i.e. if I have 100 Mbps serial stream, then I have a 100 MHz clock available. So I would clock a shift register at 100 MHz and RX the 100 MBps stream (assuming it is Manchester encoded) and study the 1's and 0's to figure out how close I am to matching? (I think 12 Mbps USB uses a 48 MHz clock for DPLLing, so I guess you have to oversample)? Thanks all. H.Article: 84791
Antti Lukats wrote: > Hi > > just a little thing: starting from 7.1 ISE abondoned the use of plain text > project files, the new project files with .ISE extension are PKZIP > compressed - that can cause an additional problem if ISE is not closed > correctly as the ZIP archive could corrupted rendering it totally useless, > ISE will refuse to open and use it. And there is no recovery, the project > must be done from scratch - well its only the project file and can mostly > easily be recreated, still if your computer (or ISE on it) can occasionally > be doing crash, then I would say its a good idea to make manual backups of > the ISE project files. Just in case. > > For me it was real surprise, I was working on project, configured the FPGA > 'live' on the PCI board in the same computer, re-enabled the BARs run a test > on that thing, it did froze the PC, well seing that the ISE project was > corrupted after that was a bit scary. Well that the price you pay if you > dont use plain text files, I really dont see any advantage that ISE now uses > compressed project files that can not be manually edited, in previous > releases I often did edit the .NPL files in text editor, thats not possible > any more Sounds more like they goofed on when to open/close, more than the Zip. If it is zipped, and properly closed when not changed, you should be able to unzip outside ISE, and even edit - and if it was well behaved like any text editor, it would say "Project file has changed outside ISE - reload?" I'd raise it as a web case, and tell them to fix the open/close handling. [ but their list is getting quite long ....] -jgArticle: 84792
I have got compact flash to configure virtex4 on ml403 board. When I want to use it for my systemACE file to be downloaded its not working but it works nicely whne I configure the device with demo ACE files which i got along with board. can anyone help me out to use CF for configuration.Article: 84793
hi can anyone expalin me how to use compact flah to configure the device with my design bit file. I tried to convert .bit to .ace using iMPACT and copied to CF and tried to configure the device but it did not work and only shows Err led on with red on the board. please help me..Article: 84794
The flying leads on my Xilinx Parallel Cable III won't last much longer (they are starting to break at the 9-way housing), and I haven't been able to find a replacement set. Harwin M20 crimp terminals and housings are very similar to the original ones and I have found that with some care, the cheap ratchet crimp tool I got for Molex terminals can be used for crimping the Harwin terminals. My assembly will be more convenient than the original Xilinx one, as I'll put all six terminals into a single 6-way housing. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 84795
You have a common problem. I bought myself some new ones which I think will be compatible with my Parallel Cable III. I bought them as spares for my newer cables. Xilinx part code "HWFLYLEADS". Expensive for what they are but a minimum hassle solution. The new lead sets have better contact and strain relief than some of the older ones. It appears to be a crimped contact with extend heatshrink as strain relief and as a side benefit I can even get them onto the 2mm JTAG header we use on our MINI-CAN product. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Leon Heller" <leon.heller@dsl.pipex.com> wrote in message news:BJCdncU4QJp0agvfRVnyjA@pipex.net... > The flying leads on my Xilinx Parallel Cable III won't last much longer > (they are starting to break at the 9-way housing), and I haven't been able > to find a replacement set. Harwin M20 crimp terminals and housings are > very similar to the original ones and I have found that with some care, > the cheap ratchet crimp tool I got for Molex terminals can be used for > crimping the Harwin terminals. My assembly will be more convenient than > the original Xilinx one, as I'll put all six terminals into a single 6-way > housing. > > Leon > -- > Leon Heller, G1HSM > http://www.geocities.com/leon_heller >Article: 84796
> corrupted after that was a bit scary. Well that the price you pay if you > dont use plain text files, I really dont see any advantage that ISE now uses > compressed project files that can not be manually edited, in previous > releases I often did edit the .NPL files in text editor, thats not possible > any more > I have to agree on that point. It's very annoying that the project file is not in plain text anymore. I'm used to change project setting (a.g. add VHDL files) in an editor. Usually tools add files with absolute paths (that's the case in Quartus, I don't know in ISE). Than you can't transfer your project to a different directory/machine/user. When adding the files manually in the project file you can use relativ paths and you're fine. MartinArticle: 84797
icegray wrote:
> I want to implement ethernet but I have no exprience about ethernet.
First of all: why do you want to implement an Ethernet controller
inside an FPGA chip if there are many specialized chips on the
market? FPGA-based peripherals are very expensive (compared
to their specialized counterparts), so generally it's not a good idea
to buy a larger FPGA chip just to insert popular peripherals (Ethernet,
USB etc.) into it. FPGAs are good for reconfigurable circuits, high
speed datastream signal processing, driving specialized peripherals
(LCDs, CODECs, ADCs etc.), but not for reinventing the wheel. :-)
> What should i do?
Buy RTL8019 or CS8900 and forget about the problem?
Best regards
Piotr Wyderski
Article: 84798
icegray wrote:
> This is not fun If I can do it I'll earn money (I hope). I must make
> network for up to 100 devices and every device need 2.5Mbit/s so I
> think this is not simple.
Are you sure you really need Ethernet? Perhaps the
old good RS485 will do -- it is a lot easier and cheaper,
but its bandwidth is comparable to Ethernet's (i.e. 10Mbit/s).
Best regards
Piotr Wyderski
Article: 84799Martin Schoeberl wrote: > > corrupted after that was a bit scary. Well that the price you pay if you > > dont use plain text files, I really dont see any advantage that ISE now uses > > compressed project files that can not be manually edited, in previous > > releases I often did edit the .NPL files in text editor, thats not possible > > any more > > > I have to agree on that point. It's very annoying that the project file is > not in plain text anymore. I'm used to change project setting (a.g. add VHDL > files) in an editor. Usually tools add files with absolute paths (that's the > case in Quartus, I don't know in ISE). Than you can't transfer your project > to a different directory/machine/user. When adding the files manually in > the project file you can use relativ paths and you're fine. > > Martin I've heard too many horror stories about 7.1 to upgrade yet, and probably won't until I start to use Virtex 4. In 6.1 at least the project navigator uses relative paths to source files and also allows you to convert from absolute to relative paths.
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