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Messages from 84875

Article: 84875
Subject: generate systemACE file in EDK
From: kurapati77@gmail-dot-com.no-spam.invalid (kurapati)
Date: Tue, 31 May 2005 11:16:29 -0500
Links: << >>  << T >>  << A >>
Hi Ed,

I don't have parallel 4 cable instead using compact flash to configure
the device on ml403 board.  here I want to generate system ACE file in
EDK. Is that possible to generate ACE file without connecting to the
board with JTAG cable. Can u tell me what r the changes I must do in
genace.tcl script for ml403 board.

Even I read "System Initialisation and Download" chapter 11 in EDK
documentation and I tried myself to make some changes in xmd options
but I was not successful.

Hope u will give some good hint..

regards


Article: 84876
Subject: Problem with Synplify 7.7.1, startup block vs clock input
From: bigboytemp@hotmail-dot-com.no-spam.invalid (Big Boy)
Date: Tue, 31 May 2005 11:16:29 -0500
Links: << >>  << T >>  << A >>
Hello

I have a design (Verilog) and using a STARTUP_SPARTAN3 instance.  On
the instance, I send the clock signal and reset signal.  The clock
and reset signals are comming directly from the top-level clock and
reset pins.

That is, I have code looking like:


module counter_7seg(reset, clk, segLow, segHigh); //Top-level
module
   input        reset;
   input        clk;
   output [6:0] segHigh, segLow;

[...]   

   STARTUP_SPARTAN3 Startup(.CLK(clk),
.GSR(reset));

[...]


When I synthesize, with Synplify 7.7.1, and I verify the technology
schematic, it get synthesize as

[code:1:7e7d529f83]
          IBUF
reset------|>---------------+
                            |
        IBUFG      BUFG     |
        +----+     +----+   |
clk ----|-|>-|--+--|-|>-|------... (global clock
network)
        +----+  |  +----+   |
                |           |  STARTUP_SPARTAN3
                |           | +----------------+
                |           +-|GSR             |
                |             |                |
                +-------------|CLK             |
                              |                |
                            0-|GTS             |
                              +----------------+
[/code:1:7e7d529f83]

As you can see, local routing is used from the clock pin to the
startup module, while the rest of the design use global clock
network

I do the same thing with XST (in ISE 7.1i), and it route using global
clock line as input of the startup block.

I tried many ways and can not come to correct result in Synplify.

help!


Article: 84877
Subject: Re: FPGA Boards
From: Jorge <jorgetrabal@hotmail.com>
Date: Tue, 31 May 2005 09:25:33 -0700
Links: << >>  << T >>  << A >>
Hi,

I am trying to implement the PCI Brige in a Spartan II board (XC2S200). The problem is when I try to program the board I got that error:

ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.

I read from the manual that I need to associate the ISO PROM with a dummy.mcs file or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM. I don't know how to that to resolved my problem. If someone know how to resolve the problem please help me.

Thank you Jorge

Article: 84878
Subject: Re: What is a typical job scope when FPGAs are involved?
From: "JJ" <johnjakson@yahoo.com>
Date: 31 May 2005 09:27:49 -0700
Links: << >>  << T >>  << A >>
Dave wrote:
> Hi all,
>
> I am looking at some FPGA related jobs and am finding that very few involve
> 100% FPGA design.
>
> Typically I am finding that current jobs will involve additional activities
> such as DSP processor programming as well.
>
> I was wondering if you guys would be able to comment on whether your jobs or
> jobs of people you know involve mostly (or 100%) FPGA design?  Or are you
> required to do other stuff as well?
>
> Many thanks for your time,
>
> Dave


If you are doing DSP, I would expect a reasonable knowledge of DSP
either programming DSP processors and or converting algorithms to HW
flow.

If you are working on any bus interface, that would likely mean knowing
that bus pretty well and use of analyzers etc, and pretty likely
writing a driver esp if usb,pci.

If you are doing DRAM interface same thing (but no SW driver there).

And if you are crazy enough to do some projects like a cpu design, you
also get to write the compiler too and the cpu ISA simulators and the
memory interface and..., but thats pretty unusual, but atleast a few
have done this.

I don't think you can do FPGA design just because you have digital HW
knowledge, there has to be an application area and knowledge base. Mind
you if you can complete a project in 1 area, it should help when moving
to an entirely different application, just more book reading along the
way.

And the usual drudgery of verification, testing, documentation, endless
(& pointless) meetings, custommer interface will be there too.

my 2c

johnjakson at usa dot com
transputer2 at yahoo dot com


Article: 84879
Subject: Re: Problems with SDRAM and Altera Cyclone
From: "GMM50" <george.martin@att.net>
Date: 31 May 2005 09:31:58 -0700
Links: << >>  << T >>  << A >>
Hello:

I'm using 2 Micron SDRAMs     MT48LC16M16A2TG-75IT

This is one of the only components that came up at the start without
any coaxing on my part.

However I'm using Quartus 4.1  When I got a copy of 4.2 it seemed to
drop buuilt in support for SDRAMs.  I've got another copy of 4.2 and
looks like it's back.  I'm on a deadline so I won't change anything for
a bit.

gm


Article: 84880
Subject: JTAG Programming Problem
From: Jorge <jorgetrabal@hotmail.com>
Date: Tue, 31 May 2005 09:37:02 -0700
Links: << >>  << T >>  << A >>
Hi,

I am trying to implement the PCI Brige in a Spartan II board (XC2S200). The problem is when I try to program the board I got that error:

ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.

I read from the manual that I need to associate the ISO PROM with a dummy.mcs file or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM. I don't know how to that to resolved my problem. If someone know how to resolve the problem please help me.

Thank you Jorge

Article: 84881
Subject: Re: generate systemACE file in EDK
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Tue, 31 May 2005 09:48:41 -0700
Links: << >>  << T >>  << A >>
kurapati wrote:
> Hi Ed,
> 
> I don't have parallel 4 cable instead using compact flash to configure
> the device on ml403 board.  here I want to generate system ACE file in
> EDK. Is that possible to generate ACE file without connecting to the
> board with JTAG cable. Can u tell me what r the changes I must do in
> genace.tcl script for ml403 board.
> 
> Even I read "System Initialisation and Download" chapter 11 in EDK
> documentation and I tried myself to make some changes in xmd options
> but I was not successful.
> 
> Hope u will give some good hint..
> 
> regards
> 

There is no need to connect a PC-4 cable to the ML403 to create
a System ACE file.  I went back and looked at some of your previous
posts and it's not clear which software version you are using and
exactly what steps you have taken.  I would suggest that you initially
follow the steps on page 26 of the "ML40x Getting Started Tutorial"
http://www.xilinx.com/bvdocs/userguides/ug083.pdf

There are several reasons why your ACE file doesn't work. These
are prioritized in the order that I think is likely.

1) You didn't include everything in the JTAG chain when you
    created the ACE file in iMPACT. See page 33 of the "ML40x User Guide"
    http://www.xilinx.com/bvdocs/userguides/ug080.pdf

2) The file name or directory that you selected was not in the 8.3 format
    I know that this is old, but System ACE only has a tiny microcontroller
    in it and we created this device back in 6 years ago.

3) You forgot to update to xilinx.sys file to point to the correct
    dir location of the new ACE file.

4) The format of the CF card is not compatible with System ACE.
    http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14456

Ed

Article: 84882
Subject: Re: Timing summary
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Tue, 31 May 2005 13:39:09 -0400
Links: << >>  << T >>  << A >>
Use Timing Analyzer, it's good to see the critical path. Make sure also that 
I/O flipflops are used.
but there is nothing wrong with this report, unless you made a copy-paste 
mistake that dramatically changes logic.
if you add 5-bit counter and 4 "if" statements, it could be mapped into more 
than one slice.
Plus if the design is consuming too much (80+ percent or so), routing can be 
using LUTs.

Hope this helps.

Vladislav


"Kalle" <tebe7689@student.uu.se> wrote in message 
news:ee8e967.-1@webx.sUN8CHnE...
> Hi, I'm implementing a ddr-fifo buffer and when viewing the synthesis 
> report on the ddr-fifo buffer by itself the timing summary is:
>
> --------------- Speed Grade: -10
>
> Minimum period: 6.976ns (Maximum Frequency: 143.343MHz) Minimum input 
> arrival time before clock: 6.546ns Maximum output required time after 
> clock: 4.543ns Maximum combinational path delay: No path found
>
> When adding a 5 bit counter and 4 if statements that changes the values of 
> wr_en and rd_en on the ddr-fifo the timing summary is:
>
> --------------- Speed Grade: -10
>
> Minimum period: 13.964ns (Maximum Frequency: 71.611MHz) Minimum input 
> arrival time before clock: 6.546ns Maximum output required time after 
> clock: 4.543ns Maximum combinational path delay: No path found
>
> The maximum frequency is about half of the original!
>
> Is this due to the fact that it take some time before the wr_en and rd_en 
> pins in the fifo is effective? So there might be some error on the first 
> and last bits of data.
>
> For me it's okay that the head and tail is corrupt, it is the bits in 
> beteween that are important to my project.
>
> Could I then forget about this timing summary and run the system at the 
> higher clock frequency?
>
> Cheers 



Article: 84883
Subject: Re: JTAG Programming Problem
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Tue, 31 May 2005 13:42:54 -0400
Links: << >>  << T >>  << A >>
Jorge,

I had this error once. If the ID code has many '1's, and this is the first 
time you try programming the board,
this could be a board / signal integrity problem.
Hope this helps.

Vladislav

"Jorge" <jorgetrabal@hotmail.com> wrote in message 
news:ee8e985.-1@webx.sUN8CHnE...
> Hi,
>
> I am trying to implement the PCI Brige in a Spartan II board (XC2S200). 
> The problem is when I try to program the board I got that error:
>
> ERROR:iMPACT:583 - '1': The idcode read from the device does not match the 
> idcode in the bsdl File.
>
> I read from the manual that I need to associate the ISO PROM with a 
> dummy.mcs file or a .bsd file to allow the JTAG programming software to 
> pass data through the ISP PROM. I don't know how to that to resolved my 
> problem. If someone know how to resolve the problem please help me.
>
> Thank you Jorge 



Article: 84884
Subject: Re: Xilinx ISE 6.1i - Fatal Error
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Tue, 31 May 2005 13:46:14 -0400
Links: << >>  << T >>  << A >>
Try getting the most updated version of the tool.
Usually most of the errors of this kind from the previous versions are fixed 
in the newest one.
Then if the problem still persists, call Xilinx. Nothing else you can do.

One other thing: if you did this with timing driven packing and placement 
option turned on, turn it off and try again.

V

"tvar_vlsi" <tvarvlsi@gmail.com> wrote in message 
news:1117452095.082732.114780@g49g2000cwa.googlegroups.com...
> Haiii all,While I have updated my project directories from ISE webpack
> 5.1 to ISE 6.1i , the following error occurs during MAP & there is no
> such error for new projects created in 6.1i.Please provide me the root
> cause & solution for the issue. Thank you.
>
> ERROR: FATAL_ERROR:Portability:PortDynamicLib.c:278:1.17 - dll open of
> library <C:/Xilinx_WebPACK/xilinx/bin/nt/libxildr.dll> failed due to an
> unknown reason. Process will terminate.
> 



Article: 84885
Subject: Xilinx DDR output registers
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 31 May 2005 17:52:07 GMT
Links: << >>  << T >>  << A >>
There's been a little side discussion about the Xilinx IOB cell DDR output
registers.  The common idea of a DDR output register is A) the use of two
registers clocked off different phases of the same clock with a mux
controlled by the clock so the register just updated goes out.

It was my recollection from dicussions here that B) the DDR output register
didn't have a physical mux but was effectively a two-clock register.

Is it A or B ?

There are 2 clock inputs for the two registers in the IOB schematic
representation.  What will happen when 100 MHz is applied on one clock and a
50 MHz clock with the rising edge coincident with the 100 MHz falling edge
applied to the other clock?  This is not true DDR but the edges are aligned
to DDR transition locations.

Will we see confused operation where the mux is controlled by clock1 or
clock2 and the different rates produce undefined behavior or will the values
be updated with the respective rising edges independent of the logic level
of either clock?


I've been considering using two BUFGMUX gated clocks to produce outputs from
two sections of my design through the DDR register based on the dual-clock
register.  If there is a real mux, this operation would be confused without
additional DDR implementation understanding.  Is there a definitive word on
these registers?


As an aside, I've seen Syplify will now infer DDR registers if coded
properly but their coding template includes the clock-controlled mux rather
than a dual-edge register.  Conceptually the muxed register is reasonable
but a silicon implementation would either need propagation control for the
mux to switch to the just-updated register after the clock-to-out time or
would need a transition control such that a low/high/high sequence wouldn't
glitch low between the highs or vice-versa.  I put together logic a decade
ago to bridge this gap in a discreete ECL solution that WAS glitching before
applying the bridge logic.



Article: 84886
Subject: Re: What is a typical job scope when FPGAs are involved?
From: Rene Tschaggelar <none@none.net>
Date: Tue, 31 May 2005 20:13:11 +0200
Links: << >>  << T >>  << A >>
Dave wrote:

> Hi all,
> 
> I am looking at some FPGA related jobs and am finding that very few involve 
> 100% FPGA design.
> 
> Typically I am finding that current jobs will involve additional activities 
> such as DSP processor programming as well.
> 
> I was wondering if you guys would be able to comment on whether your jobs or 
> jobs of people you know involve mostly (or 100%) FPGA design?  Or are you 
> required to do other stuff as well?
> 
> Many thanks for your time,

Why do you want to stick to FPGA ?
You won't make a complete product anyway.
What is wrong with doing what is connected
to it too ?
There was recently a one-man company here
advertizing that he's doing VHDL and Verilog,
none else. No pcb, no software on no cpu, nothing.
Yes, if that is sufficient for a product...

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 84887
Subject: Re: What is a typical job scope when FPGAs are involved?
From: Mac <foo@bar.net>
Date: Tue, 31 May 2005 18:43:04 GMT
Links: << >>  << T >>  << A >>
On Tue, 31 May 2005 17:56:58 +0200, Dave wrote:

> Hi all,
> 
> I am looking at some FPGA related jobs and am finding that very few involve 
> 100% FPGA design.
> 
> Typically I am finding that current jobs will involve additional activities 
> such as DSP processor programming as well.
> 
> I was wondering if you guys would be able to comment on whether your jobs or 
> jobs of people you know involve mostly (or 100%) FPGA design?  Or are you 
> required to do other stuff as well?
> 
> Many thanks for your time,
> 
> Dave

The larger the company is that you work for, the more specialized you can
potentially be.

In a small company, there is no way that doing "just FPGA design" will be
enough. You will probably need to design the whole board the FPGA goes
into. You may have to lay the board out, too, or at least deal with the
people who DO lay it out. (Of course, if it is a small company who does
FPGA design by contract, that is different. I'm envisioning a small
company which produces some kind of end-product which is not just IP.)

And you will then have to bring those boards up and test or characterize
them and so on.

In a large company, it may be possible to spend most of your time doing
FPGA design. But even then, much of the design work will be writing a
design spec, interfacing with board designers, as well as marketing and
test people, and so on.

IMO if you think you can spend more than half your time, on average,
writing code and running simulations, you are probably out of line with
reality. Of course, YMMV. And I have more experience working with small
companies than big ones, so my experience may be skewed.

--Mac


Article: 84888
Subject: Re: StateCAD 7.1i is broken?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 31 May 2005 11:43:54 -0700
Links: << >>  << T >>  << A >>
Bob Perlman wrote:

> I've never been terribly enthusiastic about the tool,
> mostly because coding an FSM in Verilog just isn't that hard.

I agree.
Consider simulation waveforms
to check and visualize the state transitions.

> But there is one significant problem: the Verilog code emitted by
> StateCAD is wrong.

> I'm probably going to write a Python script to correct the emitted
> code. 

That's fine, if you enjoy the exercise,
but consider using a text file as the
source document. The fewer tools in
the design loop, the better.

  Anyone have a better solution?

Consider using a single synchronous always block
for the entire module like this:

http://www.designabstraction.co.uk/EXAMPLE/HTML/verilog.htm

       -- Mike Treseler

Article: 84889
Subject: Altera NIOS2 50.0 SOPC periphals broken???
From: Jedi <me@aol.com>
Date: Tue, 31 May 2005 18:44:31 GMT
Links: << >>  << T >>  << A >>
Trying to run some small system with NIOS2 and timer/uart periphal...

1. Problem...regardless what I set for the UART as fixed BAUD it always
    stays at 115200 baud...

2. Adding a timer with all features enabled and 10msec period
    it doesn't allow me to start/stop and to modify period time...


So I assume other SOPC components are broken as well in NIOS2 5.0?


/jedi

Article: 84890
Subject: How fast multiplier in VirtexE?
From: ccon67@netscape.net
Date: 31 May 2005 11:57:18 -0700
Links: << >>  << T >>  << A >>
I am using CoreGen Multiplier (target Virtex-300E speed -7), I have
strugled to make it runs at about 6.5ns, and that's it.  What I want is
... faster (6ns is my goal), but it looks like I've hit the wall.  The
question is how do I now it's the limit yet?  Do I need to go to faster
speed grade or bigger device?

Notes: I use the dynamic constant multiplier (CoreGen V1.0), this one
run faster than the Multiplier V3.0..), all I need is the dynamic
constant multiplier, the constant is reloaded every 10uS or so.
Timming errors are reported within the multiplier, all outside paths
are okay.  

Thank you for reading,


Article: 84891
Subject: regional clk to dcm? possible or not?
From: "Yttrium" <Yttrium@pandora.be>
Date: Tue, 31 May 2005 19:05:20 GMT
Links: << >>  << T >>  << A >>
Hey,

I have to start a V4 design and am looking through a datasheet and i was
wondering if you can connect a regional clk to a DCM (if in a nearby
regional clk domain)? or even through logic?

kind regards,

Y



Article: 84892
Subject: Re: Altera NIOS2 50.0 SOPC periphals broken???
From: Jedi <me@aol.com>
Date: Tue, 31 May 2005 19:13:02 GMT
Links: << >>  << T >>  << A >>
Jedi wrote:
> Trying to run some small system with NIOS2 and timer/uart periphal...
> 
> 1. Problem...regardless what I set for the UART as fixed BAUD it always
>    stays at 115200 baud...
> 
> 2. Adding a timer with all features enabled and 10msec period
>    it doesn't allow me to start/stop and to modify period time...
> 
> 
> So I assume other SOPC components are broken as well in NIOS2 5.0?

Okay..UART works when I change baudrate...stupid EPCS programming over 
JTAG doesn't get automatically updated (o;

But timer still same...


/jedi


Article: 84893
Subject: Implementing sin function in fpga
From: pvnguyen@mail.ucf.edu
Date: 31 May 2005 12:13:31 -0700
Links: << >>  << T >>  << A >>
I am attempting to implement a sine function using cordic method.  I
can't figure out how to reduce an arbitrary angle to -90 and 90 deg.
For example, if an input is 390 deg, it should be reduced to 30 deg
before passing to the cordic method.  What algorithm can i use to
efficiently reduce a arbitrary angle down to -90 and 90 deg.

Any help would be much appreciated

Thanks
pvn


Article: 84894
Subject: Re: FPGA Boards
From: "Gabor" <gabor@alacron.com>
Date: 31 May 2005 12:30:15 -0700
Links: << >>  << T >>  << A >>


Jorge wrote:
> Hi,
>
> I am trying to implement the PCI Brige in a Spartan II board (XC2S200). The problem is when I try to program the board I got that error:
>
> ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.
>
> I read from the manual that I need to associate the ISO PROM with a dummy.mcs file or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM. I don't know how to that to resolved my problem. If someone know how to resolve the problem please help me.
>
> Thank you Jorge

When I've seen this error it almost always was due to a connection
problem
and nothing to do with bsdl files.  Make sure all of your JTAG
connections
are properly connected (TDI disconnected often causes this problem) and
that
the programming pod has the proper voltage.  For the Xilinx parallel
cable
4, you should have a green light on the pod.

Also sometimes you'll see this if one of the devices in a chain is not
getting its core power (Vcc int).  Try to do IDcode looping to test the
connections.


Article: 84895
Subject: Re: FPGA Boards
From: "maddy" <ghuruk@gmail.com>
Date: 31 May 2005 12:30:17 -0700
Links: << >>  << T >>  << A >>
I believe that you should get an updated BSDL file for the device that
is failing the Scan Path Verify test. Depending on the BScan software
you use, you might be able to change the expected IDCODE value of the
device so that you can pass the test. Again, getting the latest bsdl
file from the vendor is advisable.

Thanks,
  Ghuru

Jorge wrote:
> Hi,
>
> I am trying to implement the PCI Brige in a Spartan II board (XC2S200). The problem is when I try to program the board I got that error:
>
> ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.
>
> I read from the manual that I need to associate the ISO PROM with a dummy.mcs file or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM. I don't know how to that to resolved my problem. If someone know how to resolve the problem please help me.
> 
> Thank you Jorge


Article: 84896
Subject: Re: Implementing sin function in fpga
From: "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl>
Date: Tue, 31 May 2005 21:52:00 +0200
Links: << >>  << T >>  << A >>
pvnguyen@mail.ucf.edu wrote:

>I am attempting to implement a sine function using cordic method. 

Forget about CORDIC, computing 17-bit accurate sin(x) using linear
interpolation needs much smaller hardware and is conceptually simpler. 
It could be as fast as your RAM is -- my implementation of this method
at a speed grade 6 Cyclone generates up to 256*10^6 sin(x) values
per second.

    Best regards
    Piotr Wyderski


Article: 84897
Subject: Re: Implementing sin function in fpga
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 31 May 2005 19:57:59 GMT
Links: << >>  << T >>  << A >>
Rather than running the CORDIC off degrees, run it off a phase value from
0-1 corresponding to 0-360 degrees.
Just multiply an 18-bit input by 2^18/360 and use only the bottom 18 bits
from the multiply, effectively truncating the integer portion of a
fixed-decimal number.  The 18 bits are (phase/360 - int(phase/360)) * 2^18
or using a less popular notation frac(phase/360)*2^18.


<pvnguyen@mail.ucf.edu> wrote in message
news:1117566811.817537.138790@g14g2000cwa.googlegroups.com...
> I am attempting to implement a sine function using cordic method.  I
> can't figure out how to reduce an arbitrary angle to -90 and 90 deg.
> For example, if an input is 390 deg, it should be reduced to 30 deg
> before passing to the cordic method.  What algorithm can i use to
> efficiently reduce a arbitrary angle down to -90 and 90 deg.
>
> Any help would be much appreciated
>
> Thanks
> pvn



Article: 84898
Subject: Re: Xilinx DDR output registers
From: "Gabor" <gabor@alacron.com>
Date: 31 May 2005 13:07:05 -0700
Links: << >>  << T >>  << A >>
The Xilinx design actually uses an XOR gate rather than a mux on
the outputs of two independent flip-flops.  The scenario you suggest
with two clocks should work as long as there is a minimum spacing
met between the edge to one flip-flop and the edge to the other.

This has to do with the D in the flip-flops which uses the
Q output of the opposite flip-flop.  This only works if the
opposite flip-flop is not changing at the same time.

The D to each flip-flop looks like:
D1_to_flop = Q2 XOR D1_in
D2_to_flop = Q1 XOR D2_in
Q = Q1 XOR Q2

John_H wrote:
> There's been a little side discussion about the Xilinx IOB cell DDR output
> registers.  The common idea of a DDR output register is A) the use of two
> registers clocked off different phases of the same clock with a mux
> controlled by the clock so the register just updated goes out.
>
> It was my recollection from dicussions here that B) the DDR output register
> didn't have a physical mux but was effectively a two-clock register.
>
> Is it A or B ?
>
> There are 2 clock inputs for the two registers in the IOB schematic
> representation.  What will happen when 100 MHz is applied on one clock and a
> 50 MHz clock with the rising edge coincident with the 100 MHz falling edge
> applied to the other clock?  This is not true DDR but the edges are aligned
> to DDR transition locations.
>
> Will we see confused operation where the mux is controlled by clock1 or
> clock2 and the different rates produce undefined behavior or will the values
> be updated with the respective rising edges independent of the logic level
> of either clock?
>
>
> I've been considering using two BUFGMUX gated clocks to produce outputs from
> two sections of my design through the DDR register based on the dual-clock
> register.  If there is a real mux, this operation would be confused without
> additional DDR implementation understanding.  Is there a definitive word on
> these registers?
>
>
> As an aside, I've seen Syplify will now infer DDR registers if coded
> properly but their coding template includes the clock-controlled mux rather
> than a dual-edge register.  Conceptually the muxed register is reasonable
> but a silicon implementation would either need propagation control for the
> mux to switch to the just-updated register after the clock-to-out time or
> would need a transition control such that a low/high/high sequence wouldn't
> glitch low between the highs or vice-versa.  I put together logic a decade
> ago to bridge this gap in a discreete ECL solution that WAS glitching before
> applying the bridge logic.


Article: 84899
Subject: Re: Virtex4 running at 360Mhz DDR
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 31 May 2005 14:08:17 -0700
Links: << >>  << T >>  << A >>
Paul,
Many thanks!
Syms.





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