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Kolja Sulimma wrote: > Jim Granville schrieb: > >>This news is interesting >> >>http://www.eet.com/news/latest/showArticle.jhtml?articleID=187200783&pgno=2 >> >> You do need a hype filter when reading this, and many claims are >>extropolation-gone-wrong, but the base idea already exists in ring >>osc designs inside FPGA now. >> >> Seems ( with the right tools ) you could extend this inside a FPGA, by >>creating a large physical ring (long routes), with the sprinkled >>buffers. The physical delays would reduce the process variations in the >>clock, and you get the phase taps 'for free'. >> - but the tools _will_ need to co-operate :) >> >> We have done this inside CPLDs, and get appx 1.3ns granularity. >> >>With FPGAs the buffer delays are much lower, and the routing >>can be made to dominate. >> >> Sounds like a project for Antti :) > > > No. The article is not talking about chained buffers for high timing > resolution. Such a setup would still charge the clock lines from VDD and > discharge to GND for each clock cycle. > > They are really talking about sending a wave around a transmission line. Correct - see my comment on using the routes inside a FPGA for this. > Standing wave clocking is an exotic but established technique in PCB > design. At high frequencies you can use it inside ICs. > A physical wave uses the same charge again and again, only resistive and > EMI losses need to be refreshed by buffers PARALLEL to the transmission > line. yes, Parallel drive might test the FPGA tools some more :) Series drive would be a compromise, where the physical delay dominates the gate delay. With each generation, the gate delays shrink faster than the physical delays. -jgArticle: 101976
Hi newsgroup, I have observed a strange behaviour in our VHDL design: One signal goes low and stays low (133MHz clock domain)(No Reset case). That flag is synchronised with one FF into a 125MHz clock domain where a FSM is running. The flag (flag=3D'0') is checked in one of the states of the FSM. When using one FF for synchronization the circuit shows strange behaviour, when using two FFs it works fine. I mean the flag does not show much activity, it becomes high or low and remains stable. So why should one FF not be sufficient for synchronization ? Any ideas ? Rgds Andr=E9Article: 101977
Peter Alfke <peter@xilinx.com> wrote: >Xilinx gives complete data on thermal resistance with and without >heatsink and airflow. >We cannot give blanket data for power consumption, because it depends >on the aggregate frequency times capacitance product of every node >(assuming the same Vcc for all of them). >That is a problem shared by all programmable devices, but not shared by >ASICs and ASSPs, like microprocessors. They usually operate under >fairly well-specified internal conditions. FPGAs do not. Maybe one could hint it with power vs frequency diagrams under worstcase condition. And mathematical models of behaviour. And transient powerconsumption during worstcase scenarios.Article: 101978
<ALuPin@web.de> wrote in message news:1147163769.926529.291570@i39g2000cwa.googlegroups.com... > Hi newsgroup, > I have observed a strange behaviour in our VHDL design: > One signal goes low and stays low (133MHz clock domain)(No Reset case). > That flag > is synchronised with one FF into a 125MHz clock domain where > a FSM is running. The flag (flag='0') is checked in one of the states > of the FSM. > When using one FF for synchronization the circuit shows strange > behaviour, when > using two FFs it works fine. > I mean the flag does not show much activity, it becomes high or low and > remains stable. So why should one FF not be sufficient for > synchronization ? > Any ideas ? > Rgds > André Hi André, Use two FFs? :-) First, are you sure that the synthesis tool is implementing your domain crossing in just one FF? Similarly, are there any other domain crossing paths apart from the one you describe? Finally, here's a question, what's the total delay from the output of the synchronization FF to the next FFs in the FSM? Include setup time, routing and logic delays. Then remember that metastability will eat into this time. Also, what part is this in? Cheers, Syms.Article: 101979
Hi Symon, I use two FFs but I would like to understand the issue. We are using Lattice EC10-5F. There are no other domain crossing paths apart from the one I have described. The static timing analysis shows no warnings. The two clocks are unrelated so maybe the timing tool does not include that path in its calculation. But as I explained the flag goes low and stays low. The checking of the flag in the FSM is performed when the flag should be stable. Rgds Andr=E9Article: 101980
ALuPin@web.de (ALuPin@web.de) wrote: : Hi newsgroup, : I have observed a strange behaviour in our VHDL design: : One signal goes low and stays low (133MHz clock domain)(No Reset case). : That flag : is synchronised with one FF into a 125MHz clock domain where : a FSM is running. The flag (flag=3D'0') is checked in one of the states : of the FSM. : When using one FF for synchronization the circuit shows strange : behaviour, when : using two FFs it works fine. Is the one FF feeding more than one element? If so is it being duplicated by the Lattice tools? cdsArticle: 101981
Hello everybody ! I'm using an fpga card with a PCMCIA format connexion : The link : http://www.annapmicro.com/wildcard2.html I'm trying to have access to the signal "in vivo" to debug my system. Is it possible to use Xilinx Chipscope with this type of card ? Apparently, chipscope is waiting for a xilinx cable for debugging. My question is : is it possible to use chispcope with a PCMCIA interface .=2E.=20 Thanks T=F4FArticle: 101982
if you implement a LPT port emulation, Cable III emulation and BSCAN emulation IP into the PCMCIA card FPGA then, yes. otherwise no. AnttiArticle: 101983
Mike Harrison <mike@whitewing.co.uk> wrote: >Anyone know a UK stockist for the Xilinx/Digilent S3 board ? >(or anyone have a spare one - I only want the PCB) >Xilinx website seems to have discontinued it & only lists Cedar as UK disti & their website has >minimal info, and Avnet only list their own boards as far as I can see. >Digilent want $32 to ship USPS (which would cost $9 in a GP flat-rate envelope) They refuse to ship by other means .. ?Article: 101984
> <ALuPin@web.de> wrote in message > news:1147168239.611567.245280@e56g2000cwe.googlegroups.com... > Hi Symon, > The static timing analysis shows no warnings. The two clocks are > unrelated so maybe the timing tool does not include that path in its > calculation. > But as I explained the flag goes low and stays low. The checking > of the flag in the FSM is performed when the flag should be stable. Hi André, I understand, but what happens as the flag transistions from '1' to '0'? If the synchronization FF hasn't resolved in time for the checking circuit to do its work, you would be in trouble. Try constraining the time from the synchronization FF to the rest of the FFs to (say) 4ns and see if it gets better. BTW, are you using any falling edges in your destination clock domain? This might cut the time you have in two. Good luck! Syms.Article: 101985
respected knowledgious persons, i want to know about how to give clock to fpga.as i know do we give it by software or hard ware.also i wants to know that if we have 12 inputs each ofmore than 8 bits and and one input is of upto 16 bit,but our kit has only 4 to 8 switches so how we can check our design on board. thanks in advance.Article: 101986
> Hi Andr=E9, > I understand, but what happens as the flag transistions from '1' to '0'? = If > the synchronization FF hasn't resolved in time for the checking circuit to > do its work, you would be in trouble. Try constraining the time from the > synchronization FF to the rest of the FFs to (say) 4ns and see if it gets > better. BTW, are you using any falling edges in your destination clock > domain? This might cut the time you have in two. > Good luck! Syms. Hi Symon, we only use rising edges. I will try to play with some constraints to find out what the fitter is doing ... Rgds Andr=E9Article: 101987
Austin Lesea <austin@xilinx.com> asks many questions: Hi Austin, I can comment on these for you: > Why no use a RF link to send the data from sensors in the wheel to > somewhere else? > Indeed we do. > How the heck does one power a pcb in a wheel? With a battery(!) > Sounds like there are a > ton of problems to solve. Oooh yeah - we have fun testing these things! >How do you communicate with the wheel? > "Yo, wheel..."? > Like this (apologies for the enormous link!): http://www.trw.com/productsandtechnologies/main/0,1085,9_28105_28113_28114%5E4%5E28114%5E28114,00.html ahh, here's the same stuff, but shorter :-) http://www.entire-solution.com/products.htm Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 101988
>> A while back, Toms Hardware did a comparison of 3GHz P4s v the P100 1st >> pentium and all the in betweens and the plot was basically linear >Interesting. In fact I don't care about P4, as its architecture is one >big mistake, but linear speedup would be a shame for a Pentium 3... What in particular do you think is wrong with the P4 ..?Article: 101989
Hi, I'm trying to use statecad to build a state machine diagram. There is a vector condition for changing from one state to another. For example IF A = "1010" THEN next_sreg <= ... It seems that StateCAD doesn't recognise A= "1010" directly. Could you please tell me how to realize it? Thanks! JohnArticle: 101990
Perhaps - but three SMT capacitors, a bit of wire, and perhaps a bit of glue is a lot cheaper than rolling your own PWB. This would be a very simple board mod that almost any beginner could successfully manage, and it would be very effective. Cripes - I'm no expert at soldering, but even I've managed to modify boards in this way. Also, consider that this allows you to keep all your GPIO (which is rather limited on the S3E starter kit). If you are successful, you can still use the hirose connector for something else (like a video capture board) Lastly, not everyone can afford to roll their own PWB's with a true VGA DAC and connector. My wife would beat me silly if I even contemplated such a thing. So, if I had the board myself, it would either be roll the filters on the board, or live with 3-bit color.Article: 101991
"Peter Alfke" <alfke@sbcglobal.net> wrote: >I just looked it up: >14,000 rpm and a radius of 10 cm generates 20 000 g. These numbers are >not exotic at all. I have designed the controls for several small centrifuges, it takes about 100W to apply 22,000g to a bunch of small test tubes, most of that goes on stirring up the air around the rotor. I will probably be doing faster ones in the future getting towards 100,000g. --Article: 101992
Hi, I am wondering if there is anyone who has worked out a way to use ISE 8.1 projects with Makefiles to compile FPGA images. I am actually wondering if it would be possible to automatically generate a Makefile from the project file. Thank You, Sanka.Article: 101993
Xilinx offers power-estimation software that is getting better with each generation. I see no benefit in documenting perverse extreme situations that no realistic design would ever encounter. Peter AlfkeArticle: 101994
Martin, Thanks! Austin Martin Thompson wrote: > Austin Lesea <austin@xilinx.com> asks many questions: > > Hi Austin, > > I can comment on these for you: > > >>Why no use a RF link to send the data from sensors in the wheel to >>somewhere else? >> > > > Indeed we do. > > >>How the heck does one power a pcb in a wheel? > > > With a battery(!) > > >>Sounds like there are a >>ton of problems to solve. > > > Oooh yeah - we have fun testing these things! > > >>How do you communicate with the wheel? >>"Yo, wheel..."? >> > > > Like this (apologies for the enormous link!): > > http://www.trw.com/productsandtechnologies/main/0,1085,9_28105_28113_28114%5E4%5E28114%5E28114,00.html > ahh, here's the same stuff, but shorter :-) > http://www.entire-solution.com/products.htm > > Cheers, > Martin >Article: 101995
Is it the tire pressure you are going to meassure? In that case there are indirect ways of doing that: http://www.niradynamics.se/tpi.htm You don't need any sensors in the wheel, and thus no FPGA in, or communication with, the wheel either... /Johan Martin Thompson wrote: > > http://www.trw.com/productsandtechnologies/main/0,1085,9_28105_28113_28114%5E4%5E28114%5E28114,00.html > ahh, here's the same stuff, but shorter :-) > http://www.entire-solution.com/products.htm > > Cheers, > Martin > -- ----------------------------------------------- Johan Bernspĺng, xjohbex@xfoix.se Research engineer Swedish Defense Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 101996
The probable issue is metastability. Whenyou cross clock domains, you will inevitably encounter every conceivable timing relationship between the timing on D and CLK. In some cases, the flip-flop will not be able to decide its output level in the usual short time. This is called "metastable delay", and in can occasionally be a few ns. If your design cannot accomodate this extra delay, strange things will happen. Rule: Make sure that the output of the synchronizing flip-flop drives only one input, and that this path has the longest slack possible. The common solution is a second synchronizer flip-flop. There is lots of literature about metastability, I have written some of it myself... Peter Alfke, Xilinx.Article: 101997
On 09 May 2006 10:13:43 GMT, pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: >Mike Harrison <mike@whitewing.co.uk> wrote: >>Anyone know a UK stockist for the Xilinx/Digilent S3 board ? >>(or anyone have a spare one - I only want the PCB) >>Xilinx website seems to have discontinued it & only lists Cedar as UK disti & their website has >>minimal info, and Avnet only list their own boards as far as I can see. >>Digilent want $32 to ship USPS (which would cost $9 in a GP flat-rate envelope) > >They refuse to ship by other means .. ? I've not asked, but USPS are almost always the cheapest way to ship US-UK.Article: 101998
In article <E9Q7g.233$227.179@fe04.lga>, Ron <News5@spamex.com> wrote: >The synthesizer reports a maximum frequency of 58MHz for the 64 bit >design, 16MHz for the 704 bit design, 12 MHz for the 1024 bit design "as >is" without any tweaking to improve the timing, so it should take about >1.1 microseconds to multiply two 64 bit numbers together, and 85 >microseconds to multiply two 1024 bit numbers together. The unoptimised build of gmp on this bog-standard Athlon X2 4400+ system takes ten microseconds for a 1024x1024->2048 multiply; and there are two processor cores working independently. I really think you haven't looked enough into what can be done in software before jumping to hardware; gmp-ecm is in the public domain, and Bruce Dodson runs it full-time on a 120-node Opteron cluster at LeHigh university. TomArticle: 101999
Jim Granville schrieb: >> No. The article is not talking about chained buffers for high timing >> resolution. Such a setup would still charge the clock lines from VDD and >> discharge to GND for each clock cycle. >> >> They are really talking about sending a wave around a transmission line. > > > Correct - see my comment on using the routes inside a FPGA for this. > >> Standing wave clocking is an exotic but established technique in PCB >> design. At high frequencies you can use it inside ICs. >> A physical wave uses the same charge again and again, only resistive and >> EMI losses need to be refreshed by buffers PARALLEL to the transmission >> line. > > > yes, Parallel drive might test the FPGA tools some more :) > > Series drive would be a compromise, where the physical delay dominates > the gate delay. With each generation, the gate delays shrink faster than > the physical delays. I believe you are still missing the point. If you are chaining buffers you are still fully charging and discharging each node in each clock cycle using the power supply. That is not a wave. The same energy is traveling back and forth (for standing waves) or in a circle (for circular waves). You only need to replace some damping effects (Resonance). You definitely did not do that in a CPLD. You cannot have the energy cross FET-gates. At least not at frequencies that low so series will achieve nothing. http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac2003/papers/2003/dac03/pdffiles/40_1.pdf Kolja Sulimma
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Compare FPGA features and resources
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