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Sanka Piyaratna wrote: > Hi Everyone, > > I am wondering if it would be possible to drive a 800 MHz 10 bit > parellel A/D using an FPGA which has a 100MHz system clock. > > Thanks, > > Sanka I'm not sure what you mean by drive the ADC with the FPGA. The signal flow is the other way around: the ADC will drive the FPGA. You should not drive your ADC clocks from the FPGA. The jitter introduced by the FPGA will absolutely kill the noise performance of the ADC at 800MHz. At 100 MHz it will reduce the SNR to considerably less than the 10 bits. Use a clean external clock to clock the ADC. Most high speed ADCs have a clock output that can be fed to the FPGA to get a clean transfer of the ADC data into the FPGA.Article: 100826
Hi, I'd like to know how a manufacturer arrives at the max clock rate of a particular speed grade of a device? For example, if we have the Xilinx Virtex-II Pro XC2VP50 FPGA with speed grade 7 parts, how's the max limit of 200 MHz fixed? If I build a design for which I make sure that all stages complete under, say 4ns, for the XC2VP50, I would benefit if I can clock the FPGA at 250 MHz. What issues would prevent a higher clock rate from being allowed? Also, if it's based on various calculations, how do you end up with so round figures as 200 MHz or 400 MHz? Thanks.Article: 100827
I appreciate your help Tom. I think for the current project I will use C++, or hopefully ASM/SSE2 if someone writes it for me or I research it more. The advantage of the the fpga is that many reference vectors (loaded from onboard memory) can multiply by an incoming input vector (loaded over pcie) at the same time. With a spartan-3 pcie starter kit with DDR I could hope for 200 to 250 Gbits per second dot product. If you are right about the P4 being fast enough to bottleneck at the memory then I could hope for 25.6 Gbps memory bandwidth. That's actually pretty good. When I switch to optical recognition I will have perhaps 1,000 reference vectors that will be much smaller, only about 1kilobit each or so. Since these reference vectors could fit in block ram I could see 16 terabit per second on that project. I will approach the assembly forum, thanks for your help.Article: 100828
Just ignore that number of Fmax, if your timing simulation tells you that the clock period can be shorter. Watch the max output frequency of the DCM though. Peter Alfke, Xilinx ApplicationsArticle: 100829
there are many reasons that will make the computer could not find the cable. 1=2E If you have the hardware dog ( it is a kind of license), install it with the cable. 2=2E Most of time, i just chang the cable, computer or reinstall the software, and get the good result. could you describe the details of your condition? Rene Tschaggelar =E5=86=99=E9=81=93=EF=BC=9A > For a legacy project I have MaxPlus2 with the > Byteblaster MV. For a reason unknown to me, > the Programmer modal tells me that the > programmer is not there. "Can't find programming > hardware" > > I checked the JTAG pins and their voltage levels. > It should be correct. What else is checked ? > > The device connected : EPM3128AT144-10 > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.netArticle: 100830
Hi Mikhail, > method, will EDK pick up the cores from the local pcores directory instead > of its main repository automatically or will I have to import them as custom The local pcores directory is prefered. So you can copy the core 1:1 from the main repository. > peripherals after the change? Also, could you please comment on the software > side of the things? Just how much of the support is there and how much needs > to be written/modified? I didn't write the software. As I know no modifications are needed. A few bits in the TEMAC hardware can have changed. Have fun FlorianArticle: 100831
Question: Is it possible / feasible / easy to implement a design on an FPGA such that two or more circuits are guaranteed not to share any part of the FPGA hardware? The application is this: I have redundant inputs and redundant outputs - I wish to use a single FPGA, but maintain the redundancy. I am concerned only with safety, not with reliability, so complete failure of the FPGA is not an issue. My concern is that the two circuits, whilst specified independently, would end up optimised and sharing gates, thus compromising the independence.Article: 100832
Hi, pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > I read the thread on xilinx online shop issues. > > So how are the other options? > (Altera, Lattice, Actel) > > - Priceing on small samples / evaluation boards ..? > > - Software is smooth and/or pricey..? > > - Have online shop, or _good_ distributors ..? (I live in Europe) > > - Reliability (silicon & customer relations) ..? > > - Any new fpga manufactor to enter this market soon ..? Since I see that you are from my old Univeristy in Sweden I might also give you a hint to the local bible in Sweden ELFA they do have Max2,Cyclone, Cyclone2 and config memories from Altera in thier catalog. Not the cheepest way but they take small quantiy orders and you don't have to be a company to buy from them. Hope this helps FredrikArticle: 100833
Hi, Dioptre schrieb: > Question: Is it possible / feasible / easy to implement a design on an > FPGA such that > two or more circuits are guaranteed not to share any part of the FPGA > hardware? No problem. You need two independend clock and reset lines. This comes typical to two independend parts of your design. As long as both designs are complete independend and share no IO I would consider it hard to find any possibility to enable some resource sharing. Of course you need to inspect the used fpga technology if there is any global fpga function like global reset at power up and check wheter this has any influence for your demands. But in general there is no problem bye ThomasArticle: 100834
We are working on a project with some vhdl entity re-instantiated several times. We would like to use incremental synthesis, so we add this xcf file: [...] MODEL "decimatore" incremental_synthesis = yes; [...] The problem is that xst seems to perform incremental synthesis on the first instance of "decimatore" only, ignoring the other ones. Why? We need different syntax in xcf file? Thank you. -- MarcoArticle: 100835
samiam wrote: >> You're about to waste your money, IMNSHO. Especially if you don't >> already >> have a universal programmer that can handle them. > > > Point taken. > I wont invest in them ... especially after reading through my universal > programmer and NOT seeing them listed. > >> If they're free, they're too expensive. > > > Ok > >> You can buy a brand-shiny-new Xilinx XC9536 in a PLCC for $3.30, > > > I avoid CPLD's. seriously. I think they are OVERKILL for the stuff I do > and put me wayyyyy above the details I like to fool around with when I > am designing boards > > I also hate messing with anything that I can NOT get in DIP form since > I build the boards at home. > > Maybe as my exposure and experience designing and building boards at > home improves ... I may get to that point. > > But for now I love simple PLD's ... 16R8' 22v10's for replacing 74xx > parts. Nothing more. If you want a little more 'smarts' but still in DIP, look at the ATF750CL from Atmel and the AnaChip PLDs - these plug into a 22V10 socket, but have buried registers, -jgArticle: 100836
andrewfelch@gmail.com wrote: > When I switch to optical recognition I will have perhaps 1,000 > reference vectors that will be much smaller, only about 1kilobit each > or so. Since these reference vectors could fit in block ram I could > see 16 terabit per second on that project. Since the reference vectors are relatively stable, it may be effective to integrate them with the logic that actually sums the bits, and keep them in distributed RAM. See the thread on "Counting 1's" back in Oct 03, which illustrates an approach. The input leafs of the tree start the summing process by adding 3 bits in two LUTs. This leaves an extra LUT input that could be used to select between two different reference vectors embedded in the leafs. Using SRL16's would allow changing the reference vectors. Just a thought.Article: 100837
Steven is right, I definatelly recommend OpalKelly board if you need USB2.0 transfer rate (this board goes up to 30MB/s). It very easy to use and works without any problems. The only cons is the size (2.0 x 3.5") and the price 200$. Cheers, GuruArticle: 100838
Hi, There are certain synthesis constraints that will by default tend to share the resources if the logic involved across 2 set of output lines are identical. The mathematical logic resources are bound by Resource Sharing Option. If you are using the ISE for Synthesis, you can disable this option through the synthesis properties. Another property is Equivalent Register Sharing and this is about sharing flip-flops that are described in the RTL and in the Xilinx Specifif Options of the Synthesis properties, you can disable this property as well to ensure independent use of resources. Similar properties and settings are available for other party synthesis tools as well. Hope this explanation helps. regards, Venkat.Article: 100839
As Andraka pointed out, I guess you want your ADC Ouput connected to the FPGA and if from what you mean the ADC is gonna sample at 800 Mhz and you want the process those samples in your FPGA which can only work at the max of 100 Mhz clock, the only way to do that is to use a DMUX chip prior to the FPGA on board. There are DMUX chips available that will demux 1:4 or 1:8 which also gives the slowed down data latch signals (clock) which can be used as clock to latch the demux data inside the FPGA. Hope this helps. Venkat.Article: 100840
IIRC the Fmax number is something made up by companies to satisfy government export control licenses. Above a certain toggle rate it's illegal to ship to 'evil' countries. Although that might be nonsense. Cheers, Syms. "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1145419942.341970.113370@v46g2000cwv.googlegroups.com... > Just ignore that number of Fmax, if your timing simulation tells you > that the clock period can be shorter. > Watch the max output frequency of the DCM though. > Peter Alfke, Xilinx Applications >Article: 100841
entity my_entity is
port (
clock : in std_logic;
reset : in std_logic;
input_signal : in std_logic;
output_signal : out std_logic;
output_complete_signal : in std_logic
);
end my_entity;
architecture RTL of my_entity is
signal local_signal : std_logic;
signal local_flag : std_logic;
begin
process ( clock, reset )
begin
if ( reset = '0') then
output_signal <= '0';
local_signal <= '0';
local_flag <= '0';
elsif ( clock'event and clock = '1') then
if ( input_signal = '1' ) then
if ( local_signal = '0' ) then
local_signal <= '1';
end if;
end if;
if ( local_signal = '1' ) then
if ( local_flag = '0' ) then
local_flag <= '1';
output_signal <= '1';
else
if ( output_complete_signal = '1' ) then
output_signal <= '0';
local_flag <= '0';
local_signal <= '0';
end if;
end if;
end if;
end if;
end process;
Article: 100842Superman <harissh77@yahoo.com> writes: > Hi guys, > > Any 1 help me with info on *.XDL file, i know that this file a ASCII > verison of the NCD file. can 1 tell me where i can get more info?? i > have extensively searched the Xilinx webpage in vain. Create an XDL file of your design and it will have some (all that exists to my knowledge!) documentation of the format inside. There was a long thread on XDL not long back, which you might find enlightening... search google groups for "working with XDL" Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 100843
oh i dont think there is any licensing problem, because so many companies are allready selling compatible chips on net and also in trade show.. without any problem.. can anyone help? thanks In article <ddQ_f.6732$tT.3171@news01.roc.ny>, John_H says... > >Contact HP for licensing information. I believe they are legally required >to make available - for a reasonable price - the chips or the technology for >toner refillers and alternative suppliers. Doing so without their >permission may result in the product you produce violating copyrights or >considered black market. > ><tonerchips@hotmail.com> wrote in message >news:e1fg5i01hpf@drn.newsguy.com... >> hi all >> i indent to make chips for toner cartridges ( specially hp ) in singapore >> i need technical assistance in this regard and willing to pay reasonable >> amount >> for technology. >> kindly let me know if anyone can help >> >> thanks >> tonerchips > > -- NewsGuy.Com 30Gb $9.95 Carry Forward and On Demand BandwidthArticle: 100844
It is the free version of the software, the downloadable license is in place. I'm going to measure the JTAG signals now. Rene chark.chen@gmail.com wrote: > there are many reasons that will make the computer could not find the > cable. > 1. If you have the hardware dog ( it is a kind of license), install it > with the cable. > 2. Most of time, i just chang the cable, computer or reinstall the > software, and get the good result. > could you describe the details of your condition? >=20 > Rene Tschaggelar =E5=86=99=E9=81=93=EF=BC=9A >=20 >=20 >>For a legacy project I have MaxPlus2 with the >>Byteblaster MV. For a reason unknown to me, >>the Programmer modal tells me that the >>programmer is not there. "Can't find programming >>hardware" >> >>I checked the JTAG pins and their voltage levels. >>It should be correct. What else is checked ? >> >>The device connected : EPM3128AT144-10Article: 100845
Ken Reeves wrote: > Hi, > > I'd like to know how a manufacturer arrives at the max clock rate of a > particular speed grade of a device? For example, if we have the Xilinx > Virtex-II Pro XC2VP50 FPGA with speed grade 7 parts, how's the max limit > of 200 MHz fixed? If I build a design for which I make sure that all > stages complete under, say 4ns, for the XC2VP50, I would benefit if I > can clock the FPGA at 250 MHz. What issues would prevent a higher clock > rate from being allowed? > > Also, if it's based on various calculations, how do you end up with so > round figures as 200 MHz or 400 MHz? There have to be some timing cathegories, thus the round numbers. Ever wondered why resistors are available in 1%, 5%, 10% margin, that is the same. And while your board may only be used at lab conditions, the specified timing is met in the full temperature range, the full supply voltage range(s). Meaning, the specified timing is met at for the chip worst case. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 100846
You must install the driver for the cable first. See: http://www.altera.com/support/software/drivers/dri-bb-2k.html /LarsArticle: 100847
Simon, I noticed that local_signal gets set in two seperate if - end if sections. If both sections are true, the second one wins, IIRC. This can be confusing, so I endeavour to avoid this in my code. You might want to merge the two sections with an else. You could always try simulating it with a testbench to check you get what you want? Or code it as a FSM so it's more readable? BTW, I recommend using rising_edge(clock) instead of that clock'event stuff. It not only saves typing but works better in simulations when things can change from other than '0' to '1'. Finally, do you know about comp.lang.vhdl? They love this stuff! :-) HTH & Cheers, Syms.Article: 100848
Thank you very much everyone for your help. I was originally thinking of the problem in the wrong way around. Now I understand what you mean. I have not yet determined what parts to use. At this stage I am still scoping the problem. Thank you, Sanka Venkat wrote: > As Andraka pointed out, I guess you want your ADC Ouput connected to > the FPGA and if from what you mean the ADC is gonna sample at 800 Mhz > and you want the process those samples in your FPGA which can only work > at the max of 100 Mhz clock, the only way to do that is to use a DMUX > chip prior to the FPGA on board. There are DMUX chips available that > will demux 1:4 or 1:8 which also gives the slowed down data latch > signals (clock) which can be used as clock to latch the demux data > inside the FPGA. > > Hope this helps. > > Venkat. >Article: 100849
tonerchips@hotmail.com wrote: >oh i dont think there is any licensing problem, because so many companies are >allready selling compatible chips on net and also in trade show.. without any >problem.. > >can anyone help? > >thanks > > That's just it - there is no problem. I would be surprised if none of the companies that are already selling compatible chips got information legally and formally from HP.
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Compare FPGA features and resources
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