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Mark McDougall wrote: > Tommy Thorn wrote: > >> but in the captured data fse_d is shown changing one cycle after >> fse_d_out. Is this delay an expected bus turn around associated with >> a tristate bus? > > When's sram_oe_n changing? Good point, I forget to mention that. It's set a cycle earlier than fse_d_out. However in an experiment I just ran, sram_oe_n was held constant and the effect was still there, so it has nothing to do with "bus turn around" but is still related to the external bus. Puzzled. Thanks, TommyArticle: 100776
Hi Mikhail, you have 2 ways: Xilinx application about an GMII to RGMII interface. (XAPP 692 ?) Change the PLB_TEMAC core: Copy the Xilinx cores plb_temac_v2_00_a, ipic_to_temac_v2_00_a and hard_temac_v1_00_a in a EDK local pcores directory. In plb_temac change the EMAC_CONFIG_VECTOR. Look in the TEMAC documentation. You have to change also the GMII signals to RGMII signals thru all entities down to hard_temac. Both ways are running on my costumer board. Have fun Florian MM wrote: > "Joseph Samson" <user@example.net> wrote in message > news:Uzz%f.58788$F_3.20549@newssvr29.news.prodigy.net... > > > > I just got off the phone with my webcase CAE. He says that the next > > version of PLB_TEMAC (v3) will be released with 8.1 SP2, which was > > actually supposed to be today. It has RGMII and other features. > > Great news! Thanks. > > > /MikhailArticle: 100777
On Mon, 17 Apr 2006 20:44:20 GMT, "John_H" <johnhandwork@mail.com> wrote: >It may be $178 from European distribution; the www.em.avnet.com site shows >$149. I may have a cookie set that says I'm a US locale. My S3E kits >(ordered a while ago) had a few dollars shipping - not much considering the >"usual" charges. If you "Hit Order" , it will list $178 for qty = 1 , and $149 for qty >= 100 I did not go further , so i don't know if it just is $149 when logged in. Ohh and on Xilinx website i could choose EU (prob. the Powersupply) , but i can only order a US on AVNET , that is too bad. Xilinx ... When is it comming in your webstore , in an EU version ??? Regards CarstenArticle: 100778
On 17 Apr 2006 16:01:12 -0700, Eric Smith <eric@brouhaha.com> wrote: >> Those $28 would be the shipping from Xilinx , so i hope Avnet is >> shipping for free. > >I ordered the HW-SPAR3E-SK-US from Avnet on 5-Apr, and received it on >12-Apr. I was charged $149 plus $12.29 sales tax plus $12.82 shipping >and handling to get it from Avnet to me via Fedex ground service. I >wasn't charged anything for shipping from Xilinx to Avnet; it's not >customary for the end purchaser to pay for that. > >I have no idea what they'll charge for shipping to Europe, but >if it's $28 that sounds reasonable. > I meant when i ordered the Spartan3 kit from Xilinx i payed around $30 for shipment from Xilinx to DK CarstenArticle: 100779
In article <1145050118.699722.123650@e56g2000cwe.googlegroups.com>, <andrewfelch@gmail.com> wrote: >Hello, > >I am a Python programmer writing neural network code with binary firing >and binary weight values. My code will take many days to parse my >large data sets. I have no idea how much fpga could help, what the >cost would be, and how easy it would be to access it from Python. The >problem is similar to competitive networks, where I must dot product >many million-length bit vectors (which only change occasionally) with 1 >input vector. How dense are your rarely-changing bit vectors, and if you write them down in 15-bit chunks, how many of the 32768 possible 15-bit chunks are used? If the answer to the first is 'not very' then you can use sparse techniques; if the answer to the second is 'few', then look-up tables will fit nicely in L2 cache. Bitwise AND of two 128-bit vectors ought to take under a nanosecond on a fast P4, then you can do various of the popcount tricks bytewise in the SSE2 registers then add up the subregisters with a PSADBW call against a register containing zeroes, accumulate in two halves of an SSE register and an add at the end. I really think you should ask the people in comp.lang.asm.x86 to see how fast they can get your code on CPU before contemplating FPGAs: you ought to be able to manage main-memory speed, which is about two thousand a second, or faster if you can fit things into L2 cache. An FPGA will be limited by memory speed again; whilst with an unlimited budget you can get several channels of SRAM or DDR2 and perhaps five times the peak memory performance of a P4, the hardware's so expensive that you'd be better off getting a large number of cheap P4 boxes unless you're doing this at truly large scale. TomArticle: 100780
Labo.EKO <labo.eko***nospam***@free.fr> wrote: > hi everybody, > maybe we can do a petition about this xilinx store ?... > i'm French user and i can affirm that Avnet France, preferer (to not says > want ) only big customers .. > they are slow and expensive.. totaly incompatible with prototype phase. > Maybe Xilinx prefer that we try Lattice or others parts ?... > i'm realy not happy against that problem. they can be take example from > Microchip & sample service ... > ( sorry for my bad english ! ) I also plea for Xilinx keeping/reinstatiating the Online Shop. Dealing with distributors for prototyping is not an easy task... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 100781
On Tue, 18 Apr 2006 08:58:53 +0000 (UTC), Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >Labo.EKO <labo.eko***nospam***@free.fr> wrote: > > >> hi everybody, > >> maybe we can do a petition about this xilinx store ?... >> i'm French user and i can affirm that Avnet France, preferer (to not says >> want ) only big customers .. >> they are slow and expensive.. totaly incompatible with prototype phase. > >> Maybe Xilinx prefer that we try Lattice or others parts ?... > >> i'm realy not happy against that problem. they can be take example from >> Microchip & sample service ... > >> ( sorry for my bad english ! ) > >I also plea for Xilinx keeping/reinstatiating the Online Shop. Dealing with >distributors for prototyping is not an easy task... Agreed - the problem is that distis are always chasing after sales, but prototyping is done by tech people who usually can't answer questions about quantities, production schedules etc. This is why it's much better for this end of the market to be served by the manufacturer.Article: 100782
>Anyhow, Digikey seems to to at as good or better a job as Avnet at >stocking Xilinx parts. If you click on the parts listed in the Xilinx >"store" and wind up on the Avnet page, almost everything is listed as >"out of stock", and a lot of valid device/package combinations simply >aren't listed at all. This was also the case every time I looked at the old xilinx store though....Article: 100783
Hi, I'm trying to use the unbonded IOB's available in the virtex 4 (lx25) as route through's to allow one input to fanout to say 16 IDELAY's. Any ideas of how to go about doing this or documents that explain this would be much appreciated. Thanks in advance, AlastairArticle: 100784
Hi all, I was going through the datasheet of virtex2 , in which i read that "each 4-input function generator is programmable as a 4-input LUT, 16 bits of distributed SelectRAM memory, or a 16-bit variable- bits of distributed SelectRAM memory, or a 16-bit variable-tap shift register element." In the diagrams given in the viretx2 datasheet for cascadable shift register , i don't seen any clock at all. Can anybody clarify on this implementation??? Regards, PravArticle: 100785
On 2006-04-14, Gerr <gertvierman@hotmail.com> wrote: > I've got the same problem here: the USB cable works fine with windows, > but using linux, the CPLD version is mis-read, and the only thing > happening is the firmware being updated. (which takes almost an hour, > hilarious!). I'm using ISE 8 instead of 6, but the symptoms are the > same. > > I just contacted Gilles in private to see if he found any solution to > this issue yet. His workaround is the same as mine: use a windows > machine for programming with the USB platform cable. I'm sure that's > not what xilinx had in mind, when the published the Linux drivers for > this cable. > > Does anybody have this cable working yet, running a 2.6 linux kernel ? I'm not sure if I have answered in this thread or not, but my experience is that the cable works in Linux if I have started impact in windows first. If I don't, impact in Linux wants to upgrade the CPLD version. I'm using ISE 8 in both Linux and Windows. /AndreasArticle: 100786
Is there any lowpriced board with _just_ a FPGA + ethernet 100 Mbps interface?Article: 100787
Andreas Ehliar wrote: > On 2006-04-14, Gerr <gertvierman@hotmail.com> wrote: > > I've got the same problem here: the USB cable works fine with windows, > > but using linux, the CPLD version is mis-read, and the only thing > > happening is the firmware being updated. (which takes almost an hour, > > hilarious!). I'm using ISE 8 instead of 6, but the symptoms are the > > same. > > > Does anybody have this cable working yet, running a 2.6 linux kernel ? > > I'm not sure if I have answered in this thread or not, but my experience is > that the cable works in Linux if I have started impact in windows first. If > I don't, impact in Linux wants to upgrade the CPLD version. Ah, I must say I haven't tried that yet. It's terrible workaround for a serious flaw, but if it works, it's better then nothing. Thank you very much,Article: 100788
Prav, It is common practice to draw simplified block diagrams without the clock connection when all components are clocked from the same source. The blocks shown in the Virtex 2 user guide are each SRLC16, which have a Q output for variable delay plus a Q15 output for cascading. When connecting in a long variable shifter design, normally the Q15 output is attached to the next SRLC16 and the Q outputs are multiplexed using the upper bits of the delay as the selector. Then the lower 4 bits of the desired delay can route to all SRLC16's in the chain. Regards, Gabor prav wrote: > Hi all, > > I was going through the datasheet of virtex2 , in which i read that > > "each 4-input function generator is programmable as a 4-input LUT, 16 > bits of distributed SelectRAM memory, or a 16-bit variable- bits of > distributed SelectRAM memory, or a 16-bit variable-tap shift register > element." > > In the diagrams given in the viretx2 datasheet for cascadable shift > register , i don't seen any clock at all. > > Can anybody clarify on this implementation??? > > Regards, > PravArticle: 100789
Carsten wrote: > On Mon, 17 Apr 2006 20:44:20 GMT, "John_H" <johnhandwork@mail.com> > wrote: > > >>It may be $178 from European distribution; the www.em.avnet.com site shows >>$149. I may have a cookie set that says I'm a US locale. My S3E kits >>(ordered a while ago) had a few dollars shipping - not much considering the >>"usual" charges. > > > If you "Hit Order" , it will list $178 for qty = 1 > , and $149 for qty >= 100 Try: https://www.em.avnet.com/pns/home/0,5533,CID%253D0%2526CCD%253DUSA%2526SID%253D0%2526DID%253DDF2%2526LID%253D0%2526BID%253DDF2%2526CTP%253DPNS,00.html?ref=https://emwcs.avnet.com/webapp/wcs/stores/RedirectWCSLogon?langId=-1&storeId=500201&catalogId=500201&reLogon=https://www.em.avnet.com/auth/framelogin/&URL=RemoteAdvancedSearchView%3FlangId%3D%2D1%26storeId%3D500201%26catalogId%3D500201%26manufacturerPartNum%3DHW-SPAR3E-SK-US or (the same thing) http://tinyurl.com/qrr2gArticle: 100790
prav wrote: > Hi all, > > I was going through the datasheet of virtex2 , in which i read that > > "each 4-input function generator is programmable as a 4-input LUT, 16 > bits of distributed SelectRAM memory, or a 16-bit variable- bits of > distributed SelectRAM memory, or a 16-bit variable-tap shift register > element." > > In the diagrams given in the viretx2 datasheet for cascadable shift > register , i don't seen any clock at all. > > Can anybody clarify on this implementation??? > > Regards, > Prav See, specifically, Figure 21 on page 16 of "Module 2: Functional Description" (pdf page 24) from v3.4 of the "Virtex-II Complete Data Sheet (All four modules)" http://direct.xilinx.com/bvdocs/publications/ds031.pdf Where the DI and WS are illustrated on the LUT with the write strobe generated as "WSG" from the Write Enable and Clock.Article: 100791
I agree whole-heartedly - and believe me, I'm a miser when it comes to parts spending for my hobby. I have some samples of Xilinx 3042 FPGA's that I will never use. It's just not worth the effort of tracking down archaic software and installing DOS on a machine. Believe me, I'm working with an old design at work right now that uses 3 Xilinx 4010E's and a UV eraseable PROM. I had forgotten what a serious PITA it is to have to wait 30 minutes to reprogram a device. (fortunately, we have spares, so I just cycle them through the eraser when we identify a change) Then, there was the fun of trying to get a copy of ISE 4.2i - which wasn't easy even at a fortune 500 company that used it several years ago. I can't imagine trying to dig up the CD and a registration code as a hobbyist. Get a modern part that is JTAG programmable. Make sure it's supported in either the ISE or the Quartus webpacks. The time you save is worth way more than the cost difference, and you will get a better part to boot. This is a golden age for hobbyists - as you can do an entire design essentially for free, save the cost of parts, as long as you use the economy versions - and today, the "economy" versions of most of these parts are incredibly powerful - enough that the company I work for has started seriously considering them for lower power applications in lieu of Virtex and Stratix parts. Check digilent - they have modern CPLD's on a DIP board that you can directly mount in a 40 pin socket. These are perfect for prototyping - and at $20 a piece, they aren't horrible. Once your design is ready, you can get the bare part for under $3 or $4, and design a PCB. Much simpler, easier - and probably even cheaper in the long run.Article: 100792
Hello: Does anyone know if there is a simple PCB out there with a Xilinx FPGA (almost anything would work, Spartan III prefered) that has that FTDI 245 (the parrallel version) USB FIFO IC integrated on the PCB? I just need something for a code demonstration. I am in a pinch for a demonstration and we dont have the time to cut a PCB...... And it seems that the new webstore policy means that I can no longer get chips for at least 12 weeks...... -EliArticle: 100793
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > Is there any lowpriced board with _just_ a FPGA + ethernet 100 Mbps interface? > The closest thing I have found is the VirTex 4 Mini Module from Avenet/Memec -EliArticle: 100794
Steve- Thanks very much for the detailed explanation. I did not realize S3 has that much variation in pull-up/pull-down values, and the min values could be under 2k. That does explain some of the things we've seen. We had got this idea in our heads of "weak pull-ups" from our Spartan II boards... I wish S3 Rs were a uniform 10k or so, but it sounds like it's not easy as the process continues to shrink. Is this what we can expect on newer devices also? It seems if we used a lot of internal FPGA pull-ups/downs instead of external ones we could significantly increase power consumption and heat of the device. -JeffArticle: 100795
Jeff Brower wrote:
> but XST appears to be doing something different with the integer
> comparison than what I'm expecting, possibly sign-extending both sides
> to 32-bits. Is there a way to "typecast" an index?
Try your question on comp.lang.verilog.
In vhdl I would use an integer range or unsigned.
Whatever XST is doing, I expect that it would match modelsim.
I prefer trial-and-error simulation to synthesis.
-- Mike Treseler
Article: 100796Thomas Reinemann wrote: > Hello, > I want to attach an FPGA to a micro controller and therefore I'm looking > for methods how to do this. Is there more than memory mapped, any where > an overview? > > Bye Tom Look at how peripherals are connected to micro controllers, and consider using the same methods for your FPGA. The three popular methods are memory mapped, SPI (Serial Peripheral Interface, but you may see it under other names) bus, and I2C (Inter Integrated Circuit -- called "eye squared cee") bus. Memory mapped you know of. It's fast, but it uses the most FPGA pins and quite a few FPGA resources. None the less the actual FPGA design is straightforward, although if the processor speed approaches that of the FPGA one can end up sweating timing details to a large degree. SPI is a byte-oriented synchronous serial link. It uses three or four wires from the micro to the peripheral -- clock, data in, data out, and some sort of framing information which is often bit-banged in software. If the FPGA is set up as the slave it can be little more than an externally clocked shift register and a latch to let the FPGA know that the transfer is done. It's slower than memory mapped, and it only supports point-point links. I2C is an invention of the devil -- er, Philips. It's this way-complex thing that allows two-wire communication between a micro and a number of peripheral chips on a board. It would probably require more space inside the FPGA than memory mapped, you'd tear your hair out making it work, and when you were done you couldn't call it "I2C" without paying Philips royalties (they trademarked the name, but if they patented it it's expired -- so some vendors make their stuff compatible, then figure out how to tell you so without saying "I2C"). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/Article: 100797
On Tue, 18 Apr 2006 09:51:48 -0400, Eli Hughes <emh203@psu.edu> wrote: >Hello: > >Does anyone know if there is a simple PCB out there with a Xilinx FPGA >(almost anything would work, Spartan III prefered) that has that FTDI >245 (the parrallel version) USB FIFO IC integrated on the PCB? I just >need something for a code demonstration. > >I am in a pinch for a demonstration and we dont have the time to cut a >PCB...... And it seems that the new webstore policy means that I can no >longer get chips for at least 12 weeks...... > FTDI now sell nice little DIL modules in their online store that would make it very easy to add to most FPGA boards : http://apple.clickandbuild.com/cnb/shop/ftdichip?op=catalogue-products-null&prodCategoryID=39&title=UM245RArticle: 100798
Eli Hughes <emh203@psu.edu> wrote: > Does anyone know if there is a simple PCB out there with a Xilinx FPGA > (almost anything would work, Spartan III prefered) that has that FTDI > 245 (the parrallel version) USB FIFO IC integrated on the PCB? I just > need something for a code demonstration. The EZ2SUSB has a Spartan-II: <http://www.easyfpga.com/ez2susb_features.htm> -aArticle: 100799
Thomas Reinemann wrote:
> I want to attach an FPGA to a micro controller and therefore I'm looking
> for methods how to do this. Is there more than memory mapped,
also port mapped, or embedded (nios, microblaze)
> any where an overview?
http://en.wikipedia.org/wiki/Memory-mapped_IO
-- Mike Treseler
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