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Hi does anyone know what should happen on read access to DDR memory space when external connections to DDR memory are not correct? I am troubleshooting a custom board and what I see is that OPB DDR controller makes total OPB bus freeze on first DDR read access. ToutSup=1 and then nothing happens. In the datasheet DQS strobe is going to WREN of read fifo so I could think a missing DQS from external chip could cause bus freeze, but I am not really sure as it is not described in the datasheet (eg what should happen on missing DQS). I have tried all DDR controllers from EDK 8.1 PLB_DDR OPB_DDR OPB_MCH_DDR and all seem to have similar freeze behaviour the DCMs all work (tested) and the EDK system also works - well until first read to DDR space any helpful hints? AnttiArticle: 101001
Hello Guru The FIFOs can be expanded, isn't it? There's a lot of resources availables to do this. And I need a very high transmisión speed and the results showed in the xapp807 are reception bandwith. I'm watching a webcast at www.techonline.com about to learn to use the ultracontroller-II with the TEMAC. I will inform about the evaluation of the UCII + TEMAC. Best regards boysArticle: 101002
Hi all, i am currently working on altera FPGAs,when i was trying to generate a memory using megafunction wizard,in the options it is registering both inputs and outputs of the memory,and i have the option of not-regestering the output.But as the input is registered when i use the component it is not giving the expected value.Can anyone tell me how to disable the option of not registering he inputs. waiting for reply, Thank you, Regards RamakrishnaArticle: 101003
Mine is actually a demux. A 8 bit data goes to any of the 256 locations. Thus a statement like below will create latch. reg [256*8-1:0] out; out[ind*8+7:ind*8] = in; this can be converted to FFs by following statement always@ (posedge clk4x) out1[ind1*8+7:ind1*8] = in1; clk4x because to reduce size i am using TD multiplexing. The output goes to another FF which latches on the +ve edge of the clk. so how this can be possible. I think i have to phase shift the clk4x advance it wrt to the clk by a small amount. These are my problems in using FFs. I tried the FF type (not given important to functionality). But found that that design is also not routing. The LUT is 88% FF is 33% Slice is 96%. Now only 20 or less latches in the design ( most of then are part of the complicated case statements). If that too is also a problem will avoid that. regards Sumesh V SArticle: 101004
Hi It's no bad the webcast at www.techonline.com. There is a presentation with voice and you can save it in pdf format and the transcription of the voice too. We will follow informing...Article: 101005
>"freechip" <freechip@hotmail.fr> wrote in message >news:VqSdnSn0Kpv2YtXZRVn_vA@giganews.com... >> >> Hi, >> I am working on a 10 Gb Ethernet project (deep packet inspection) and need >> to implement CAM in my FPGA. I am using a Stratix GX and I don't think I >> can use CAM (internal or external) in the stratix GX Dev Board. >> >> Let me know your thoughts about that. >> >> Thanks a lot. > >How big a (Ternary?)CAM do you need? > > Hi, I don't yet. Do you think it is possible with Altera products? Have a good day.Article: 101006
Hi Ramakrishna, as far as I know it is not possible to disable the input registration. Rgds Andr=E9Article: 101007
Hi freechip, yes I think it is possible to build a CAM around Altera RAM blocks. How big is the CAM ? After how many clock cycles do you need a hit ? Rgds Andr=E9Article: 101008
>Hi freechip, > >yes I think it is possible to build a CAM >around Altera RAM blocks. > >How big is the CAM ? After how many clock cycles >do you need a hit ? > >Rgds >Andr=E9 > > Hi Andr, Actually, I am in the research phase and I really don't know how big is the cam. I just wanted to know, to compare to Xilinx Family, if it was poosible to use cam with Altera product. For my project (deep packet inspection), the use of the cam is necessary. If you can tell me how can a build a cam around Altera RAM block (and the max. of the cam without my answers to your questions), I will be very pleased. Thanks.Article: 101009
I'd like to canvass opinion here. I'm sure opinions will vary greatly. The question is: Is is time to create a new group devoted entirely to general-purpose reconfigurable computing. In the usenet space, comp.arch.fpga is the best location for discussions related to "reconfigurable computing". I am well aware that mostly any use of an FPGA could be termed "reconfigurable computing" but I use the term here to describe attempts to create general-purpose computers based around reconfigurable logic. I am aware that this was the original intention of the comp.arch.fpga group. Times have changed however, the majority of FPGAs are destined for uses such as DSP and not as reconfigurable computing processing units. I'm quite sure that many people will state that there is room enough for both on this board and that the two aren't that far removed but I'm not so sure. Threads have a tendancy to migrate away from reconfigurable computing as I understand it. The following post from 1997 seems relevant to this discussion: http://groups.google.co.uk/group/comp.arch.fpga/browse_thread/thread/9febb2c8691cba64/801c034d1eb563ac?lnk=st&q=%22reconfigurable+computing%22&rnum=5#801c034d1eb563ac So, who here would be interested in creating a reconfigurable computing only group? Incidentally, one exists already at openfpga.org: http://www.osc.edu/forums/w-agora/index.php?bn=oscgeneral_openfpga It's been quiet so far but I think it just needs a push to get started. It may however be too far off the beaten track to ever see much action. Thanks, RobinArticle: 101010
>>How big a (Ternary?)CAM do you need? >> >> freechip wrote: > > Hi, > I don't yet. > Do you think it is possible with Altera products? > Have a good day. It's possible to build teeny, tiny CAMs. The information Austin pointed out gives you an idea of what you can accomplish with FPGA resources that can apply to all FPGAs, not just Xilinx. If you need a few entries, you might be okay. If you need small entries, you may be able to do many more. Read that documentation and you'll get a feel for the limits you're faced with. Personally, I'd love a 4kx20 CAM but I know there's no way to do it in an FPGA>Article: 101011
Trust me, it is more complicated than that, but there are plenty of both legit and questionable reasons for going with external buffers. For one, we are typically driving very long cable harnesses or large backplanes with lots of fan-out. While an FPGA pin might be able to do it, we are guaranteed performance with the external parts. There is also the fact that a technician can reasonably replace, or probe, a buffer chip - while a BGA repair requires a trip back to the factory. Then, there is debug and integration. Our integration and test cycles are already too short to allow for a two-week trip back to the factory for rework. Also, even at just 5%, the buffers are cheaper.Article: 101012
Hello all, I am running Xilinx ISE Project Navigator 8.1.03i. There seems to be an intermittent "bug"/"problem" that keeps on occuring. About, once/~hour the program will crash (and lock the project files. this is not a problem since the project offers the option to unlock the files upon openning the project...). However It does get very annoying. Usually it crashes when I am employing schematic editor. Also, this migth be unrelated to the above problem, but after several days/weeks of working on the same project, a new project has to be reconstructed from the original project's source files for the program just freezes up after the prompt of the [do you want to unlock the project?] (P.S When the program hangs, the task manager indicates that the _pn process eats anywhere from 88MB to 156MB -seems like a little too much) Has anyone else experienced this ? P.S I am running Win 2000, 238MB of RAM, 1.6GHz, P4 Please advise -RogerArticle: 101013
If I'm not mistaken, you have the option of determining whether the "calibration" works once at configuration, or continuously during/after configuration. Continuous calibration compensates for temperature/voltage variances during operation, but other than that, it has no real advantages, and if the board is quieter at configuration, it might be helpful to select calibration at config only. IIRC, one-time calibration uses less power too. If the calibration process is reasonably slow, is it possible to use a cap in parallel with the DCI resistor to help lower the AC impedance, and therefore reduce noise? (assuming noise was an issue in the first place) In any case, I would not place DCI resistors close to the FPGA at the expense of bypass cap placement near the FPGA. AndyArticle: 101014
Roger Bourne wrote:
> I am running Xilinx ISE Project Navigator 8.1.03i.
> Usually it crashes when I am employing schematic editor.
> Please advise
Consider entering your design and testbench
with a good text editor using an HDL.
Check the code with modelsim.
Use ISE to view RTL and run place+route.
-- Mike Treseler
Article: 101015Andy, Do not place a cap in parallel with the DCI resistor. If you do not need continuous calibration, then by setting it to calibrate once, you would need not be concerned about any noise. Austin Andy wrote: > If I'm not mistaken, you have the option of determining whether the > "calibration" works once at configuration, or continuously during/after > configuration. Continuous calibration compensates for > temperature/voltage variances during operation, but other than that, it > has no real advantages, and if the board is quieter at configuration, > it might be helpful to select calibration at config only. IIRC, > one-time calibration uses less power too. > > If the calibration process is reasonably slow, is it possible to use a > cap in parallel with the DCI resistor to help lower the AC impedance, > and therefore reduce noise? (assuming noise was an issue in the first > place) > > In any case, I would not place DCI resistors close to the FPGA at the > expense of bypass cap placement near the FPGA. > > Andy >Article: 101016
Hello: I ran into an issue (which may be a 'feature') in version 8.1 of ISE. When I have a simple verilog project with a top level module, I can no longer right click on one of the sub verilog modules for synthesis. In previous versions (7.1, etc) I could right click on any of the sub modules and syntehsize them indivdually. In 8.1 the only processes I have for a submodule are to check syntax, generate schematic symbol and view instantiation template. This is a real annoyance as it is nice to add submodules to my project to synthesize/simulate them indivually before integrating them into my top level module. If there a way to turn this 'feature' off? -EliArticle: 101017
On Mon, 24 Apr 2006 10:58:46 -0400, Eli Hughes <emh203@psu.edu> wrote: >Hello: > >I ran into an issue (which may be a 'feature') in version 8.1 of ISE. >When I have a simple verilog project with a top level module, I can no >longer right click on one of the sub verilog modules for synthesis. In >previous versions (7.1, etc) I could right click on any of the sub >modules and syntehsize them indivdually. In 8.1 the only processes I >have for a submodule are to check syntax, generate schematic symbol and >view instantiation template. > > >This is a real annoyance as it is nice to add submodules to my project >to synthesize/simulate them indivually before integrating them into my >top level module. If there a way to turn this 'feature' off? > >-Eli I don't know if it will work in verilgo, but I soppes it will. It works on VHDL. Right click on source node , "Select as Top Module". Do remember to reselect original Top module when done. I should classify it a s a real feature, because you can bypass it when needed, but you save time when double clicking on Synthesis with the wrong node selected. Best regards, ZaraArticle: 101018
I still have not completely figured out the pull up resistors on the Spartan 3 chips. It would appear that the data sheet has never been thoroughly reviewed for omissions and errors. Some of the information that should be clearly indicated in any number of places is missing and/or misleading. "A Low logic level on HSWAP_EN activates the pull-up resistors on all I/Os during configuration." Does this include the dedicated configuration signals? How about the dual purpose configuration pins? Or is it just the User IO? I found this sentance to be especially unenlightening... "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a pull-up resistor to HSWAP_EN during configuration, regardless of the value on the HSWAP_EN pin." What does a "pull-up resistor to HSWAP_EN" mean??? Why would TDO have (or need) a pull up to any value since it is a full time output? Why does Xilinx make it so hard to get the all important details on a part that has been in full production for so long? They just updated the Spartan 3 data sheet this month! Why wasn't the information that they know is lacking included? I say they know info is lacking because you can find it in an answer record if you know to look for it. I may put up a web page detailing all the short comings in the Spartan 3 devices and documentation.Article: 101019
Antti When you get a timeout the OPB bus master should release the bus removing "SELECT" and other signals from active to their inactive state of all "0"s. I'm guessing the DDR module isn't passing back the XFERACK as expected. If you have done this manually check the timeout signals are wired into the array correctly. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Antti" <Antti.Lukats@xilant.com> wrote in message news:1145862564.498508.148690@j33g2000cwa.googlegroups.com... > Hi > > does anyone know what should happen on read access to DDR > memory space when external connections to DDR memory > are not correct? I am troubleshooting a custom board and > what I see is that OPB DDR controller makes total OPB bus > freeze on first DDR read access. ToutSup=1 and then nothing > happens. In the datasheet DQS strobe is going to WREN of > read fifo so I could think a missing DQS from external chip could > cause bus freeze, but I am not really sure as it is not described > in the datasheet (eg what should happen on missing DQS). > > I have tried all DDR controllers from EDK 8.1 > PLB_DDR > OPB_DDR > OPB_MCH_DDR > and all seem to have similar freeze behaviour > the DCMs all work (tested) and the EDK system > also works - well until first read to DDR space > > any helpful hints? > > Antti >Article: 101020
Antti wrote: > Hi > > does anyone know what should happen on read access to DDR > memory space when external connections to DDR memory > are not correct? I am troubleshooting a custom board and > what I see is that OPB DDR controller makes total OPB bus > freeze on first DDR read access. ToutSup=1 and then nothing > happens. In the datasheet DQS strobe is going to WREN of > read fifo so I could think a missing DQS from external chip could > cause bus freeze, but I am not really sure as it is not described > in the datasheet (eg what should happen on missing DQS). It freeze ... ie, never acks the transfer. We use the ddr controller from EDK (without any ipic/ipif, just the bare controller that's common to plb_ddr, opb_ddr & co) and if the phase shift of the second dcm is off, it never acks and thus freeze. SylvainArticle: 101021
Rick, Why not just email all of this to Steve Knapp directly? Or me or Peter for Virtex parts? Seems that if you'd like to help us by pointing out anything confusing or inconsistent, you could get it to the right party in one step. I agree with you that answers should be scrubbed for any update to a document. It is the little things that drive us all crazy. Austin rickman wrote: > I still have not completely figured out the pull up resistors on the > Spartan 3 chips. It would appear that the data sheet has never been > thoroughly reviewed for omissions and errors. Some of the information > that should be clearly indicated in any number of places is missing > and/or misleading. > > "A Low logic level on HSWAP_EN activates the pull-up resistors on all > I/Os during configuration." Does this include the dedicated > configuration signals? How about the dual purpose configuration pins? > Or is it just the User IO? > > I found this sentance to be especially unenlightening... > > "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, > HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a > pull-up resistor to HSWAP_EN during configuration, regardless of the > value on the HSWAP_EN pin." > > What does a "pull-up resistor to HSWAP_EN" mean??? Why would TDO have > (or need) a pull up to any value since it is a full time output? > > Why does Xilinx make it so hard to get the all important details on a > part that has been in full production for so long? They just updated > the Spartan 3 data sheet this month! Why wasn't the information that > they know is lacking included? I say they know info is lacking because > you can find it in an answer record if you know to look for it. > > I may put up a web page detailing all the short comings in the Spartan > 3 devices and documentation. >Article: 101022
Devlin wrote: > When I complied any project with ISE 8.1 webpack with SP3, I got > warnings like below: > > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch_map.ngm" line 0 > duplicate design unit: 'Module|stopwatch' > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch.ngc" line 0 duplicate > design unit: 'Module|stopwatch' > > Does anyone know what does it mean? or how can I avoid this? > thanks a lot. You're not alone. I get this warning, too. And I don't know what it means or how to avoid it either! -Dave PollumArticle: 101023
John_H wrote: > It's possible to build teeny, tiny CAMs. The information Austin pointed > out gives you an idea of what you can accomplish with FPGA resources > that can apply to all FPGAs, not just Xilinx. > > If you need a few entries, you might be okay. If you need small > entries, you may be able to do many more. However, if you plan decode 32 bit or 128 bit IP addresses, an FPGA solution will likely cost just as much and not work quite as well as a real CAM. -- Mike TreselerArticle: 101024
Robin Bruce wrote:
> I'd like to canvass opinion here. I'm sure opinions will vary greatly.
> The question is:
> Is is time to create a new group devoted entirely to general-purpose
> reconfigurable computing.
When this newsgroup is overloaded with
postings regarding reconfigurable computing,
such a new group might be indicated.
-- Mike Treseler
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Compare FPGA features and resources
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