Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, today TobiFlex released his new turbo core for the CPC TREX. http://www.symbos.de/trex.htm The CPC TREX is a complete FPGA-based implementation of the classic computer Amstrad CPC on a Terasic T-REX C1 board ( http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=14&Revision=018&PartNo=1 ). The great thing is, that TobiFlex also released the complete source code as a Quartus Snapshot! The core includes his new Z80 implementation which is much smaller, faster and more compatible than the previous OpenCore T80. So everyone, how is searching for a better Z80 core, should have a look on it. If you switch the CPC TREX into Turbo Mode you will have a system with 24MHz power! This is really a little bit crazy fast. The update also contains a new start-up system. The Starter-SymbOS is included directly in the flash file and doesn't need to be loaded with the 6502-based big boot from CF card any more. That means, booting the TREX is much faster now. The Starter-SymbOS is the "risc-version" of the brand new Release 1.0. Please download the update and the TREX turbo core source code here: http://www.symbos.de/trex.htm#marke3 CU, ProdatronArticle: 101601
After making some changes to some hardware that used to synthesize, xst now seg faults. This is using the Xilinx EDK flow. The error looks like: ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... ./synthesis.sh: line 3: 25715 Segmentation fault xst -ifn system_xst.scr I am wondering specifically if this is happening because I am trying to add too many slaves to my PLB bus. I increased the max number of slaves allowed on the PLB bus and I am now trying to put 33 slaves on there. Is that a no-no? My other thought was that I could be trying to use more BRAM memory than is available on my device. Would it be possible get a seg fault in that case? Thanks for any pointers. MattArticle: 101602
"Matt Blanton" <notreally@myemail.com> schrieb im Newsbeitrag news:e3au7r$mrt$1@solaris.cc.vt.edu... > After making some changes to some hardware that used to synthesize, xst > now > seg faults. This is using the Xilinx EDK flow. The error looks like: > ========================================================================= > * Advanced HDL Synthesis * > ========================================================================= > > Advanced RAM inference ... > Advanced multiplier inference ... > Advanced Registered AddSub inference ... > ./synthesis.sh: line 3: 25715 Segmentation fault xst -ifn > system_xst.scr > > I am wondering specifically if this is happening because I am trying to > add > too many slaves to my PLB bus. I increased the max number of slaves > allowed > on the PLB bus and I am now trying to put 33 slaves on there. Is that a > no-no? My other thought was that I could be trying to use more BRAM memory > than is available on my device. Would it be possible get a seg fault in > that case? Thanks for any pointers. > > Matt 33 !? thats sounds like trouble! why do you need them on PLB bus? add PLB-OPB bridge (or more than one) and place some there AnttiArticle: 101603
Rainier wrote: > I want to open an ISE 8.1 project in ISE 7.1, but it seems impossible. > and there's even no compatibility property in the save option. > > My project has verilog, vhdl, schematic and coregen files. > > thanks. > I guess you need to create a new project and add the source files.Article: 101604
I want to learn how to create my own fixed netlist ip cores in Xilinx ISE 8.1 using segments of my existing vhdl source projects. Does anyone know of a decent reference I can turn to?Article: 101605
Kolja Sulimma wrote in news:4448ed30$0$18265$9b4e6d93@newsread2.arcor-online.net : "[..] Formal model checking and property checking are becoming mainstream for hardware development but are hardly ever used for software development. [..]" There is a difference between being mainstream and being available. Formal methods have existed for a long time for software. Just as one should not be willing to take a software developer opposed to formal methods, one should not be willing to take a hardware developer who has only acquired exposure to formal methods because of a trend instead of actively appreciating the need for formal methods. On Thu, 27 Apr 2006, Falk Salewski wrote: "[..] I am also of the opinion that applications realizing hard real-time parallel functionality are easier to verify on a device allowing real parallelism. [..]" Of course implementing parallelism with real parallelism is easier, but verifying something whether it is implemented with true parallelism or interleaved sequential code should take the same effort no matter the implementation: check whether the inputs and the outputs match.Article: 101606
Antti wrote: > Hi Folks, > > got interested to test it out, and well I have VERY preliminary results > - all > the test setup was done within 30 minutes, so it's just proof of > concept: When I tested a (red?) LED a few weeks ago ( similar idea?) the uA meter in sunlight indicated some few uA. So yes, it does change, but not by much! Two leds might allow a Push-pull type drive, but it would be a challenge to have a stable setup that could be LED out, or LED in ? -jgArticle: 101607
Sometines when it looks like a flip-flop not changing, it actually changed twice, forard and then back. That could be the result of a glock glitch. A flip-flop can react to a 2-ns clock double-transition that are difficult to see on the scope. Peter AlfkeArticle: 101608
Hello,
I have been working on a project and the submission date is
due very soon. Now I am having some problems which need to be
addressed. Here I go,
I am using digilent Spartan 3 board for my project. My
project needs to operate on the data sent by PC. I am using PCs
parallel port to send and receive data. (I have a code written in C
which uses outportb() and inportb() to exchange data. on the otherside
in VHDL i have a data bus which is bi-directional.. inout... )
now the problem is the voltage levels these two operate at. FPGA
operates at 3.3V and parallel port uses 5V to represent logic values...
I saw a parallel I/O board (PIO1) on digilent website, but now have no
time to order one...
So what is the best way to construct a simple interface which can be
used.
Also can I directly connect the PC parallel port to spartan 3 boards
expansion slot??
if no, please suggest me a simple interface (some level shifter which
has to be bi-directional, or alternate solution) which I can use...
I need something similar to the digilent POI1 board.
http://www.digilentinc.com/Products/Detail.cfm?Prod=PIO1&Nav1=Products&Nav2=Accessory
Can i construct this board and use it? (ofcourse without the JTAG
module) if yes, please tell me in this schematic
http://www.digilentinc.com/Data/Products/PIO1/DmodPio1_sch.pdf what is
IC2. seems like a voltage regulator. but can you tell me which
regulator is this?
I feel i can construct this interface which consists of voltage
dividers, this voltage regulator and connections.. but please tell me
whether this will work for bi-directional data???
waiting for your reply
thankyou
Shailesh.
Article: 101609kulkarni.shailesh@gmail.com wrote: > Hello, > I have been working on a project and the submission date is > due very soon. Now I am having some problems which need to be > addressed. Here I go, > > I am using digilent Spartan 3 board for my project. My > project needs to operate on the data sent by PC. I am using PCs > parallel port to send and receive data. (I have a code written in C > which uses outportb() and inportb() to exchange data. on the otherside > in VHDL i have a data bus which is bi-directional.. inout... ) > > now the problem is the voltage levels these two operate at. FPGA > operates at 3.3V and parallel port uses 5V to represent logic values... > > I saw a parallel I/O board (PIO1) on digilent website, but now have no > time to order one... > > So what is the best way to construct a simple interface which can be > used. > Also can I directly connect the PC parallel port to spartan 3 boards > expansion slot?? > if no, please suggest me a simple interface (some level shifter which > has to be bi-directional, or alternate solution) which I can use... > > I need something similar to the digilent POI1 board. > http://www.digilentinc.com/Products/Detail.cfm?Prod=PIO1&Nav1=Products&Nav2=Accessory > > Can i construct this board and use it? (ofcourse without the JTAG > module) if yes, please tell me in this schematic > http://www.digilentinc.com/Data/Products/PIO1/DmodPio1_sch.pdf what is > IC2. seems like a voltage regulator. but can you tell me which > regulator is this? > I feel i can construct this interface which consists of voltage > dividers, this voltage regulator and connections.. but please tell me > whether this will work for bi-directional data??? > > waiting for your reply > thankyou > Shailesh. > Why not just use the RS-232 port?Article: 101610
Have you looked at xapp717? They connect a few registers to the ppc using a "subset" of the apu interface, and it only takes a page or so of code. -GregArticle: 101611
Eli Hughes wrote: > kulkarni.shailesh@gmail.com wrote: > > Hello, > > I have been working on a project and the submission date is > > due very soon. Now I am having some problems which need to be > > addressed. Here I go, > > Why not just use the RS-232 port? Because his homework assignment was to use the parallel port. -aArticle: 101612
Andy Peters <Bassman59a@yahoo.com> wrote: > Eli Hughes wrote: > > kulkarni.shailesh@gmail.com wrote: > > > Hello, > > > I have been working on a project and the submission date is > > > due very soon. Now I am having some problems which need to be > > > addressed. Here I go, > > > > Why not just use the RS-232 port? > Because his homework assignment was to use the parallel port. Perhaps he needs to acchive datarates far above 1MBaud? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 101613
kulkarni.shailesh@gmail.com wrote: > Hello, > I have been working on a project and the submission date is > due very soon. Now I am having some problems which need to be > addressed. Here I go, > > I am using digilent Spartan 3 board for my project. My > project needs to operate on the data sent by PC. I am using PCs > parallel port to send and receive data. (I have a code written in C > which uses outportb() and inportb() to exchange data. on the otherside > in VHDL i have a data bus which is bi-directional.. inout... ) > > now the problem is the voltage levels these two operate at. FPGA > operates at 3.3V and parallel port uses 5V to represent logic values... > > I saw a parallel I/O board (PIO1) on digilent website, but now have no > time to order one... Series resistors ( wire between M-F DB25 as a cascade connector ) should be good enough. Add clamp diodes if you like. You only need microsecond region times, and probably do not care about power loss. -jgArticle: 101614
Robin Emery wrote: > Oh, and just to qualify what I said in the last post... > > I am able to see which state the FSM is in on the logic analyser, and > when the FSM moves from a state in which it will change the value of > the output pin into the next, the signal does not change. There is no > conditional expression or anything that would prevent it from changing > the signal... > > -------------- > > Peter, thank you for your suggestion. I'll see what I can do, but I too > would expect incorrect VHDL. I am unable to find an error, however! > > --------------- > > If you would like some more information, I'll happily post it. Something simple like making sure you are probing the right pin ? Give it some simple code that toggles the pin, and verify you see that, and alias the expected OP onto some other pins, and see if _any_ change ? -jgArticle: 101615
I was hoping to avoid that because I am using a custom hardware module to control plb bram controllers which write to the BRAMs. I assume moving to the OPB will require a lot of changes to my hdl code and XPS project files, but I may have to end up doing that if the number of slaves I have on the PLB ends up being the problem. Thanks for the idea. Matt "Antti Lukats" <antti@openchip.org> wrote in message news:e3aub6$6bj$1@online.de... > "Matt Blanton" <notreally@myemail.com> schrieb im Newsbeitrag > news:e3au7r$mrt$1@solaris.cc.vt.edu... >> After making some changes to some hardware that used to synthesize, xst >> now >> seg faults. This is using the Xilinx EDK flow. The error looks like: >> ========================================================================= >> * Advanced HDL Synthesis * >> ========================================================================= >> >> Advanced RAM inference ... >> Advanced multiplier inference ... >> Advanced Registered AddSub inference ... >> ./synthesis.sh: line 3: 25715 Segmentation fault xst -ifn >> system_xst.scr >> >> I am wondering specifically if this is happening because I am trying to >> add >> too many slaves to my PLB bus. I increased the max number of slaves >> allowed >> on the PLB bus and I am now trying to put 33 slaves on there. Is that a >> no-no? My other thought was that I could be trying to use more BRAM >> memory >> than is available on my device. Would it be possible get a seg fault in >> that case? Thanks for any pointers. >> >> Matt > > 33 !? thats sounds like trouble! > why do you need them on PLB bus? add PLB-OPB bridge (or more than one) > and place some there > > Antti >Article: 101616
On 3 May 2006 08:57:58 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >Hi Folks, > >got interested to test it out, and well I have VERY preliminary results >- all >the test setup was done within 30 minutes, so it's just proof of >concept: > >Test setup > >1) Xilinx S3 FPGA (a GOP module from oho-elektronik) >2) IOPad oscillator (using 2 io pins, see at the end of posting) >3) green 0805 SMD LED >4) JTAG Frequence meter software and ip-core, one channel connected to >the IOPad oscillator (the frequence meter application is the same as at >gforge.openchip.org) > >first I tried to put the LED between the 'diff' outputs of the iopad >oscillator, but that did not have good results, by placing the LED with >one terminal on X2 and other >one just unused (put pullup enable) FPGA pin I was able to see light >influence on the oscillator frequency. the oscillator did run at 35MHz, >light from window or then covered up with paper caused a frequence >change of 80KHz, well that isnt much but I guess my setup wasnt not the >best to get the 'sensor effect' out - still the frequence change was >cleary observable. > >of course the current test setup is sensitive also to capacitance so >using your finger to cover up the LED will have more capacitive impact >then light dependant >changes. Anyway with proper bias and (series) resistor the light >dependancy of an normal LED should be very easy to measure with an FPGA I saw a neat trick recently for effectively all-digital measurement of light using a LED. The gist of it was to charge the junction capacitance of a LED up, then measure the time it took to discharge - higher light-levels increasing discharge rate. This was implemented on a PIC but should be equally do-able on a FPGA.Article: 101617
Benjamin Todd wrote: > You can't have internal tristates, unless you're using old Virtex technology > They'll be replaced by equivalent circuits. (like MUXES) (if I recall > correctly) > Ben > "samtee" <samxx@yahoo.com> wrote in message > news:4458b047$0$27288$c3e8da3@news.astraweb.com... > >>Hi, >>I use ISE8.1 (webpack) in Verilog. I try to use inout port. Sample code: >>module ....(... inout wire[7:0] data, ...); >>reg [7:0] buff; >>reg hiZ; >> >>assign data=hiZ ? 8'bzzzz_zzzz:buff; >>.... >>endmodule >> >>When I use xst to synthesis, and when I look at RTL logic , I cannot find >>tristate buffer in the circuit. And when I simulate with ModelSIM XE 6.0d >>(eval version), I got xxxx instead of zzzz. >> >>Thank you, >>Sam > > > Thank you fro your respond. Then, how can I use inout port to conect to other module? Sam.Article: 101618
On Wed, 03 May 2006 23:26:02 GMT, Mike Harrison <mike@whitewing.co.uk> wrote: >On 3 May 2006 08:57:58 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > >>Hi Folks, >> >>got interested to test it out, and well I have VERY preliminary results >>- all >>the test setup was done within 30 minutes, so it's just proof of >>concept: >> >>Test setup >> >>1) Xilinx S3 FPGA (a GOP module from oho-elektronik) >>2) IOPad oscillator (using 2 io pins, see at the end of posting) >>3) green 0805 SMD LED >>4) JTAG Frequence meter software and ip-core, one channel connected to >>the IOPad oscillator (the frequence meter application is the same as at >>gforge.openchip.org) >> >>first I tried to put the LED between the 'diff' outputs of the iopad >>oscillator, but that did not have good results, by placing the LED with >>one terminal on X2 and other >>one just unused (put pullup enable) FPGA pin I was able to see light >>influence on the oscillator frequency. the oscillator did run at 35MHz, >>light from window or then covered up with paper caused a frequence >>change of 80KHz, well that isnt much but I guess my setup wasnt not the >>best to get the 'sensor effect' out - still the frequence change was >>cleary observable. >> >>of course the current test setup is sensitive also to capacitance so >>using your finger to cover up the LED will have more capacitive impact >>then light dependant >>changes. Anyway with proper bias and (series) resistor the light >>dependancy of an normal LED should be very easy to measure with an FPGA > >I saw a neat trick recently for effectively all-digital measurement of light using a LED. >The gist of it was to charge the junction capacitance of a LED up, then measure the time it took to >discharge - higher light-levels increasing discharge rate. This was implemented on a PIC but should >be equally do-able on a FPGA. > Randomly-grabbed led's measured... red 32 pF yel 9 grn 10 white 42 JohnArticle: 101619
Write it as several 8-bit vectors or as one n*8 bit vector. You can't pass arrays in Verilog or Verilog2001. There's also comp.lang.verilog. "CMOS" <manusha@millenniumit.com> wrote in message news:1146677836.868136.228860@g10g2000cwb.googlegroups.com... > hi, > > using verilog how to write a module which has an inpput port for an > array of 8 bit signals and how to write a test bench for it. > > thank you. > CMOS >Article: 101620
Glory and riches are showered upon those who successfully factor one of
the RSA Challenge Numbers (see note [1]) ;-). I would like to be the
first to factor an RSA number using a standalone FPGA development
board(s) (ie; not connected to a conventional computer).
The RSA Challenge numbers have traditionally been solved by networks of
supercomputers using a distributed Number Field Sieve (NFS) or similar
method. Sieving is unfortunately not suited to FPGA implementation, but
there is another integer factorization method called the Elliptic Curve
Method (ECM, see note [3]) that I think might stand a chance of cracking
RSA-704. I have therefore designed and tested a Verilog implementation
of ECM with a compile time bus-width specification (ie; `define L 704)
so that it's easy to determine how the LUT requirement increases as I
change the bus width. I've optimized the circuit for gate count to the
extent of multiplexing everything that is used more than once (multiply,
divide, modulo, etc) - a process that almost brought tears to my eyes at
one point, because I had to eliminate several areas that naturally lent
themselves to parallelization.
Even so, the design requires far more LUTs than are currently available
from anyone as far as I know. I presently have Xilinx xc3s500e and Actel
ProASIC3E A3PE600 development boards, but I can't compile the design for
a 704 bit bus-width because I get the error message in Note [4] below (I
also get a similar message from the Actel synthesizer). I *can* compile
the design for a 384 bus-width however. Using a Xilinx 3s4000 as the
target device (even though I only have a 3s500) with a 384 bit
bus-width, I get the following Device utilization summary:
---------------------------
Selected Device : 3s4000fg676-4
Number of Slices: 49176 out of 27648 177% (*)
Number of Slice Flip Flops: 52253 out of 55296 94%
Number of 4 input LUTs: 83797 out of 55296 151% (*)
Number of bonded IOBs: 18 out of 489 3%
Number of GCLKs: 1 out of 8 12%
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
---------------------------
This would lead me to believe that my design would require at least
101,376 LUTs, and probably more depending on how much of the FPGA is
consumed by routing. Since the Xilinx 3s4000 has 55296 LUTs and 27648
slices, I imagine a part with twice that number of slices & LUTs (a
Xilinx 3s8000 perhaps?) would be needed to fit my design. Anyone care to
hazard a guess as to if/when such a monster might be available?
Also, thus far the longest number that has been factored with ECM is
only 66 decimal digits (see Note [3]). If RSA-704 (212 decimal digits)
were factored, it would set a new record for ECM factoring also.
If such a device did become available, my only hope for acquiring the
requisite hardware/software would be to work out a deal with the FPGA
vendor or someone to lend me the necessary development board and s/w
tools in exchange for the potential fame and glory, since I am but a
humble retired engineer/hobbyist. :-)
Ron
_________________
Notes:
[1] RSA Challenge Numbers:
http://www.rsasecurity.com/rsalabs/node.asp?id=2093
[2] Factoring Methods:
http://mathworld.wolfram.com/PrimeFactorizationAlgorithms.html
[3] Elliptic Curve Factorization Method
http://mathworld.wolfram.com/EllipticCurveFactorizationMethod.html
[4] When synthesizing ECM with a 704 bit bus-width for the Xilinx
xc3s4000-4fg676, I get:
ERROR: Portability:3 - This Xilinx application has run out of memory or
has encountered a memory conflict. Current memory usage is 2092148 kb.
Memory problems may require a simple increase in available system
memory, or possibly a fix to the software or a special workaround. To
troubleshoot or remedy the problem, first: Try increasing your system's
RAM. Alternatively, you may try increasing your system's virtual memory
or swap space. If this does not fix the problem, please try the
following: Search the Answers Database at support.xilinx.com to locate
information on this error message. If neither of the above resources
produces an available solution, please use Web Support to open a case
with Xilinx Technical Support off of support.xilinx.com. As it is
likely that this may be an unforeseen problem, please be prepared to
submit relevant design files if necessary.
ERROR: XST failed
Process "Synthesize" did not complete.
Article: 101621Mike Harrison wrote: > > I saw a neat trick recently for effectively all-digital measurement of light using a LED. > The gist of it was to charge the junction capacitance of a LED up, then measure the time it took to > discharge - higher light-levels increasing discharge rate. This was implemented on a PIC but should > be equally do-able on a FPGA. Nice idea, but would need care on devices without Schmitt Pins. Slow edges and FPGA are uneasy bedfellows :) -jgArticle: 101622
Ron <News5@spamex.com> wrote: >Glory and riches are showered upon those who successfully factor one of >the RSA Challenge Numbers (see note [1]) ;-). I would like to be the >first to factor an RSA number using a standalone FPGA development >board(s) (ie; not connected to a conventional computer). >The RSA Challenge numbers have traditionally been solved by networks of >supercomputers using a distributed Number Field Sieve (NFS) or similar >method. Sieving is unfortunately not suited to FPGA implementation, but >there is another integer factorization method called the Elliptic Curve >Method (ECM, see note [3]) that I think might stand a chance of cracking >RSA-704. I have therefore designed and tested a Verilog implementation >of ECM with a compile time bus-width specification (ie; `define L 704) >so that it's easy to determine how the LUT requirement increases as I >change the bus width. I've optimized the circuit for gate count to the >extent of multiplexing everything that is used more than once (multiply, >divide, modulo, etc) - a process that almost brought tears to my eyes at >one point, because I had to eliminate several areas that naturally lent >themselves to parallelization. Why not use bricks with matrix or bus wired fpgas?, and let them share the load. They got lvds etc.. so they can ship data quick within a board. If one needs more horsepower one simple adds another brick to the backplane.Article: 101623
CMOS- > using verilog how to write a module which has an inpput port for an > array of 8 bit signals and how to write a test bench for it. Wait until you try to initialize your arrays. Try this search in Google Groups: initializing array of registers in XST group:comp.arch.fpga It has been suggested that RAMs in general work better and are more flexible than arrays or registers or wires. I'm not sure though on whether it's possible to pass a RAM or RAM "base address" to a module. -JeffArticle: 101624
Sam- This type of coding: assign data = hiZ ? 8'hzz : (buf1 ? buff_1 : 8'hzz); assign data = hiZ ? 8'hzz : (buf2 ? buff_2 : 8'hzz); works Ok, it's just not implemented using actual internal tri-states. Don't worry, tools handle it for you. ISE 7.1.04 may give warnings about "the following tristate(s) are NOT replaced by logic..." and I opened a webcase about that, but the word back is "just ignore". -Jeff
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z