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pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: >What kind of cpu resources does fpga "compilation" (Analyse, Synthesis, etc..) >use on a cpu..? > >Integer/Branch/Bitshifting..? >Floating point..? >Will a pipeline cpu greatly improve speed..? > > > I'm sure there's no floating point, except to report % usages at the end. Pipelining always helps, but anything newer than a 286 has at least some level of pipelining. Plenty of main memory and cache will help greatly. Swapping to disk will kill this type of large database sorting task. JonArticle: 101676
Does anybody know of an IP vendor that sells the 87C51 & 87C52 IP cores for FPGA's? I have gone through the following IP vendor sites but couldn't find what I was looking for. I did find various forms of 8051 and 8052, though! 1) Digital Core Design 2) Elliptic Cores 3) Eureka Tech 4) Northwest Logic Cores 5) 4i2i Tech 6) Cast 7) Helion Tech 8) Inicore 9) Intelliga 10) Memec Design (Avnet) 11) MorethanIP Tech 12) Evatronix 13) EInfoChips Any help would be great!!! Thanks a lot.Article: 101677
Austin Lesea wrote: > We already sponsor this sort of research at many universities and schools. > If you want to go play, ... Play? Research? How insulting. Didn't you read my original message at all? There is no play or research involved. I suppose since this is a hobby of mine, it could be considered "play" in a sense, but there is also a $30,000 reward for factoring RSA-704 which isn't normally associated with "play". I have already designed and tested my circuit (both in simulation and on a *REAL* FPGA, but using a smaller bus width). There is absolutely NO research whatsoever involved, it's purely a pragmatic matter of implementation and being able to afford your overpriced software design tools on my retirement savings. For what it's worth, I've had Fermat's Method of integer factorization running on a Lattice LFEC20E FPGA for a couple of weeks so far (it's the only algorithm small enough to fit on the Lattice board), but since it's a sub-optimal factorization method, I have little or no hope that it will ever find the answer. ECM is another matter however, because it's well known and respected in numerical analysis circles. That and its relative simplicity compared with NFS is the reason I chose it. Gads, play indeed. RonArticle: 101678
Sid wrote: > Does anybody know of an IP vendor that sells the 87C51 & 87C52 IP cores > for FPGA's? > > I have gone through the following IP vendor sites but couldn't find > what I was looking for. I did find various forms of 8051 and 8052, > though! A strange question. Is it the missing 'C' or the missing '7' that is bothering you ? 'C' = CMOS tag, and even tho these cores are called 8051 and 8052, they are not NMOS ROM cores, but named thus to show 128 and 256 byte models. ( and likely the Timer2 ) '7' = OTP, which covers the CODE storage. Most FPGA cores handle the Code separately, either off-chip, or into Block RAM. Typically here, the HEX file is morphed into the bitstream, and downloaded, and the FPGA has BRAM holding correct CODE when it comes out of configure. Summary: Those cores will behave like 87C51 and 87C52 [except you will be able to change the code! :)] -jgArticle: 101679
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:4bv0puF12s3kqU1@individual.net... > > The downside to this template is that it clock enables > everything in the process -- too restrictive for me. > Hi Mike, I try to make sure every process (and, of course, every entity) has an enable. Even if the enable is set to '1' in the code, it makes it a lot easier to reuse in future designs with faster clocks. Sadly, I don't always remember to do this. :-( Cheers, Syms. p.s. Jan, sorry for wandering off topic!Article: 101680
"avishay" <avishorp@yahoo.com> writes: > Another type of problem is the SOPC builder. The SOPC builder takes the > system specification from PTF files (as KJ mentioned) and copies HDL As I mentioned earlier in news:<87psj0kulu.fsf@gustad.com> I usually do the following to build a new implementation: cvs checkout designname cd designname/impl/somefpgadevicename make This inlcudes designs based upon the SOPC builder. The PTF file it checked into CVS together with the C source files. Make will use the SOPC builder scripts to generate everything from the PTF file. The generated (or copied) HDL files are not checked in. > files from the relevant library into the project directory. These > copied files are not strictly sources, but rather intermediate > products, and as such they should not be under the soruce control (they I don't keep the generated files under source control since they can be regenerated using the PTF file and SOPC builder. > should, in fact, but they should be controlled by the one that wrote > the component, not the one using them). After SOPC builder has finished > its run, there is no way (to my understanding) to distinguish between > true source files and those who were copied. They will both show up the > same in the said report. A possible solution might be to instruct SOPC > builder to copy its files to a directory other than the project root (I > think it would be much easier to manage also), but I don't know how to > do that. Can't you keep the sources for the components in a different directory (also under your source control system) and refer to them from your SOPC run? You can then reuse the components for different projects as well. This is similar to how the components supplied with SOPC builder are handled (except that they are a part of the SOPC distribution and not under a source control system). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 101681
http://www.emsec.ee.ucla.edu/ Austin Lukasz Salwinski wrote: > Austin Lesea wrote: > >> Ron, >> >> We already sponsor this sort of research at many universities and >> schools. >> >> If you want to go play, there are many excellent programs in graduate >> education on the subject. >> >> I am aware of a very active group at UCLA. >> >> Austin > > > > uh... would you mind giving me a pointer to these guys ? > > lukaszArticle: 101682
The easiest way is to use the new platform flash PROMs for configuring the device. You put them in the JTAG scan chain and the Xilinx cables (Parrallel V3, V4 or USB) can program them -ELi Jon Elson wrote: > > > Jim_L_Williams@hotmail.com wrote: > >> Hello, >> >> I am new to FPGAs and was wondering, how do fpga store the bitstream? >> I >> mean, with CPLD, I don't need any special memory chips to program them >> and >> they retain their programming, but for FPGA, I see that they seem to >> need >> some flash or prom to store the bitstream, which then loads into the >> FPGa. >> Is this the case? If so, what type of memory is used, and how do I use >> >> Xilinx webpack to program it? >> >> > Many mid-sized Xilinx FPGAs use serial EPROMs, most can also handle > a parallel EPROM if you provide an address counter. I've been working with > 5 V Spartan devices, and use Xilinx's own 17128 through 17256 and 17S20 and > 17S30 serial EPROMs, which use a direct-wired connection to the FPGA. > They have some 3.3 V versions that are used with the newer FPGAs that have > a 3.3 V interface. This is by far the simplest setup for mid-size FPGAs > such as the Spartan series. > > You can't program these directly with the WebPack software. I use a Xeltek > universal device programmer, and it is very good, and pretty cost > effective. > Xilinx does have a link on their web site to a device programmer that > only supports > their own PROM products, but the Xeltek is only just a little more > expensive > and so much more flexible. > > Jon >Article: 101683
Ron, I play everyday. Play is what some people call work who don't enjoy what they do. My oldest brother Ron had a great attitude: if you don't look forward to walking through the door in the morning: don't - go get another job. To help you win a prize is not in the realm of 'sponsored tax deductible activities' that Xilinx is inclined to support. I meant no disrespect. If you call it "hard work" then that is fine by me. That prize for factoring is an incentive to continue the research in cypher breaking, and improving computational methods. We need no such prize: our customers have real problems (3-D Xray imaging, 3G base stations, joint task strike fighter plane, Mars Rovers, gigabit routers, etc.) that need our devices every day to solve their problems. That prize was 1.73 billion dollars (US)last year (Xilinx sales). If you feel that you can win the prize, you should invest your own money, and build the "solver." I have no doubt it will be done by someone, and soon (since there are published papers on how to use FPGAs to do this now for less money). Austin Ron wrote: > Austin Lesea wrote: > >> We already sponsor this sort of research at many universities and >> schools. >> If you want to go play, ... > > > Play? Research? How insulting. Didn't you read my original message at > all? There is no play or research involved. I suppose since this is a > hobby of mine, it could be considered "play" in a sense, but there is > also a $30,000 reward for factoring RSA-704 which isn't normally > associated with "play". > > I have already designed and tested my circuit (both in simulation and on > a *REAL* FPGA, but using a smaller bus width). There is absolutely NO > research whatsoever involved, it's purely a pragmatic matter of > implementation and being able to afford your overpriced software design > tools on my retirement savings. > > For what it's worth, I've had Fermat's Method of integer factorization > running on a Lattice LFEC20E FPGA for a couple of weeks so far (it's the > only algorithm small enough to fit on the Lattice board), but since it's > a sub-optimal factorization method, I have little or no hope that it > will ever find the answer. ECM is another matter however, because it's > well known and respected in numerical analysis circles. That and its > relative simplicity compared with NFS is the reason I chose it. > > Gads, play indeed. > > RonArticle: 101684
C'mon Ron, have a sense of perspective. You claim it is not research because it is already well-understood, and it is not play (but rather a hobby), because you want to make money by winning the prize. And Austin told you that you have "competition", since several universities try to do the same thing. Maybe we can find a way, but please don't be too thin-skinned. Peter AlfkeArticle: 101685
Hi Ron, I have four suggestions for you: 1. there is a huge difference between "integer factorization" and "factorization of RSA numbers". Methods for the first one that do not work for the second one are among others "Fermat's Method" and EC-factorization (but there are some exceptions). 2. get a cheap medium size FPGA. Altera CycloneII or Xilinx Spartan 3 on a cheap board. Re-write your code until it fits, I have seen this sort of stuff in mush smaller devices than 3s4000. read some articles on, e.g. CPU design. And learn how to use your FPGA! 3. I have already seen some of your code and I suggest you publish it somewhere so people can learn from it and/or help improving it. 4. 30000 USD is probably a tiny fraction of what it will cost to factor a RSA-704 number. my guess is that it would cost between 50 to 100M USD today, and that does not include the billions that have already been used for research in universities and various TLAs... Of course, in your case the journey is more rewarding than the contest reward itself. You will learn a lot, as I did 10-15 years ago when I was first introduced this stuff. good luck, and have fun!Article: 101686
"Sid" <sid.gaddam@gmail.com> writes: > Does anybody know of an IP vendor that sells the 87C51 & 87C52 IP cores > for FPGA's? > > I have gone through the following IP vendor sites but couldn't find > what I was looking for. I did find various forms of 8051 and 8052, > though! The 87C51 and 87C52 are just the CMOS versions of the 8051 and 8052 with onboard EPROM program memory. You should be able to use an 8051 or 8052 CPU core, and use a blockram for the program memory.Article: 101687
shawnn@gmail.com wrote: > Ok I did some reading and answered my own question. This is a really > great article -- > > http://www.eetimes.com/editorial/2000/design0003.html Peter, after reading your article, I have a much better understanding of FIFOs, especially regarding the FULL and EMPTY flags. When I reached the end of the article, and saw your bio (invented the first FIFO IC, the Fairchild 3341), I thought "that's why he knows so much about FIFOs"! -Dave PollumArticle: 101688
Paul wrote:
> hi, there,
>
> I want to set one of I/O pin as 3 state, how can I do this in Xilinx
> FPGA using Verilog?
>
> thanks
You may want to ask in comp.lang.verilog.
VHDL code:
-- this makes the output "out_pin" hi-impedance when "Z_enable" is a
'1'.
-- Otherwise, "out_pin" is assigned the value of "some_bit".
out_pin <= 'Z' when Z_enable = '1'
else some_bit;
HTH
-Dave Pollum
Article: 101689Some time ago I did some experimentation (for a very cost sensitive application) with a Spartan 3 part using an LVDS differential input as a voltage comparator for a crude delta sigma ADC. The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the 3.3v supply and the differential input voltage was (obviously) limited to whatever it took drive the LVDS input one way or the other. It worked fine. Now the customer says he wants to use Cyclone II. I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have to provide a 2.5v supply just for this one input. So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator) input on 3.3v biased at 1.65v. After an age I get the answer no, but I could use an LVPECL standard <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is outside the LVPECL standard common mode range and LVPECL is only available on dedicated clock input pins anyway. So I ask the question again and after another age get told no, LVDS has to run on 2.5v and no more than 650mV differential input with no further explanation. I just read through the Cyclone II Device Handbook again and find it says "Cyclone II devices have one set of VCC pins (VCCINT) that power the internal device logic array and input buffers that use the LVPECL, LVDS, HSTL, or SSTL I/O standards." So if I believe this the Vccio supply is irrelevant for LVDS receivers and the FAE was talking crap again. Can anyone confirm this and has anyone experience of using LVDS inputs as voltage comparators on Cyclone II (or Spartan 3/3e for that matter). --Article: 101690
Similar to CPLDs, there are some non-volatile FPGAs that have on-chip flash for the configuration bitstream. You might want to check out the LatticeXP or MachXO. ~BartArticle: 101691
nospam, The LVDS input buffer in VII, II Pro, V4, Spartan 3, and 3E is a full CMOS differential comparator, than will 'function' from rail to rail. Basically, each input ties to both a nmos differential pair, AND a pmos differential pair, so that even when one, or the other is cutoff (out of its range), its complement is still in range, and will operate to sense the difference properly. Why did we go tothis extra trouble? Well, these are tiny devices, and it basically costs nothing to do it right the first time, so that you could meet or beat any standard that anyone dreams up without redesigning it. It is powered from Vccaux, not Vcco! Since Vccaux is 2.5 volts in Spartan 3, that means that an input voltage has to be in the range of 0 to 2.5 volts just to work at all (common mode range). We don't specify it use at the rails, because we can't cahracterize all the possible uses of the circuit. For low speeds, as I said, it will function. Don't complain if it doesn't switch as fast as it is specified for the LVDS specification (you are not using it there). Since every IO pin also has a giant nmos and pmos stack for the single ended driver attached to it, you also have a diode from ground to the pins, and a diode to Vcco for the bank. That means if the pin voltage tries to go below ground (negative ~ 0.5V or greater) or above Vcco (~Vcco+~0.5V) you will clamp the pin to that one diode above or below ground. You should let the customer know who is likely to provide you with more timely and useful information. They might change their mind.... Austin nospam wrote: > Some time ago I did some experimentation (for a very cost sensitive > application) with a Spartan 3 part using an LVDS differential input as a > voltage comparator for a crude delta sigma ADC. > > The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the > 3.3v supply and the differential input voltage was (obviously) limited to > whatever it took drive the LVDS input one way or the other. > > It worked fine. > > Now the customer says he wants to use Cyclone II. > > I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have > to provide a 2.5v supply just for this one input. > > So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator) > input on 3.3v biased at 1.65v. > > After an age I get the answer no, but I could use an LVPECL standard > <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is > outside the LVPECL standard common mode range and LVPECL is only available > on dedicated clock input pins anyway. > > So I ask the question again and after another age get told no, LVDS has to > run on 2.5v and no more than 650mV differential input with no further > explanation. > > I just read through the Cyclone II Device Handbook again and find it says > > "Cyclone II devices have one set of VCC pins (VCCINT) that power the > internal device logic array and input buffers that use the LVPECL, LVDS, > HSTL, or SSTL I/O standards." > > So if I believe this the Vccio supply is irrelevant for LVDS receivers and > the FAE was talking crap again. > > Can anyone confirm this and has anyone experience of using LVDS inputs as > voltage comparators on Cyclone II (or Spartan 3/3e for that matter). > > --Article: 101692
Austin Lesea wrote: > http://www.emsec.ee.ucla.edu/ > > Austin > > Lukasz Salwinski wrote: > >> Austin Lesea wrote: >> >>> Ron, >>> >>> We already sponsor this sort of research at many universities and >>> schools. >>> >>> If you want to go play, there are many excellent programs in graduate >>> education on the subject. >>> >>> I am aware of a very active group at UCLA. >>> >>> Austin >> >> uh... would you mind giving me a pointer to these guys ? >> >> lukasz thanks ;o) lArticle: 101693
Lukasz, You are welcome. The UC system in California is as impersonnal as ever: if you want a great education, you have to go and get it (no one in the UC system is there to help you - there are at least fifty students waiting to get in, so if you drop out, who cares? NO ONE!). So, if I have helped in some small way, that is great. For anyone offended by my opinion (backed by my experience of being a student, professional engineering employee, and a professor at UC Berkeley), I offer no apology. Been there, saw that. Seen that it hasn't changed (nor why should/could it?). Great schools (all campuses), highly recommended. Just don't expect anyone to hold your hand, that is all. For a kinder and gentler college experience, there is this school right across the bay from Berkeley....(also a great school). I am sure there is the equivalent in the LA basin as well... Just don't ask me to cheer for their football teams. Go Bears! Austin Lukasz Salwinski wrote: > Austin Lesea wrote: > >> http://www.emsec.ee.ucla.edu/ >> >> Austin >> >> Lukasz Salwinski wrote: >> >>> Austin Lesea wrote: >>> >>>> Ron, >>>> >>>> We already sponsor this sort of research at many universities and >>>> schools. >>>> >>>> If you want to go play, there are many excellent programs in >>>> graduate education on the subject. >>>> >>>> I am aware of a very active group at UCLA. >>>> >>>> Austin >>> >>> >>> uh... would you mind giving me a pointer to these guys ? >>> >>> lukasz > > > > thanks ;o) > lArticle: 101694
Austin Lesea wrote: > nospam, > > The LVDS input buffer in VII, II Pro, V4, Spartan 3, and 3E is a full > CMOS differential comparator, than will 'function' from rail to rail. > > Basically, each input ties to both a nmos differential pair, AND a pmos > differential pair, so that even when one, or the other is cutoff (out of > its range), its complement is still in range, and will operate to sense > the difference properly. > > Why did we go tothis extra trouble? Well, these are tiny devices, and > it basically costs nothing to do it right the first time, so that you > could meet or beat any standard that anyone dreams up without > redesigning it. > > It is powered from Vccaux, not Vcco! Excellant and relevent info, I trust that this is all in the revised data sheets ? :) The 'better' LVDS devices offer rail-rail, but often specify a lower speed, or Vos, outside the std 'sweet-spot'. Most also have a small Hyst band - do the Xilinx ones ? > Since Vccaux is 2.5 volts in Spartan 3, that means that an input voltage > has to be in the range of 0 to 2.5 volts just to work at all (common > mode range). We don't specify it use at the rails, because we can't > cahracterize all the possible uses of the circuit. For low speeds, as I > said, it will function. Don't complain if it doesn't switch as fast as > it is specified for the LVDS specification (you are not using it there). > > Since every IO pin also has a giant nmos and pmos stack for the single > ended driver attached to it, you also have a diode from ground to the > pins, and a diode to Vcco for the bank. That means if the pin voltage > tries to go below ground (negative ~ 0.5V or greater) or above Vcco > (~Vcco+~0.5V) you will clamp the pin to that one diode above or below > ground. > > You should let the customer know who is likely to provide you with more > timely and useful information. They might change their mind.... :) -jgArticle: 101695
nospam wrote: > Some time ago I did some experimentation (for a very cost sensitive > application) with a Spartan 3 part using an LVDS differential input as a > voltage comparator for a crude delta sigma ADC. > > The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the > 3.3v supply and the differential input voltage was (obviously) limited to > whatever it took drive the LVDS input one way or the other. > > It worked fine. > > Now the customer says he wants to use Cyclone II. > > I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have > to provide a 2.5v supply just for this one input. > > So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator) > input on 3.3v biased at 1.65v. > > After an age I get the answer no, but I could use an LVPECL standard > <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is > outside the LVPECL standard common mode range and LVPECL is only available > on dedicated clock input pins anyway. > > So I ask the question again and after another age get told no, LVDS has to > run on 2.5v and no more than 650mV differential input with no further > explanation. When someone says that, it starts to sniff of a back-back clamp diode structure - some opamps do use this to protect sensistive 1st stage devices. Would be surprising on a FPGA tho. This is the sort of thing you could test on a bench very easily ? -jgArticle: 101696
Ron wrote: > I have already designed and tested my circuit (both in simulation and on > a *REAL* FPGA, but using a smaller bus width). There is absolutely NO > research whatsoever involved, it's purely a pragmatic matter of > implementation and being able to afford your overpriced software design > tools on my retirement savings. Hi Ron, I "play" most days too with large FPGAs as a consultant, small business owner, and hobbiest. There are much more affordable ways to tackle these larger problems than rushing out and paying retail that many of us use instead. Building your own FPGA boards is not nearly as difficult as it might seem, if you keep a KISS (Keep it Simple Stupid) design goal clearly in mind. I've helped other homebrew folks do the same, drop me a note if you need some guidance. Consider using NOS (New Old Stock) parts available from Gray Market sources, such as Ebay. Your 100,000 LUTs can be found in ten Xilinx XC2V1000-4FF896C FPGAs listed in item 7606455467 for roughly $730 US. I believe that seller has a few more as well, and they have been listed for some time, so if you made an offer, they might be available for quite a bit less if you are willing to take them all. Add in the $300 price of 2 4-layer PCBs from PCB Express, and you too can have your own NEW homebrew FPGA super computer running for about $1,000 US in a month or two of fun hardware/software projects. A little more risk (but manageable) is recycling FPGAs from scrapped boards available from a number of sources, including Ebay. Reballing FPGA can also be done at home, using little more than a toaster oven (with electronic controls, or a convection oven). Larger Altera and Xilinx FPGA's can frequently be had for under $100ea as scrap. See Ebay lot 7613930035. Using recycled parts, you can save another 80% or more off NOS parts, but they require an investment in reballing supplies (min order on preforms). A larger 300,000 LUT or more home FPGA super computer can easily be built under $1,000US using this strategy. I reball/recycle parts frequently to cut costs in prototyping (including reusing first run parts on a prototype design when I cut the second/third revison boards). This can substantially cut prototyping costs for contracts, as well as hobby projects. Have Fun! JohnArticle: 101697
Hi, Recently I received a RFID chip to open company's door when entering office building. It is very easy to carry and use like a key. I would like to know whether it contains a battary or not. If there is no battary in it, how can a circuit work running with Radio Frequency? WengArticle: 101698
Weng Tianxiang wrote: > Hi, > Recently I received a RFID chip to open company's door when entering > office building. > > It is very easy to carry and use like a key. > > I would like to know whether it contains a battary or not. > > If there is no battary in it, how can a circuit work running with Radio > Frequency? > > Weng > No battery. The circuit scavenges the energy in the RF signal, rectifies it and uses that to power the circuit. Sort of like a crystal radio set.Article: 101699
Robin Bruce wrote: > >>You'll probably have to resurrect an old system >>slower/older than a pentium 166 to get it to work. > > > Couldn't he use a dos emulator like DOSBox or something like that? > That's what I do when I want to play some archaic PC game from back in > the day... > > Robin > Depends on how it interacts with the parallel port. The issue with the faster computers with the old software is that the parallel port communication gets too fast for the dongle.
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