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included in CRC are 1) data to be written 32 bits 2) addr of target register 4 or 5 bits depending on family data stream sent to LOUT register is not included AnttiArticle: 101726
Aurelian Lazarut wrote: > Peter, > One more thing, can you please point me to the document and page # where > you find 0xAA995566 as sync word? > thanks, > Aurash Aurash, XAPP452 "Spartan-3 Advance Configuration Architecture", p. 11 XAPP151 "Virtex Series Configuration Architecture User Guide", p. 27 (I know this is not for the S3 but the interface is so similar and it documents many things XAPP452 doesn't) A hex inspection of any bit file will also bring up the same data. Similarly, is there any chance that you, or anyone else, can point me to a reference which confirms this byte ordering (i.e. MSB first)? I'm clearly missing something obvious. Thanks to all who have replied on this topic, PeterArticle: 101727
Rob Warnock wrote: > <tomstdenis@gmail.com> wrote: > +--------------- > | What this does open the door for though is for mixed architecture > | systems. E.g. synthesize a MIPS core in the FPGA and map the DDR > | controller on to it. > | > | Then you have x86 and MIPS in the same system. > +--------------- > > But *not* necessarily running ccNUMA with each other!! See my recent > post on "comp.lang.lisp" [yeah, they were talking about the prospects > for using the same DRC FPGA for an update on the Lisp Machine]: > > http://groups.google.com/group/comp.lang.lisp/msg/ac1488796602931d > > especially the bits about the difference between "non-coherent HT", > used for ordinary I/O (PIOs & DMA), and the "coherent HT" used for > the inter-Opteron ccNUMA cache-coherency. I *strongly* suspect the > DRC FPGA[1] only does non-coherent HT, which, while just fine for > a DMA-style crypto co-processor, wouldn't let your FPGA-based MIPS > CPU participate in the Opteron cache-coherency protocol. They would definitely be non coherent. For the device to work though it would need a memory controller that interprets HT. There is no way for the Opteron to talk to the other node (from a software point of view) other than by memory read/writes. Likely the device reserves a space for it's registers then maps the memory somewhere. The Opteron would have to be the boot processor and it would setup the DRCs node link table and other jazz. >From the opterons point of view all of the memory on the DRC side of the link would be uncacheable. That's about the only way to make it work. ... Still wants a x86-mips or even x86-ARM hybrid... muahahhahaaha TomArticle: 101728
Thanks, I;ve opened adept with the correct package/fpga. All the pins seem to be physically connected, is there an option somewhere for viewing the unbonded iob's? Thanks a lot, AlastairArticle: 101729
Hi Peter, dont push xilinx again on documentation too hard - it is as it is - the bytes appear in bytewide config stream in the order they are in the .BIT file, also the bits are sent out MSBit first, eg if you write the .BIT file as continous file onto MMC/SD card, and then read the card sector per sector clocking CCLK on each databit then FPGA does get configured. Similarly you can just copy .BIT file into SPI flash and read out the image (and copy to DIN/CCL) and it works and configures the FPGA. Well if you have multiply FPGAs in serial chain then you need to run promgen (to insert second bitstream as LOUT stream), promgen reverses bits (when XCF is target) then to get programming file for SPI flash (chained config) the output of promgen needs to have bitreversing applied. I was really surprised and frustrated when trying to load 2 FPGA's from SPI flash, no matter the settings the best result (without using LOUT stream) was that both FPGAs did get configured DONE=1 but on the second FPGA GHIGH was not activated (FPGA not released from config) the first FPGA started well. I still dont understand completly why it was like that, but using promgen (to 'insert' the slave stream inside the master bitstreams LOUT frame) fixed the issue. I had to write my own bitreverse to fix the output of promgen though. AnttiArticle: 101730
>Hello, > >I am verry new to this Field and i would be verry happy if anybody would sujjest > me a link or any document which gives me an idea on what an FPGA/CPLD is and > its arcitecture,how a vhdl code is actually implmented in these... > Regards, Guru Prasad So, you're new to the field and don't know what an FPGA/CPLD is, but you want a "detailed description" of the architecture? You're new to the field, but you want to know how the VHDL is implemented in the devices? This is like a man who says he doesn't know what a car is, but wants a "detailed description" of the engine management system and how it's algorithms are implemented in an embedded processor. My advice is to give up now. If your first action is to throw up your hands and ask for help, you've no chance. If you know how to send a message to this group, then you know how to use a search engine. A year ago, I was "verry new to this Field". I'm still new to it. Maybe in another five years I'll be able to claim an average competence. But neither of us will get there the way you're going.Article: 101731
Ron (News5@spamex.com) wrote: : Glory and riches are showered upon those who successfully factor one of : the RSA Challenge Numbers (see note [1]) ;-). I would like to be the : first to factor an RSA number using a standalone FPGA development : board(s) (ie; not connected to a conventional computer). <big snip> : If such a device did become available, my only hope for acquiring the : requisite hardware/software would be to work out a deal with the FPGA : vendor or someone to lend me the necessary development board and s/w : tools in exchange for the potential fame and glory, since I am but a : humble retired engineer/hobbyist. :-) Ron, Perhaps you could partner with a local university and form an undergraduate project based on this? I say this because universities have access to this rather nice board at an affordable price... http://www.xilinx.com/univ/xupv2p.html Unless you could shrink the design you'd need to join several boards... Cheers cdsArticle: 101732
>You can't program these directly with the WebPack software. I use a Xeltek >universal device programmer, and it is very good, and pretty cost effective. Ie you must have an configuration memory on the board? (be it sram or whatever.) If yes, then why is it so..?, fpga wants data at a very high datarate ..?Article: 101733
Ed McGettigan a =E9crit : > christophe ALEXANDRE wrote: > > hi Xilinx, > > > > do you thing i have a chance to buy an ML405 > > board before i retire ? > > > > i saw the first announcement for this board > > in XCELL first quarter 05. > > > > We are in May 06. > > > > Any problem with virtex4 FX ? > > > > The first volume production of the ML405 (XC4VFX20-FF672-10CES4) > will be available for sale in late June 06. That's less then > 2 months from now, so I hope that your nest egg is well > funded. :-) > > All of the initial volume of the XC4VFX20 devices had been > prioritized and allocated to customer sockets over the eval > boards. Since we are using long lead time manufacturing to > keep the costs and prices down it has been longer than > expected to get these boards available for sale. We expect to > do much better with the next generation. > > Ed McGettigan > -- > Xilinx Inc. Is your calendar reliable ? I mean, i don't care about marketing and i only want to know when i can get it for sure from AVNET in Europe. Would it be possible to get a user's manual + schematics in advance to prepare some future designs ?Article: 101734
I am trying to find some opb_ipif timing diagrams. The Xilinx document "DS404" has figure numbers and titles on the pages, but there are no figures for the register timing! I have tried downloading two different versions, on different computers, and still see nothing. Other diagrams (FIFO timig) are fine. Both computers use Adobe Acrobat 7.0. I hve looked at 3.01a and 3.01b versions of the doc. Any info? Can these same figures be found in another document?Article: 101735
Not all device/package combinations have unbonded IOBs. Usually a big device in a small package have unbonded IOBs. As an example, if you open 4vlx25sf363 in ADEPT, it will displays all unbonded IOBs (UNB_XmYn pins) in this package. HTH, Jim http://home.comcast.net/~jimwu88/toolsArticle: 101736
On Fri, 05 May 2006 07:59:55 +0200, Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de> wrote: >Weng Tianxiang wrote: > >> It is really a marvelous invention!!! >> >> Who is the inventor? >Ok - this was the direction from the interrogator to the tag. Backward >communication is done by drawing more or less energy from the field >(switching on/off a load). Who could be named here? - I don't know. Is that generally true? I had imagined that communication from the tag would be easier by controlling the level of one or more harmonics re-radiated from the tag. - BrianArticle: 101737
The FPGA stores its configuration in SRAM memory cells. These are part of the FPGA, so you don't need external SRAM. But, since it's RAM, the FPGA doesn't keep the configuration memory contents if you disconnect the power supply. That's what the mentioned (Platform)Flash chips are for - to provide the FPGA with an initial bitstream on powerup. You can just as well power up your FPGA and load the initial configuration through JTAG. hth -EnnoArticle: 101738
I wonder how long it'll be before folks get flamed on usenet for not wikipeding before posting? :-) http://en.wikipedia.org/wiki/RFIDArticle: 101739
Ok thanks, so the 4vlx25ff668 doesn't have any?Article: 101740
Subroto - For my archiving purposes, I'd like to know the smallest set of Quartus files I need to save to re-create the design. My analogy here is - "if your house was on fire, what what you carry out with you". I think I only need to keep my HDL code, the .qpf, and .qsf files. All the other files can be re-created using the Altera tools, correct? Luckily, if "my house is on fire", all of these files will fit in my pocket. John ProvidenzaArticle: 101741
Look at the data sheet: The family overview in table 1 tells you that the chip has 448 IO. Table 2 then tells you that the SF363 package has 240 available IO, and the FF668 package has all 448 IO brought out. Peter Alfke, XilinxArticle: 101742
Bob, There are some combinations that may be possible to set the config bits to support, but we intentionally choose not to do so (no standard). So, just because something is possible, does not mean we need to support it. Safest thing to do here is to power Vcco from 2.5V, Vccaux is 2.5V, and you instantiate a LVDS25 input. If you instantiate a LVDS25 input and the Vcco is 3.3V, all you get is a design rule error (3.3V and 2.5V IOs in same bank). If you can ignore the error, and get a bitstream anyway, there you go (success). Austin > [snip] > > Austin, > > Are you saying that, since in V2-V4 the LVDS input buffer is driven from > VCCAUX, even if a bank's VCCO is not 2.5V you may instantiate an LVDS25 > input? What about an LVDS output in a non-2.5V VCCO bank? > > Thanks much, > Bob > >Article: 101743
Peter, I apolgise the corect sync word is 0xAA 0x99 0x55 0x66 the docs are correct. you need to send the bytes in this order (from left to right) at your select map interface. MSB to MSB (NSB bit from the bytes from file to D7 at fpga) Aurash Peter Mendham wrote: > Aurelian Lazarut wrote: > >> Peter, >> One more thing, can you please point me to the document and page # >> where you find 0xAA995566 as sync word? >> thanks, >> Aurash > > > Aurash, > > XAPP452 "Spartan-3 Advance Configuration Architecture", p. 11 > XAPP151 "Virtex Series Configuration Architecture User Guide", p. 27 > (I know this is not for the S3 but the interface is so similar and it > documents many things XAPP452 doesn't) > > A hex inspection of any bit file will also bring up the same data. > > Similarly, is there any chance that you, or anyone else, can point me to > a reference which confirms this byte ordering (i.e. MSB first)? I'm > clearly missing something obvious. > > Thanks to all who have replied on this topic, > > PeterArticle: 101744
Antti wrote: > sent as aa 55 66 99 > > Antti > Antti I think it's 0xaa 0x99 0x66 0x66 (typo?) AurashArticle: 101745
Aurelian Lazarut wrote: > Antti wrote: > >> sent as aa 55 66 99 >> >> Antti >> > Antti > I think it's 0xaa 0x99 0x66 0x66 (typo?) > Aurash I meant 0xaa 0x99 0x55 0x66 (yes typo, friday evening) AurashArticle: 101746
"johnp" <johnp3+nospam@probo.com> writes: > I think I only need to keep my HDL code, the .qpf, and .qsf files. All > the other files can be re-created using the Altera tools, correct? I keep my HDL files and a small tcl script to compile the design and generate the programming files (optionally upload the programming files to the DUT). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 101747
Austin Lesea wrote: > [...] > For a kinder and gentler college experience, there is this school right > across the bay from Berkeley....(also a great school). I am sure there > is the equivalent in the LA basin as well... > [...] yup. it's called USC ;o) lArticle: 101748
nospam wrote:
> So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator)
> input on 3.3v biased at 1.65v.
>
> After an age I get the answer no
Don't worry, the answer "no" is the safest possible answer, so it is
often used as the default reply. :-) Once I asked Cypress whether
I can do something fancy with their GPIF automaton and got the
answer "no". Then I sent the question again with more detailed info
and again received "no". Then I have created a prototype and
the "answer" from it was "oh, yes!". :-)
Rule of thumb: If FAE says "yes", then it "yes". If FAE says "no", then he
says.
> So I ask the question again and after another age get told no
Don't worry again, I still don't know whether I can temporarily deselect
a Spartan 3 device during reprogramming and grant the bus to another
DMA device... I bet the answer, if any, will be "no". :-)
Best regards
Piotr Wyderski
Article: 101749
Jan Decaluwe wrote:
> Does Quartus issue warnings also?
> No doubt the warnings are related to the use of blocking
> assignments in a clocked always block. You know :-)
Yes, and the warning isn't even apropos in this case since
you've gone belt-and-suspenders with a single named block
and local declarations for every reg appearing left of an '='.
I will check if I there is some way to stifle the warning.
> At least XST doesn't declare this an error.
I knew XST had to be better at something :)
> My worst nightmare
> would be that half-baked synthesis tools or Verilog gurus
> would prevent me from writing code like this. It's a realistic
> possibility that explains my occasional angry outbursts.
The tools have always allowed it,
and I suspect that a silent majority
of serious designers have used the
style without making a big deal of it.
There will always be quiet producers
and noisy lint-pickers.
> What I think happens is that XST creates a FF for any reg
> in the code. When it detects that the Q output is not used,
> it issues a warning. Fine with me, as long as it uses
> the D input wire properly :-)
Synthesis really has to do this anyway
because wasting flops is a mortal sin.
> An interesting side effect is that no warnings are issued
> in the more "advanced" case when a reg is potentially
> used immediately but also stored for later usage,
> like the 'counting' flag in this example:
>
> http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch
Yes, synthesis is very clever.
Every variable-reg update gets
its own little "instance" of gates.
Keep up the good work and
don't let the b^st^rds get you down.
If I have to learn a new trick,
I think I would prefer python to systemverilog.
-- Mike Treseler
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