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"Zara" <yozara@terra.es> wrote in message news:aid9321jos46c9kqo56ispelb6cdliho9o@4ax.com... > On Wed, 5 Apr 2006 05:25:59 -0700, ahakan <> wrote: > >>Thanks for your response, but I am using Parallel Cable IV, so I guess the >>problem is not due to the parallel cable (I tried the Platform Cable USB >>as well). > > > I have the same problem from time to time with PCIV (not tried with > other cables) and XC3S400. > > Sometimes it is just a momentary problem, you muts just try again and > it programs OK. Sometimes it is plain stupidity of (I suppose) the > FPGA, switch power off and on again, it usually works. > > Best regards, > > Zara I have always had this problem using the parallel cable IV as above. Even with my Virtex 4 board the problem was even more apparent likely because the bit files are so much larger. My strategy was to switch the board off and on and restart iMPACT and possibly even regenerate the bit file. I think that the parallel stream occasionally creates errors and this error happens. I always program the SPROM and do my unit testing from there rather than program every time with the JTAG port. Hope that helps, AndrewArticle: 101751
"boru" <aborundiya@gmail.com> wrote in message news:1146491542.962164.163010@j33g2000cwa.googlegroups.com... > hi everyone, > i am curently debugging a board developed havin vitex chip... when i > try to program this board following error occurs. > > ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position > '1' > > i tried to go through the xilinx website and found some instruction but > that did not help .. > if any one encountered the same problem .... your help will be > appreciated...... > > One of the reason I am thinking is the the speed with which the virtex > chip and Jtag are operating are not matching, correct me if I am wrong. > If yes is there anyway to change frequency of JTAG. > That error typically appears when there is no communication path to the FPGA or SPROM. Many things can cause this error, from lack of power to poor connections. Check that your test board has the correct jumper setting for boundary-scan. What board are you using? -AndrewArticle: 101752
Austin Lesea wrote: > That prize was 1.73 billion dollars (US)last year (Xilinx sales). I complain about your software design tools being too overpriced for a mere retired engineer to afford, and you come back bragging about Xilinx's profits last year? Personally I think it's unethical for you Xilinx fuckwits to be using a public forum to promote your products. RonArticle: 101753
Ron, here is some friendly advice, from one senior citizen to another: If you expect some asistance of any kind, calling us "you Xilinx fuckwits" is not a very helpful comment. It's not appropriate under any circumstances. It just reflects badly on you, I am sorry to say... Peter Alfke, Xilinx ApplicationsArticle: 101754
Thanks for all your help.Article: 101755
Peter Alfke wrote: > If you expect some asistance of any kind, Not any more I don't. I realized right away that you money grubbing SOB's from Xilinx couldn't care less about promoting your products to anyone who doesn't come to you with bulging pockets full of money. The irony is that the Lattice support people I have corresponded with have been very helpful and friendly. RonArticle: 101756
Eric Smith wrote: > "Sid" <sid.gaddam@gmail.com> writes: > > Does anybody know of an IP vendor that sells the 87C51 & 87C52 IP cores > > for FPGA's? > > > > I have gone through the following IP vendor sites but couldn't find > > what I was looking for. I did find various forms of 8051 and 8052, > > though! > > The 87C51 and 87C52 are just the CMOS versions of the 8051 and 8052 > with onboard EPROM program memory. You should be able to use an 8051 > or 8052 CPU core, and use a blockram for the program memory. I was interested in the EPROM program memory feature of the 87C52's. If I can use the BRAM's in its place, then I think I can go ahead with one of the already available cores. Thanks for the help guys.Article: 101757
fpga_toys@yahoo.com wrote: > Consider using NOS (New Old Stock) parts available from Gray Market > sources, such as Ebay. Thanks for the tip John. It's the best (and *only*, Ha!) advice I've received here. It would never have occurred to me to look for FPGA parts on ebay, but they have quite a huge selection of things to choose from. RonArticle: 101758
Antti wrote: > Hi Peter, > > dont push xilinx again on documentation too hard - it is as it is - the > bytes appear in bytewide config stream in the order they are in the > .BIT file, also the bits are sent out MSBit first, eg if you write the > .BIT file as continous file onto MMC/SD card, and then read the card > sector per sector clocking CCLK on each databit then FPGA does get > configured. Similarly you can just copy .BIT file into SPI flash and > read out the image (and copy to DIN/CCL) and it works and configures > the FPGA. > > Well if you have multiply FPGAs in serial chain then you need to run > promgen (to insert second bitstream as LOUT stream), promgen reverses > bits (when XCF is target) then to get programming file for SPI flash > (chained config) the output of promgen needs to have bitreversing > applied. > > I was really surprised and frustrated when trying to load 2 FPGA's from > SPI flash, no matter the settings the best result (without using LOUT > stream) was that both FPGAs did get configured DONE=1 but on the second > FPGA GHIGH was not activated (FPGA not released from config) the first > FPGA started well. I still dont understand completly why it was like > that, but using promgen (to 'insert' the slave stream inside the master > bitstreams LOUT frame) fixed the issue. I had to write my own > bitreverse to fix the output of promgen though. So, what happens with 3 FPGAs from a SPI stream ? -jgArticle: 101759
Ron, I thank you for your gift of such supreme and sublime eloquence and expression. AustinArticle: 101760
nospam wrote: > > Some time ago I did some experimentation (for a very cost sensitive > application) with a Spartan 3 part using an LVDS differential input as a > voltage comparator for a crude delta sigma ADC. > > The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the > 3.3v supply and the differential input voltage was (obviously) limited to > whatever it took drive the LVDS input one way or the other. > > It worked fine. > > Now the customer says he wants to use Cyclone II. ... > Can anyone confirm this and has anyone experience of using LVDS inputs as > voltage comparators on Cyclone II (or Spartan 3/3e for that matter). I have a bunch of Cyclone I and II designs using LVDS based at 1.65V that are working just fine at 270MHz input rate. They are fed by either Gennum 9064 or CYV270M0101EQ cable equalizers (I prefer the Cypress, but it has only just become available in volume). I remember from my Altera days that there was some reference-ish design that used the same trick to make an LVDS pair act as a Digta-Selma (or the other way round) ADC. It had horrible DC properties, but at frequencies over 100Hz it was fairly accurate (16 bit up to 250KHz or so). Best regards, BenArticle: 101761
Austin Lesea wrote: > I thank you for your gift of such supreme and sublime eloquence and > expression. I try to adapt my phraseology to match the IQ of my target audience. In the case of Xilinx application engineers I'm forced to constrain my vocabulary to simple words understandable by simple minds.Article: 101762
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:445baf1c$1@clear.net.nz... > Antti wrote: >> Hi Peter, >> >> dont push xilinx again on documentation too hard - it is as it is - the >> bytes appear in bytewide config stream in the order they are in the >> .BIT file, also the bits are sent out MSBit first, eg if you write the >> .BIT file as continous file onto MMC/SD card, and then read the card >> sector per sector clocking CCLK on each databit then FPGA does get >> configured. Similarly you can just copy .BIT file into SPI flash and >> read out the image (and copy to DIN/CCL) and it works and configures >> the FPGA. >> >> Well if you have multiply FPGAs in serial chain then you need to run >> promgen (to insert second bitstream as LOUT stream), promgen reverses >> bits (when XCF is target) then to get programming file for SPI flash >> (chained config) the output of promgen needs to have bitreversing >> applied. >> >> I was really surprised and frustrated when trying to load 2 FPGA's from >> SPI flash, no matter the settings the best result (without using LOUT >> stream) was that both FPGAs did get configured DONE=1 but on the second >> FPGA GHIGH was not activated (FPGA not released from config) the first >> FPGA started well. I still dont understand completly why it was like >> that, but using promgen (to 'insert' the slave stream inside the master >> bitstreams LOUT frame) fixed the issue. I had to write my own >> bitreverse to fix the output of promgen though. > > So, what happens with 3 FPGAs from a SPI stream ? > > -jg > not quite sure, I guess promgen inserts 3rd one into LOUT of the second one, and that combined bistream into LOUT of the first one. But I have not dealt with such configs. BTW its the same if SPI flash or normal fpga serial flash AnttiArticle: 101763
"Ron" <News5@spamex.com> wrote in message news:wSM6g.97$R03.76@fe03.lga... > Austin Lesea wrote: >> That prize was 1.73 billion dollars (US)last year (Xilinx sales). > > I complain about your software design tools being too overpriced for a > mere retired engineer to afford, and you come back bragging about Xilinx's > profits last year? > > Personally I think it's unethical for you Xilinx [expletive] to be using a > public forum to promote your products. > > Ron The involvement is to HELP folks on this board, not (purposely) to promote the products. Bite the hand.Article: 101764
"Ron" <News5@spamex.com> wrote in message news:LkN6g.24$771.2@fe06.lga... > Peter Alfke wrote: >> If you expect some asistance of any kind, > > Not any more I don't. I realized right away that you money grubbing SOB's > from Xilinx couldn't care less about promoting your products to anyone who > doesn't come to you with bulging pockets full of money. > > The irony is that the Lattice support people I have corresponded with have > been very helpful and friendly. > > Ron Once you realized a business wasn't willing to provide you with something worth the price of a car so you could win $30,000.... Folks here were helpful and friendly until you decided to stink up the place.Article: 101765
>things now bringing high end commodity CPUs (as opposed to specialist DSP >hardware) and FPGAs close together - offerings from Cray, SGI, this new >opteron socketed thingie etc. Most of the fuss is around their use in >reconfigurable computing so the offerings tend to be lacking for raw >serial IO... >: Whats you acquisition area? >Starlight - astronomical adaptive optics. Potentially you can be talking >about multiple CCDs of many thosands of pixels framing at over 1KHz... CCD -> Hyperthread -> FPGA -> Hyperthread .. other cpu(s). (just a quick thought)Article: 101766
Ron wrote: [crude insult deleted] Peter Alfke wrote: > If you expect some asistance of any kind, Ron wrote: > Not any more I don't. I realized right away that you money grubbing > SOB's from Xilinx couldn't care less about promoting your products to > anyone who doesn't come to you with bulging pockets full of money. Next time you buy a car, try to convince GM, Ford, Toyota, or Honda that they should give it to you free or at a substantial discount because you're trying to win a prize, and see how far that gets you. For that matter, see whether any of the car makers offer an only slightly limited version of one of their cars as a free download. > The irony is that the Lattice support people I have corresponded with > have been very helpful and friendly. Sounds like you should use Lattice parts instead of complaining about Xilinx. My experience has been that Xilinx support people have been helpful and friendly. That doesn't mean that they're always able to give me everything I want for free, though. And I don't curse them (publicly or privately) when they can't. EricArticle: 101767
"Sid" <sid.gaddam@gmail.com> writes: > I was interested in the EPROM program memory feature of the 87C52's. If > I can use the BRAM's in its place, then I think I can go ahead with one > of the already available cores. Thanks for the help guys. Difficult to use EPROM program memory in an FPGA that doesn't contain any EPROM. If there's some reason that you really need it to be an EPROM-like technology, I think there are flash-based FPGAs from Lattice, and flash memory is functionally fairly similar to EPROM (aside from not using UV to erase). But if all you need is a basically non-volatile program store that is only infrequently changed, BRAMs work fine as ROMs. They get loaded from the config memory, so when you do want to change the firmware you just rewrite the config memory. Best regards, EricArticle: 101768
In article <wSM6g.97$R03.76@fe03.lga>, Ron wrote: [stuff] > Is this close to what you're looking at doing? http://www.hyperelliptic.org/tanja/SHARCS/talks06/bulens.pdf -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 101769
christophe ALEXANDRE wrote: > Ed McGettigan a écrit : > >> christophe ALEXANDRE wrote: >>> hi Xilinx, >>> >>> do you thing i have a chance to buy an ML405 >>> board before i retire ? >>> >>> i saw the first announcement for this board >>> in XCELL first quarter 05. >>> >>> We are in May 06. >>> >>> Any problem with virtex4 FX ? >>> >> The first volume production of the ML405 (XC4VFX20-FF672-10CES4) >> will be available for sale in late June 06. That's less then >> 2 months from now, so I hope that your nest egg is well >> funded. :-) >> >> All of the initial volume of the XC4VFX20 devices had been >> prioritized and allocated to customer sockets over the eval >> boards. Since we are using long lead time manufacturing to >> keep the costs and prices down it has been longer than >> expected to get these boards available for sale. We expect to >> do much better with the next generation. >> >> Ed McGettigan >> -- >> Xilinx Inc. > > Is your calendar reliable ? I mean, i don't care about marketing > and i only want to know when i can get it for sure from AVNET in > Europe. > > Would it be possible to get a user's manual + schematics in advance to > prepare some future designs ? > This board was designed by my group and the production manufacturing is on target, so there so be no problems with Avnet selling you one in July. We are not planning on releasing the user documentation ahead of the product. Ed McGettigan -- Xilinx Inc.Article: 101770
Does anyone use the profiling tools with the Xilinx ppc405? I am trying to profile code on the ppc405 in a Xilinx XC2VP4. It works for a simple test, but when I try the real code, it fails. The call stack seems to be getting corrupted. When I look at the failure, the link register points to the instruction after mcount is called (the profile code at the beginning of the function) so at the end of the function it jumps back to the beginning of the fuction, ad infinitem. I am using EDK7.1sp2. profile is using PIT for timer. If someone else is getting this to work, I can keep trying. Otherwise, I may give up. Alan NishiokaArticle: 101771
John, We have seen counterfeit devices, and non-functional devices here as RMA's from customers who purchased products from non-approved sources. Since we know by the markings who we shipped them to, the sellers will remove markings, and remark (so they can not be traced). As soon as the number is bogus we know the buyer obtained the parts through a non-approved source, and that ends any support we can offer. We have seen parts that are not even our FPGAs (just random silicon) remarked and sold. They are likely to burn up your board when you try to power them on. Cavet Emptor: if you buy through the gray market, do not complain when you get ripped off. Sometimes folks are lucky and obtain an overstock device that someone could not use. But, since the packaging has absorbed moisture, one has to bake them before use, or the package will pop-corn when assembled (common to all packages nowadays). Austin fpga_toys@yahoo.com wrote: > Ron wrote: > >>I have already designed and tested my circuit (both in simulation and on >>a *REAL* FPGA, but using a smaller bus width). There is absolutely NO >>research whatsoever involved, it's purely a pragmatic matter of >>implementation and being able to afford your overpriced software design >>tools on my retirement savings. > > > Hi Ron, > > I "play" most days too with large FPGAs as a consultant, small business > owner, and hobbiest. There are much more affordable ways to tackle > these larger problems than rushing out and paying retail that many of > us use instead. Building your own FPGA boards is not nearly as > difficult as it might seem, if you keep a KISS (Keep it Simple Stupid) > design goal clearly in mind. I've helped other homebrew folks do the > same, drop me a note if you need some guidance. > > Consider using NOS (New Old Stock) parts available from Gray Market > sources, such as Ebay. Your 100,000 LUTs can be found in ten Xilinx > XC2V1000-4FF896C FPGAs listed in item 7606455467 for roughly $730 US. I > believe that seller has a few more as well, and they have been listed > for some time, so if you made an offer, they might be available for > quite a bit less if you are willing to take them all. Add in the $300 > price of 2 4-layer PCBs from PCB Express, > and you too can have your own NEW homebrew FPGA super computer running > for about $1,000 US in a month or two of fun hardware/software > projects. > > A little more risk (but manageable) is recycling FPGAs from scrapped > boards available from a number of sources, including Ebay. Reballing > FPGA can also be done at home, using little more than a toaster oven > (with electronic controls, or a convection oven). Larger Altera and > Xilinx FPGA's can frequently be had for under $100ea as scrap. See Ebay > lot 7613930035. Using recycled parts, you can save another 80% or more > off NOS parts, but they require an investment in reballing supplies > (min order on preforms). A larger 300,000 LUT or more home FPGA super > computer can easily be built under $1,000US using this strategy. > > I reball/recycle parts frequently to cut costs in prototyping > (including reusing first run parts on a prototype design when I cut the > second/third revison boards). This can substantially cut prototyping > costs for contracts, as well as hobby projects. > > Have Fun! > John >Article: 101772
John, You forgot one other possiblity: Get a job as a consultant in a large company, contact the local FPGA rep of your choice, and tell them you need samples. <fpga_toys@yahoo.com> wrote in message news:1146785744.192075.124210@u72g2000cwu.googlegroups.com... > > Ron wrote: >> I have already designed and tested my circuit (both in simulation and on >> a *REAL* FPGA, but using a smaller bus width). There is absolutely NO >> research whatsoever involved, it's purely a pragmatic matter of >> implementation and being able to afford your overpriced software design >> tools on my retirement savings. > > Hi Ron, > > I "play" most days too with large FPGAs as a consultant, small business > owner, and hobbiest. There are much more affordable ways to tackle > these larger problems than rushing out and paying retail that many of > us use instead. Building your own FPGA boards is not nearly as > difficult as it might seem, if you keep a KISS (Keep it Simple Stupid) > design goal clearly in mind. I've helped other homebrew folks do the > same, drop me a note if you need some guidance. > > Consider using NOS (New Old Stock) parts available from Gray Market > sources, such as Ebay. Your 100,000 LUTs can be found in ten Xilinx > XC2V1000-4FF896C FPGAs listed in item 7606455467 for roughly $730 US. I > believe that seller has a few more as well, and they have been listed > for some time, so if you made an offer, they might be available for > quite a bit less if you are willing to take them all. Add in the $300 > price of 2 4-layer PCBs from PCB Express, > and you too can have your own NEW homebrew FPGA super computer running > for about $1,000 US in a month or two of fun hardware/software > projects. > > A little more risk (but manageable) is recycling FPGAs from scrapped > boards available from a number of sources, including Ebay. Reballing > FPGA can also be done at home, using little more than a toaster oven > (with electronic controls, or a convection oven). Larger Altera and > Xilinx FPGA's can frequently be had for under $100ea as scrap. See Ebay > lot 7613930035. Using recycled parts, you can save another 80% or more > off NOS parts, but they require an investment in reballing supplies > (min order on preforms). A larger 300,000 LUT or more home FPGA super > computer can easily be built under $1,000US using this strategy. > > I reball/recycle parts frequently to cut costs in prototyping > (including reusing first run parts on a prototype design when I cut the > second/third revison boards). This can substantially cut prototyping > costs for contracts, as well as hobby projects. > > Have Fun! > John >Article: 101773
Tobias Weingartner wrote: > Is this close to what you're looking at doing? > > http://www.hyperelliptic.org/tanja/SHARCS/talks06/bulens.pdf Thanks for the article Tobias. Parts of it look interesting, but no, what they are doing bears little resemblance to what I have done. As I said earlier, my ECM algorithm is coded entirely in Verilog HDL with no connection to an external PC or anything else (nor any embedded microprocessor core). Once it's programmed I turn it on (the number to be factored is hard coded into the FPGA) and wait for it to factor the requisite composite number and invoke a module I'll have to write myself because Xilinx only provides VHDL examples of it's interface) that displays the factor. Also, another thing that makes my Place and Route problems much greater than the UCL group's is that I am dealing with a bus width of 704 bits rather than the 79 or even 163 bit numbers discussed in the viewgraphs you mentioned. I am very impressed with their timing numbers however. As I mentioned earlier, the basic design for ECM and a couple of other factoring methods I haven't alluded to but which I've also coded in Verilog, have been completed for several weeks. What I have is purely a packaging problem. I have a little more squeezing I can do on my designs, and I could afford the cost of the development boards if necessary, but I simply cannot justify spending the cost of a decent motorcycle on proprietary design software tools sold at usurious prices by a company whose employees are both condescending and offensive at the same time. Regards, RonArticle: 101774
Austin Lesea wrote: > Cavet Emptor: if you buy through the gray market, do not complain when > you get ripped off. Certainly. On the other hand I generally turn fraud over to the FBI, as it makes little sense to complain to anybody else, like Xilinx. I've purchased gray market parts in volume without a problem for 35 years, including high end Xilinx FPGAs. The last 6 years has been a gold mine in bankrupt NOS sales from the DOT COM bust, plus recycling parts from new never used boards from the same sources. In the VERY few cases I've had problems, it's easily absorbed into the steep discount I get on most gray market parts. Consider 18 Qty 2K reels of AVX TAJB226K004R for a lot price of $275 including shipping that I picked up last month, which would have cost about $3K through distribution at that Qty, and twice that a reel at a time as I would normally purchase them -- 5-10% on the dollar is worth a little risk. Most of the several hundred reels of parts I have in inventory was purchased for a few pennies on the dollar -- as Gray Market NOS parts at auction over the last 6 years. Ditto for another several hundred trays of specialty ASICs, FPGAs, memory, PLDs and processors. Ditto for several hundred NOS XC18V04's at a buck a piece, a couple hundred NOS XCV1000E's at $15/ea plus another hundred pulls from the same source at $3/ea. Some high value project boards are not worth the Gray Market risks, but that is our clients choice. While in many cases we can not ship pulls as new product for resale, we can use them to build boards for captive in-house use, spares inventory, prototypes and save the client quite a few dollars. Consider a few hundred pulls of XC2VP 30/40/50/70's at $35-55/ea, and another few hundred XC2V6000 for a little less is a significant savings for building prototypes, research designs, and spares inventory for devices prices originally in the several hundred to several thousand dollar range. A little risk isn't about getting lucky, it's about buying smart. It allows us to low ball fixed price contracts and pass the savings to our clients by sharing the windfall. It also allows personal research projects that only large corporations could fund using new distribution parts. And another several thousand pulls of XC4062XLA, XC4085XL, XCV300/600/800/1000/1600/2000/2600 and XC2V parts as well, mostly down in the $1-10/ea for parts smaller than XCV1000's. I seldom pay much more for larger parts, a range that I've used for various projects over the last 6 years. TechStar balls in bulk make reballing reasonably cheap :). SolderQuik preforms for everything else. Bake, flip thru the solder fountain to strip ball slag off, clean/flux and reball in a fixture under A.P.E SMD-1000's. BG432/560 parts are certainly easier than later parts. > Sometimes folks are lucky and obtain an overstock device that someone > could not use. But, since the packaging has absorbed moisture, one has > to bake them before use, or the package will pop-corn when assembled > (common to all packages nowadays). Yep ... bake almost everything. Really isn't a problem to kit next days build and put the whole thing in the oven for a day anyway. For low volume client builds, there are plenty of New Old Stock parts at reasonable prices. And a Lot that people are holding at full retail, waiting for someone that needs to short run an old design to avoid regulatory certification if the design were changed for new parts. For short runs (up to a few hundred boards) you don't need to be lucky, just buy smart. Have Fun, John
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Compare FPGA features and resources
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