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On Mon, 27 Mar 2006 12:56:10 +1000, Allan Herriman <allanherriman@hotmail.com> wrote: >On Mon, 27 Mar 2006 01:12:41 GMT, mk <kal*@dspia.*comdelete> wrote: > >>On Sun, 26 Mar 2006 22:47:13 +1000, Allan Herriman >><allanherriman@hotmail.com> wrote: >> >>>>> dff #4 park_reg(.din (next_pv), >>>>> .clk (clk), >>>>> .q (park_vec), >>>>> .se (se), .si(), .so()); >>... >>>dff isn't a gate primitive, so it must be a UDP. However, it seems >>>that the standard only allows ordered parameter assignments and not >>>named parameter assigments for UDPs. >>> >>> >>>Therefore the code isn't legal according to the standard. >>> >>>This seems to be a mistake in the standard. Does anyone know why it >>>doesn't allow named parameter assignments for UDPs? >> >>I must be missing something. Why is a named parameter assignment >>needed ? Isn't this an ordered parameter assignment ? > >In the above code, > >( >.din(next_pv), >.clk(clk), >.q(park_vec), >.se(se), >.si(), >.so() >) > >is a named parameter assignment. Oh, you mean "named port connection" in which case you're correct. The port assignment of UDPs can only be done by order. "named parameter assignment" is something entirely different.Article: 99576
mikeotp@gmail.com writes: > is it possible from the driver of a chip and pin assignment > of a chip to reverse a chip,and to produce the same chip? By "the same chip" I assume you really mean "an equivalent chip", in which case the answer is yes. However, it may take arbitrarily long to to prove (or disprove) that your equivalent chip has identical functionality to the original.Article: 99577
For the past week or so the Xilinx online store says that target availability (from the store) is April, but that it is available "now" from Avnet. But the link to the Avnet site brings up a page that says that it's not available for ordering. Maybe someday... "If it sounds too good to be true, it probably is."Article: 99578
On Mon, 27 Mar 2006 03:40:36 GMT, mk <kal*@dspia.*comdelete> wrote: >On Mon, 27 Mar 2006 12:56:10 +1000, Allan Herriman ><allanherriman@hotmail.com> wrote: > >>On Mon, 27 Mar 2006 01:12:41 GMT, mk <kal*@dspia.*comdelete> wrote: >> >>>On Sun, 26 Mar 2006 22:47:13 +1000, Allan Herriman >>><allanherriman@hotmail.com> wrote: >>> >>>>>> dff #4 park_reg(.din (next_pv), >>>>>> .clk (clk), >>>>>> .q (park_vec), >>>>>> .se (se), .si(), .so()); >>>... >>>>dff isn't a gate primitive, so it must be a UDP. However, it seems >>>>that the standard only allows ordered parameter assignments and not >>>>named parameter assigments for UDPs. >>>> >>>> >>>>Therefore the code isn't legal according to the standard. >>>> >>>>This seems to be a mistake in the standard. Does anyone know why it >>>>doesn't allow named parameter assignments for UDPs? >>> >>>I must be missing something. Why is a named parameter assignment >>>needed ? Isn't this an ordered parameter assignment ? >> >>In the above code, >> >>( >>.din(next_pv), >>.clk(clk), >>.q(park_vec), >>.se(se), >>.si(), >>.so() >>) >> >>is a named parameter assignment. > >Oh, you mean "named port connection" in which case you're correct. The >port assignment of UDPs can only be done by order. "named parameter >assignment" is something entirely different. Uh, yes, you're right. Sorry, I copied the wrong bit out of the standard and confused myself. Still, I don't understand why named port connection isn't allowed for a UDP. Regards, AllanArticle: 99579
Hi, I have been trying to port Linux on the ML403 board using the 2.4 devel tree downloaded from montavista site using rsync.The compilation goes fine with the modifications of some source files and makefiles after copying the BSP generated from EDK 7.1 (I used some BYU website advice about porting Linux on XUV2P board). I manage to download the Linux kernel via xmd, the kernel boots but it has a problem and an exception 0400 seems to occur. Did anyone try the same method and managed it correctly ? Does anyone have an idea as to why I have this exception ? How could I investigate this issue not being an expert in Linux but just trying to understanding what is going on ? Best regards, JFArticle: 99580
Brian, if you start with sn 8 MHz signal with a duty cycle significntly different from 50%, there is no way (in hell) to generate a low-jitter 16 MHz output, without using a DLL or PLL or other complicated timing circuit. That's really basic. Peter AlfkeArticle: 99581
Xilinx can safely say so, Avnet is good by taking orders now and shipping 6 months later. Avnet was the first to announce V4 evalboard availability so of course I placed order immediatly. When those 6 months elapsed, well at the time I finally got Avnet board I could have received some better board. But I had already order pending at Avnet, because of their advance announcement. Nice marketing politics. Works one time. You get pissed once, and you will avoid Avnet later if you have options. Sure after Avnet swallowed Memec there isnt many options to get Xilinx silicon and/or boards so you are stuck with Avnet one way or another (as long as you stick with Xilinx). Hm I kinda understand why it took so long for Avnet to get the approval in court to buy memec (because of the anti-monopoly laws). Ok, ok maybe its all not so bad, maybe I am just releasing the monday morning steam, maybe all other have very good experiences with Avnet and have received the orders on time (not sooner not later), etc, etc.. if that is the case then sorry (to Avnet).Article: 99582
yes, thats correct, given infinite time all is doable, but after using that indefinite time for reverse engineering it may also require another indefinite time to prove that the result is functioning correct. that means there is no answer - things that may seem like they can not be duplicated could be easy to clone, something that looks like an inverter may be impossible to clone, as it may use pulse width and delay jitter modulation technics to implement a shadow protocol for an high secure co processor that is mimicing an inverter to all measurements made from outside world.Article: 99583
MikeShepherd564@btinternet.com writes: > Does anyone know why they do this? I wanted to download one of their > PDF documents, but the site don't respond (even to pings). I have no problems downloading PDF documents (just downloaded a 10MB PDF file). Many sites will block ICMP for security reasons. This will prevent ping/traceroute from working properly. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 99584
you right, from germany web browser says that it cant find DNS lookup and tracert dies on timeout somewhere in Santa Clara maybe Altera has announced Xilinx-killer and servers are overloaded on US westcoast? Stratix-IIGX should be sampling this week, but I dont think that is that big news that makes servers to shut down. If you havent decided on the silicon yet, then well Xilinx has finally solved their issues with V4FX silicon and LatticeSC also provides SERDES up to 3.4G, and excpet S2GX I dont see anything on Altera that could be of interest. Cyclone/II is beaten with Lattice ECP2 MaxII is beaten by Lattice machXO small PLD from Altera arent on the menu for longer time, so what remains? S2GX could be still of some interest, maybe, but here also if you arent going to use 6G SERDES then up to 3.4G you can go with LatticeSC and with V4FX up to 10G. hm, when Altera comes online I will sure look to see if they have something new. I bet not as they have told that all announcements are made and nothing is expected in short term. Altera 65nm FPGAs should be announced by the end of the 2006 not earlier.Article: 99585
Antti wrote: > you right, from germany web browser says that it cant find DNS lookup > and tracert dies on timeout somewhere in Santa Clara > > maybe Altera has announced Xilinx-killer and servers are overloaded on > US westcoast? Stratix-IIGX should be sampling this week, but I dont > think that is that big news that makes servers to shut down. It's also off from NZ.... Still, it is Sunday there ? - and ESC is next week, so perhaps they are doing a big web overhaul... ? -jgArticle: 99586
"Mich" <michiel.vanderlinden@gmail.com> wrote in message
news:1143374491.123467.22910@t31g2000cwb.googlegroups.com...
> Hi
>
> I have added it in the pao file and placed the sub module first
>
> lib IP_COMP_v1_00_a teller4 vhdl
> lib IP_COMP_v1_00_a user_logic vhdl
> lib IP_COMP_v1_00_a IP_COMP vhdl
>
> I still get the same error.
>
> Is there something I do wrong?
How are you instantiating "teller4"?
If you are using something like "teller4_inst: entity
IP_COMP_v1_00_a.teller4 generic map(...) port map(...);" then you should be
OK. If you are just doing "teller4_inst: teller4 generic map(...) port
map(...);" then you probably need to make some definition of teller4 visible
in the module in which you're instantiating it. So either a local component
statement, or a component statement in a package which you then "use" at the
top of the file, or (quicker) switch to the first style of direct entity
instantiation.
HTH,
-Ben-
Article: 99587Austin Lesea wrote: > Chris, > > Brings up a question for the group: how many lines of verilog can you > fit in any given FPGA? > > Anyone out there in the ASIC emulation world care to comment? There is no answer for that, it is very dependent on the designs and the application field. Processors and telecom chips have quite different needs for the FPGA for example. In the telecom side usually there is enough DFFs and logic resources. And the FPGA size can be determined with the help of internal ram resources. --KimArticle: 99588
Hi Marco. I tought that I could use LwIP without any OS. Think I have read that someplace but could not find it again now. I don't know yet what the error is, but it might be that LwIP needs the xilkernel (I don't know yet). I have some interrupt in my work now and I am going to have to take up the thread again in the next week. Do you know if the LwIP needs an OS of any kind (as spoken, I thought that it supported OSless systems). My system is now without OS. If it needs an OS I will maybe consider Linux instead of xilkernel. RaymondArticle: 99589
Well we might beat them out with Tarfessock1 after all then. John Adair Enterpoint Ltd. - Soon to be Home of Tarfessock1. The PCMCIA Spartan-3E Development Board. http://www.enterpoint.co.uk "Antti" <Antti.Lukats@xilant.com> wrote in message news:1143441448.222657.261710@t31g2000cwb.googlegroups.com... > Xilinx can safely say so, Avnet is good by taking orders now and > shipping 6 months later. Avnet was the first to announce V4 evalboard > availability so of course I placed order immediatly. When those 6 > months elapsed, well at the time I finally got Avnet board I could have > received some better board. But I had already order pending at Avnet, > because of their advance announcement. Nice marketing politics. Works > one time. You get pissed once, and you will avoid Avnet later if you > have options. Sure after Avnet swallowed Memec there isnt many options > to get Xilinx silicon and/or boards so you are stuck with Avnet one way > or another (as long as you stick with Xilinx). Hm I kinda understand > why it took so long for Avnet to get the approval in court to buy memec > (because of the anti-monopoly laws). > > Ok, ok maybe its all not so bad, maybe I am just releasing the monday > morning steam, maybe all other have very good experiences with Avnet > and have received the orders on time (not sooner not later), etc, etc.. > if that is the case then sorry (to Avnet). >Article: 99590
It's also down here (Edinburgh). I'm going to need some information later, can someone post up an IP address? Thanks in advance, NialArticle: 99591
Hi Brannon, can you remember what clock rate you were getting on which architecture when you implemented this algorithm? Cheers, RobinArticle: 99592
>It's also down here (Edinburgh). > >I'm going to need some information later, can someone post up an >IP address? > >Thanks in advance, There's no point having an IP address because the site doesn't respond, even when you have one. I contacted our distributor. They haven't been able to reach Altera either e.g. when visiting customers on Friday. They sent me the file I've been trying to download since last week (presumably from their existing copy), but it's a rather comical way to operate in 2006.Article: 99593
"Antti" <Antti.Lukats@xilant.com> writes: > you right, from germany web browser says that it cant find DNS lookup I have no problems: $dig www.altera.com | grep ^www.altera.com www.altera.com. 511 IN A 66.35.227.20 $wget http://www.altera.com/literature/hb/stx2gx/stxiigx_handbook.pdf Gives me the Stratix IIGX handbook without problems. BTW I'm located in Oslo, Norway. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 99594
"Nial Stewart" <nial@XXXXnialstewartdevelopments.co.uk> writes: > It's also down here (Edinburgh). > > I'm going to need some information later, can someone post up an > IP address? $dig www.altera.com | grep ^www.altera.com www.altera.com. 511 IN A 66.35.227.20 Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 99595
Hi Nial, I can see it ok from here in Ireland.... Alan Nial Stewart wrote: > It's also down here (Edinburgh). > > I'm going to need some information later, can someone post up an > IP address? > > Thanks in advance, > > > Nial > > >Article: 99596
Hi, is any spartan FPGA is in PLCC package?also its availabilty ? I want to use spartan series FPGA & not the any other spartan seris like spartan 2e etc. which sprom should be used?Article: 99597
On 26 Mar 2006 23:13:53 -0800, "Antti" <Antti.Lukats@xilant.com> wrote: >you right, from germany web browser says that it cant find DNS lookup >and tracert dies on timeout somewhere in Santa Clara > >maybe Altera has announced Xilinx-killer and servers are overloaded on >US westcoast? Stratix-IIGX should be sampling this week, but I dont >think that is that big news that makes servers to shut down. > >If you havent decided on the silicon yet, then well Xilinx has finally >solved their issues with V4FX silicon and LatticeSC also provides >SERDES up to 3.4G, and excpet S2GX I dont see anything on Altera that >could be of interest. > >Cyclone/II is beaten with Lattice ECP2 >MaxII is beaten by Lattice machXO >small PLD from Altera arent on the menu for longer time, so what >remains? > >S2GX could be still of some interest, maybe, but here also if you arent >going to use 6G SERDES then up to 3.4G you can go with LatticeSC and >with V4FX up to 10G. > >hm, when Altera comes online I will sure look to see if they have >something new. I bet not as they have told that all announcements are >made and nothing is expected in short term. > >Altera 65nm FPGAs should be announced by the end of the 2006 not >earlier. I assume that the features which you mention (e.g. 3.4GHz SERDES) are of particular interest to you. They are of no interest to us. When I buy a car, I want a reliable brand with good support. You're simply telling me that I need a Ferrari and that everyone needs a Ferrari. Since you don't know our application or how many devices might be sold, you can't weigh device capabilities and costs against the advantages of good design tools and support, which is my present concern.Article: 99598
All, I can assure you that the site is up, but we are having technical problems that are being worked as I type. I can not give an ETA to normal operation at this time. Tim Colleran Altera Corp.Article: 99599
dotnetters wrote > We're working with a Xilinx Virtex II Pro board. As a part of our > project, we had to write a hardware stack. After having made it work, > we thought of optimizing the design and hence removed a few states and > reduced the no. of states from 8 to 4. The older code was getting > synthesized in around 20 mins, but the new code takes hours together to > get synthesized, and so does the PAR. How can we reduce the synthesis > time? Why is that the code which took lesser time to get synthesized is > now taking longer? Try Synplicity. You may well get some insight from using another compiler - different warnings, unexpected resource usage, and so on.
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