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Hi Ray, > I don't have any shrink-wrapped off the > shelf IP for a general purpose Bresenham's implementation, but have > several implementations that are close that I could modify. These are > in VHDL for xilinx. If they're in VHDL, why would they only be for Xilinx? ;-) BenArticle: 84701
Hi Brad, > Are there any Bresenham line drawing algorithms that > are suitable for FPGA pipeline video streaming? In VHDL? I think there's a line-drawing implementation somewhere on www.niosforum.org in the "own IP" section. I remember it not being pipelined, but you could set up a coordinate FIFO or so. Best regards, BenArticle: 84702
Hi - On 24 May 2005 01:57:32 -0700, "techie" <tech_11153@rediffmail.com> wrote: >I am new to varification field. i have just written small test benches >but for the first time i have to write a big. The equirement is like >this. > >The main test bench should run from ModelSim. The selection of the UUT >will be through VHDL. Once invoked, the code will pause and query the >user for the stimulus file name and output file name. > >Compare the generated and the expected results and should disply the >warnings and error. Also should generate a output file for this. > >Can anyone guide me. > >Thanking you. The best book I've read on the subject is "Writing Testbenches: Functional Verification of HDL Models" by Janick Bergeron. http://tinyurl.com/865bq Bob Perlman Cambrian Design WorksArticle: 84703
Ben Twijnstra wrote:
> Hi Ray,
>
>
>>I don't have any shrink-wrapped off the
>>shelf IP for a general purpose Bresenham's implementation, but have
>>several implementations that are close that I could modify. These are
>>in VHDL for xilinx.
>
>
> If they're in VHDL, why would they only be for Xilinx? ;-)
>
> Ben
>
I've got lots of VHDL (and Verilog) only for Xilinx. Instantiate a
Xilinx primitive and it suddenly becomes very difficult to synthesize
using Altera tools (unmodified, that is).
Jake
Article: 84704Thanks for the info, Austin (and Greg). So the question goes back to Altera: Was the "NIOS Development Board from Altera" which "features a PLL-capable APEX EP20K200E-2X" laid out with good, low-noise design rules for planes for the VCC_CKOUT2 and GND_CKOUT2? I've never considered any FPGA or CPLD to be capable of producing very low jitter outputs because of all the digital activity going. The Xilinx noise seminar suggested (my impression) that only signals within an I/O bank *significantly* change the noise characteristics of an I/O on that bank; the effect from signals in other banks is negligible. If a clock output was the only output on a bank (the CKOUT2 realm perhaps?) perhaps noise could me mitigated. While the Xilinx "Tech Topic" results are from a competitor, the equipment and setups should be solid. So, did Altera do their job right with the board? Or are there other Altera documents to support the use of a digital circuit in a precision analog system? "austin" <austin@xilinx.com> wrote in message news:42936F9F.6060700@xilinx.com... > Also note that jitter is transferred from the core, power, and IOs to > the PLL. > > See out technical note: > > http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf > > Austin > > > gregs@altera.com wrote: > > > Nicolas, > > The output jitter spec on APEX 20KE devices is .35% of output period, > > but it is RMS, not peak-to-peak. The conversion from RMS to > > peak-to-peak depends on the desired bit error rate and the observation > > period. But if you are getting 800 ps total jitter, that is reasonable > > for a 73 ps RMS jitter. > > > > So the next question on your mind will be "How to reduce output > > jitter?" > > > > First off, examine your input jitter. The device spec is 2% of the > > input period peak-to-peak, so 333 ps peak-to-peak jitter is acceptable. > > However, reducing the input jitter can reduce your output jitter in > > some circumstances. The key factor is the frequency of periodic jitter > > components. The bandwidth of the APEX 20KE PLL is around 5 MHz, so > > jitter below that frequency will pass but jitter above that frequency > > will be attenuated. For example, if the 60 MHz input signal is > > modulated by a nearby 1 MHz signal, then that 1 MHz jitter will pass > > through the PLL. On the other hand if it the jitter is random jitter, > > or higher-frequency jitter, then the PLL will attenuate this jitter. > > > > To break this down to practical advice, take a look at the jitter of > > your clock source with a tool like an Agilent DCAJ, LeCroy SDA6000A, or > > Wavecrest. These can break down the jitter into deterministic and > > random components, and also can show you information about the > > frequency components of the jitter. For example if the clock is coming > > from an oscillator that is routed through another device like a CPLD > > you may be picking up some jitter there. > > > > The second thing to look at on the system is the board layout of the > > APEX device. The APEX devices have separate VCC and GND pins for each > > PLL, and these should be isolated from the VCC and GND used by the > > logic or IOs of the device. There's also a separate VCC and GND pin for > > the clock output, and again you may want to isolate these VCC and GND > > pins from other ones, otherwise noise on VCCIO will show up as jitter > > on the clock output. You can determine if these are the problem by > > looking at jitter with and without the logic and IOs toggling - if the > > jitter is worse with toggling then this would be a good place to look. > > App Note 115 on the Altera web site has some more details. > > http://www.altera.com/literature/an/an115.pdf > > > > Sincerely, > > Greg Steinke > > Altera Corporation > > gregs@altera.com > >Article: 84705
Jim,
You must have vcom.exe in your Path. In other words, the variable PATH
must include something like "C:\Modeltech_6.0c\win32" (or wherever your
Modelsim executables live).
Best regards,
Ryan Laity
Xilinx
zoinks@mytrashmail.com wrote:
> Hello,
>
> I have a problem simulating a design made in Xilinx Platform Studio
> with EDK 6.3.
>
> The thing is, I cannot get compedklib to work. It cannot detect my
> ModelSim simulator, and therefore it will not compile the libraries I
> need for my simulation.
>
> I'm using the 6.3 EDK and ModelSim SE 6.0c.
> Does anyone know which environment variables I have to set for the
> compedklib to detect my installation of ModelSim?
>
> I have the following system variables:
>
> XILINX=c:\Xilinx
> XILINX_EDK=C:\edk
> MODELSIM=c:\modeltech_6.0c\modelsim.ini
> LMC_HOME=C:\Xilinx\smartmodel\nt\installed_nt
> LM_LICENSE_FILE=<..bunch of IP adresses..>
>
> all the paths above are correct.
>
> Does anyone else experience this same problem?
> Or does anyone using a similar config have a working system?
> Your help is appreciated.
>
> Thanks in advance,
> Jim Tuilman
>
Article: 84706Hi Jake, > I've got lots of VHDL (and Verilog) only for Xilinx. Instantiate a > Xilinx primitive and it suddenly becomes very difficult to synthesize > using Altera tools (unmodified, that is). What kind of stuff do you need to instantiate then? I can imagine the DCMs and the MGTs because they're highly dedicated silicon, but every time I see a BUFG or a MUXCY - or even an SRL16 instantiated I tend to choke - XST by now should be quite capable to infer those itself. Heck, I once visited a company that instantiated all its multipliers where a simple '*' operator would have sufficed. IMHO, instantiating vendor-only stuff only distracts from what you're trying to do - but that's probably my Mentor background. Best regards, BenArticle: 84707
What kind of Xilinx FPGA do you use? Most Xilinx FPGA device, Spartan and Vertex, have DLL(PLL). If you want to divide clk, you should use internal DLL to reduce skew and easy use. If else, you should use IBUFG(clock input buffer) for input and OUBF(output buffer) for output.Article: 84708
Hi Dave, > VHDL makes > designing complex and/or large hardware very easy compared to schematic > entry... A tool is only as capable as the person using it. For the same "function", some can easily create schematics as fast as anyone can code in HDL, if that schematic person knows what they are doing. The key is symbol libraries, and better yet, tested libraries (thank you Philip ;-)...which allows hierarchical, basically, drag and drop, schematics. This can be done with datapaths, as well as state machines, functions etc. It's as good (or as poor) as you want it to be, depending on how much work you put into your libraries. Of course, it takes time to build up a good library, but not *that* much time, and the time it saves in the long run can be huge. People seem to like to draw gates...why I don't know. My schematics are like block diagrams, and alleviate the "need" that people have to turn HDL code into block diagrams to understand what it does. I won't contend that if starting from scratch, HDLs will typically have an edge on time to completion, and the tools today are far better than a decade ago, but that does not diminish my point. IF someone had come out with a library that was publicly available, schematics would have been quite a bit more popular. This capability (having a large library of pre-built schematic modules) was a huge advantage I had for many years being an independant contractor. I was able to do designs that met performance goals of speed and resource utilization, as well as do them very quickly and cost effectively. But, basically, schematics for FPGAs, at least Xilinx FPGAs, are dead today, IMO. But, without schematics, I could not have done the designs I did in the earlier Xilinx series parts (2k, 3k & 4k), as the synthesis tools were rather poor back then, and required far more work to get the results to come close to the speeds (and densities) achievable with schematics. Using an HDL simply as a netlister is not a very good use of the tool IMO...but now, that is the only way to get every Hz out, is to instantiate what you need to using HDL. Sigh. There is not a thing wrong with schematics compared to HDLs, and schematics even have many advantages, but today, they just aren't popular. HDLs are. It has not a wit to do with schematics lack of ease or capabilities. Regards, AustinArticle: 84709
Ben Twijnstra wrote:
> Hi Jake,
>
>>I've got lots of VHDL (and Verilog) only for Xilinx. Instantiate a
>>Xilinx primitive and it suddenly becomes very difficult to synthesize
>>using Altera tools (unmodified, that is).
>
> What kind of stuff do you need to instantiate then? I can imagine the DCMs
> and the MGTs because they're highly dedicated silicon, but every time I see
> a BUFG or a MUXCY - or even an SRL16 instantiated I tend to choke - XST by
> now should be quite capable to infer those itself. Heck, I once visited a
> company that instantiated all its multipliers where a simple '*' operator
> would have sufficed.
>
> IMHO, instantiating vendor-only stuff only distracts from what you're trying
> to do - but that's probably my Mentor background.
I agree -- the synthesis tool should do a lot of this. And they're
getting pretty good. Ray has been around a while. He's got lots of
stuff that was written to pull every bit of speed from the devices. To
do so meant (and still means, sometimes) to force certain structure on
the design.
Also, XST changes what it does from version to version. Writing
structural HDL makes the design immune to these changes at the expense
of readability. For a lot of optimized blocks, it's best just to tell
the tool exactly what you want and then not worry about it changing the
results as the rest of the design changes.
For example, the mults are relatively new to the FPGA. I remember old
designs where writing "*" would blow up into using half of the gates of
the entire FPGA (when the 4062 was a big device). CORE modules or
hand-written mults were the only way to go.
Jake
Article: 84710
The Bresenham Line drawing algorithm can be farily easily unrolled and
pipelined for streaming implementation. I haven't done the algorithm by
itself, but I have used it an unrolled version of it for other
applications. One that comes to mind was for computation of a gradient
for a zoned image (the image was split into 4 quadrants for a coloring
algorithm. The effect was faded from the midpoint of each quadrant into
the adjoining quadrant. Rather than using tables or additional
multiplies, the x and y coefficients for the quadrant contributions for
each pixel were computed using Bresenham's algorithm (thereby
eliminating the multiplies). I don't have any shrink-wrapped off the
shelf IP for a general purpose Bresenham's implementation, but have
several implementations that are close that I could modify. These are
in VHDL for xilinx.
Brad Smallridge wrote:
>Are there any Bresenham line drawing algorithms that
>are suitable for FPGA pipeline video streaming? In VHDL?
>
>b r a d @ a i v i s i o n . c o m
>
>
>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84711
zeeman_be wrote:
>Hi Antti,
>
>I agree with everything you said.
>I also encountered the ChipScope issue on a Virtex4 design with the
>ISE7.1 tools. Either disabling the "Use SRL16" or disabling the "Use
>RPM" provided a good workaround.
>
>
I know exactly what the issue is, and it is in 6.3 as well as 7.1. The
problem is there is a bug in the RPM grid resolver that doesn't take
into account BRAM or DSP48 columns. If your RPM has placed elements
that require an M-slice (SRL16 or lut RAM), and that slice is placed
within the RPM so that there is a non-lut column between it and the RPM
origin (lower left corner), it barfs because it lost track of the which
column is the M-slice column when it crossed over the non-LUT column.
This becomes crucial in devices like the V4sx55 where you only have four
lut columns between non-lut columns, as it becomes impossible to place
such an RPM where it doesn't straddle a non-lut column. In my case, I
was able to work around it by assigning the resources in the RPM to
different HUSETs, depending on which column they fell in, and then
putting separate RLOC_ORIGINs on each HUSET. they told me it would be
fixed in the next service pack. FWIW, it is case 578431-1. Xilinx says
it only affects locked macros, but that is not entirely true: it will
allow an unlocked macro provided the placer can find a place to put the
macro where it won't straddle a non-lut column. This may not be the
possible with some of the V4 devices and larger macros.
Disabling USE RPM will sidestep the problem, but it also throws away
all the placement information, so it may not allow you to meet timing if
you are pushing the performance envelope. Turning off use SRL16 avoids
the problem by making so there are no slice_Ms in the design. You pay a
price in increased area and power consumption, however.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84712> "Nicolas Matringe" <nic_o_mat@msn.com> schrieb im Newsbeitrag > news:1116938369.355985.65660@z14g2000cwz.googlegroups.com... > http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=21127&iLanguageID=1 Now this is interesting stuff... and stuff that would've definitely bitten me later on... You have to configure the FPGA in less than 10 minutes after powerup, or the DCMs might not work as expected. Same if your reset is active for more than 10 seconds. Any insights as to why that is? Sounds to me like one of those "features" I wouldn't know how to implement if I wanted to :) cu, SeanArticle: 84713
It is basically an FIR core with the delay queue stripped off. Which
device family? What is the data rate?
If you don't have, don't have enough or don't want to use the embedded
multipliers, you can also use a distributed arithmetic approach. One of
the advantages of not relying on the xilinx cores is that somethinglike
this is easily extracted from the existing library.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84714"Sean Durkin" <smd@despammed.com> schrieb im Newsbeitrag news:4294132f$1@news.fhg.de... > > "Nicolas Matringe" <nic_o_mat@msn.com> schrieb im Newsbeitrag > > news:1116938369.355985.65660@z14g2000cwz.googlegroups.com... > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=21127&iLanguageID=1 > Now this is interesting stuff... and stuff that would've definitely > bitten me later on... You have to configure the FPGA in less than 10 > minutes after powerup, or the DCMs might not work as expected. Same if > your reset is active for more than 10 seconds. > > Any insights as to why that is? Sounds to me like one of those > "features" I wouldn't know how to implement if I wanted to :) > > cu, > Sean Hi Sean in order to understand whats and why I guess you need to get educated on the topic named 'NBTI' I wasnt aware also that such kind of things could be happen on shipped tested silicon. one another comment I have heard on the AR21127 was "bizzare" I think thats an excellent comment. short and kinda says it all ;) AnttiArticle: 84715
> There is not a thing wrong with schematics compared to HDLs, and > schematics > even have many advantages, but today, they just aren't popular. HDLs are. > It has not a wit to do with schematics lack of ease or capabilities. > I agree with that. BTW: Altera / Quartus has still a very good schematic editor. The only problem (surprise): It is not vendor-independend. If you have a large schematic design, it would be a huge effort to transfer this to e.g. Xilinx. Many people explained correctly that you have to think "hardware" when you are writing VHDL. Therefore I think, graphic design is even a "higher level language" then VHDL because the schematics are better human readable in many cases. For e.g. state-machines and simulation, things are different, of course. So a mix of VHDL and schematic design (top-level: schematic, with sub-modules that may also be in VHDL) would be perfect. Is there any good tool out there that can convert such a graphic/VHDL-mixture into a vendor-independent VHDL-design? Regards, Thomas www.entner-electronics.comArticle: 84716
Hi, take a look at Opencores Ethernet mac (http://www.opencores.com/projects.cgi/web/ethmac/overview) It's easy to use and works very well. I have used this core in several projects with great success. You only need an external Phy connected to the FPGA (e.g. Intels LXT971A). The businterface to external uc is a wishbone bus (defined by opencores).Article: 84717
Thanks Berty This is not fun If I can do it I'll earn money (I hope). I must make network for up to 100 devices and every device need 2.5Mbit/s so I think this is not simple. I want to run 10 devices together now. Your I2C example is very good. You can recommend Eth Mac (I think this is ethernet controller like as RTL8100). If I you Eth Mac I think I can done for a month.Article: 84718
Hi AVG, (http://www.opencores.com/proje=ADcts.cgi/web/ethmac/overview) is verilog? I can write VHDL, can I use it as component?Article: 84719
hi Ed, I found I/O expansion header port with JTAG pins. Can I use it for my JTAG PC-3 cable instead of having PC-4. If so how can I do that and what kind of jumper settings I have to do on my ML403 board. Even I am trying to use compact flash but I found some problem in converting .bit file to.ace file. I used iMPACT to convert the file format but when I want to configure the device with the new .ace file the Err led lights on with red. What could be the problem. Please do u suggest me the best way to configure the device on ML403 board. regardsArticle: 84720
Hi, yes you can. Mixed languages designs are no problem. You can instanciate a verilog component inside a vhdl unit without any problems.Article: 84721
Are there additional command or setup? Can I syntesis without problem as writing vhdl component?Article: 84722
Hi Thankyou for comment.... Now I am making effort fixing,,,,,,with no luck.... But I found that this problem is not related with BRAM..... Is someone aware of the information below? I am doing XST synthesis (without special constraint and without UCF)..... Thankyou for comment again :) ----------------------------------------------------------------- INFO:LIT:95 - All of the external outputs in this design are using slew rate limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the schematic. INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "CLK_bufg" (output signal=3Dclk_int2) ------------------------------=AD------------- -------------------------Article: 84723
Hello.. Is there any tool that generates the .mem ROM files from a binary or intel hex file compatible with Lattice Module/IP Manager? regards jediArticle: 84724
It depends on your synthesis tool. I do my synthesis with Precision + ISE for Xilinx and with Quartus for Altera. There are no special commands required to synthesise verilog files. You only have to add the verilog files to your synthesis project like your vhdl files. It's really very easy.
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