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On 10 May 2005 03:48:12 -0700, stud_lang_jap@yahoo.com wrote: >Hello Guys, >I have to divide an clock by 2.5. I cannot use the DCM of virtex 2 pro >has my clock is 10 MHZ which is too less for the DCM to handle. >I think this division can be done using state machine (posedge and >negedge).....but i cannot figure out on what state should i derive the >clock and how many state are required?? > >Can any one please provide suggestions > >thanks and regards >williams http://www.fpga-faq.org/FAQ_Pages/0019_Divide_Clock_By_N_point_5.htm Philip Freidin FliptronicsArticle: 83951
Did some more research on this... Obviously the ECP port test fails when iMPACT or ChipScope try to open the cable. ChipScope 7.1 is more verbose "Expected 00 but read 20", hence it suspects ECP is not working and uses compatibility mode. It obviously does not matter what BIOS-Settings or driver settings in Windows you use... Xilinx uses Windriver from Jungo to talk to the cable, and this is what I found on their website: http://www.jungo.com/support/faq.html#lfc11 "Parallel / Serial Port Issues I am using WinDriver for communicating peripherals with the parallel port. In case of ECP mode, some computers work well, but on one computer this does not work. This might be a hardware problem, due to BIOS-specific implementations of parallel port modes on various computers. WinDriver cannot control this behavior, since it is programmed into the BIOS. We advise you to follow the brand of computer or BIOS that you have observed works correctly." OK, so it's all the BIOS' fault and I'm supposed to only use computer with compatible ones. That is one hell of an elegant solution. cu, SeanArticle: 83952
Philip Freidin <philip@fliptronics.com> wrote: : http://www.fpga-faq.org/FAQ_Pages/0019_Divide_Clock_By_N_point_5.htm From which the following reference is particularly relevant, as it includes a divide-by-2.5 circuit: http://www.xilinx.com/xcell/xl33/xl33_30.pdf Richard. http://www.rtrussell.co.uk/ To reply by email change 'news' to my forename.Article: 83953
Rudolf Usselmann wrote:
> I guess it all depends on your needs. If the 245 will do the
> trick than great ! If you need bidirectional signaling, than
> the 3010 might be a better option.
Yes, in this case 245 cannot be applied, thay are
pseudobidirectional and coarse-grained (i.e. the
direction of all 8 signals must be identical). But
in my project it's not the problem. BTW, my local
distributor sells much more powerful 1C3 speed
grade 8 Cyclones considerably cheaper than 1K30
ACEXes; even with 8xLVC245 the price is still lower.
Strange, but Cyclone is the winner, so I'll use it in my
cost-sensitive project. :-)
Best regards
Piotr Wyderski
Article: 83954
Piotr Wyderski wrote:
> BTW, my local distributor sells much more powerful
> 1C3 speed grade 8 Cyclones considerably cheaper
> than 1K30 ACEXes; even with 8xLVC245 the price
> is still lower. Strange, but Cyclone is the winner, so
> I'll use it in my cost-sensitive project. :-)
And another thing I forgot to mention: an Atmel
2313 + AT45DB011B-SI 1MBit serial DataFlash
is over 2 times cheaper than the EPC1
configuration memory -- why are Altera's
config devices so expensive?
Best regards
Piotr Wyderski
Article: 83955On Mon, 09 May 2005 21:00:04 -0700, praveen.kantharajapura wrote: > Hi peter, > > So what you mean to say is in simple dual port memories one port is > restricted only for write, and the other one only for read. > > I read in ALTERA cyclone FPGA's that there memory blocks can be used as > > 1)Simple dual port memory. > 2)True dual port memory. > 3)FIFO buffers. > Is it the same in XILINX. > > But according to your explanation Simple dual port memory is nothing > but a FIFO, so why have they explicitly mentioned as FIFO buffers. > You can use the memories in a variety of ways, but they are all based on either single-port, simple dual-port (independant read and write ports) or true dual-port (independant bidirectional ports) arrangements. The idea of a simple dual port memory is that often it is all you need - for example, it forms the basis of a FIFO - and can be (on Altera devices - I don't know about Xilinx) twice as wide as true dual-port arrangements. So you use simple dual-port where it is sufficient, and true dual-port where it is necessary. Xilinx devices also have some hardware specifically for making fast FIFOs (along with a simple dual-port ram block). I've no idea whether this is faster than corresponding soft logic on Altera devices, but Xilinx certainly considers it a marketing point so there is presumably some advantage. > Please clarify on the 3 types of memory usages. > > Thanks in advance, > PraveenArticle: 83956
Peter Alfke wrote: > > Just remember: delay is from source to destination, skew is between > destinations. I believe what you explained above is correct. I have one confusion on the Xilinx "place and route" timing report. I got a timing result (a skewtest module using Xilinx spartan III - XC3S1000FG320) like this: ----------------------------------------------------------------------- Slack: -0.659ns CLKEXT Error: 0.759ns skew exceeds 0.100ns timing constraint by 0.659ns >From To Delay(ns) Skew(ns) DCM_X0Y1.CLK0 V2.O1 3.608 0.745 DCM_X0Y1.CLK0 T5.O1 3.587 0.724 DCM_X0Y1.CLK0 V3.O1 3.579 0.716 DCM_X0Y1.CLK0 T4.O1 3.622 0.759 ------------------------------------------------------------------------ I can understand that the 3.608ns is the delay from DCM_X0Y1.CLK0 to V2.01. I don't know what 0.745ns skew stands for, since there is only ONE destination (V2.01). Can you shed some light on? Thank you in advance. Regards, Jane DSP System EngineerArticle: 83957
Here are some tricks: If you have a true dual-port RAM, but need only a single port, you can 1. divide the RAM in two (evenly or non-evenly divided) pieces, and address each from its own port. Now these two RAMs are completely independent, but are each single-port. 2. You can make the RAM wider (but also shallower). In Virtex, the widest dual-port BlockRAM is 512 x 36, but you can make it into a single-port 256 x 76 memory. Just remember, you cannot increase the size of the starage array... Peter Alfke, (with a name like this I can never hide), Xilinx ApplicationsArticle: 83958
I know of several FPGA project currently running, and using the XP10, and it looks promissing! You mention all the great benefits og the XP, and they work as Lattice prommise. Althoug the Xp are very new, its predecessors (EC, ECP) works perfectly, and since Fujitsu produces the chip using 130nm tecknology, the chip is built on well testet producion methods. Unfortunetly I have not had time to get my hands dirty with it yet;)Article: 83959
<stud_lang_jap@yahoo.com> wrote in message news:1115722092.337801.26280@f14g2000cwb.googlegroups.com... > Hello Guys, > I have to divide an clock by 2.5. I cannot use the DCM of virtex 2 pro > has my clock is 10 MHZ which is too less for the DCM to handle. > Untrue. Use the DCM to multiply by 4 using the CLKFX mode. The minimum CLKIN is 1MHz in this case, CLKFX output still has a minimum of 24MHz but that's OK as you've now got 40MHz. Divide that by 10. Cheers, Syms.Article: 83960
I hate to say this, but you are trying to do the impossible. If you feed a common reference frequency to several chips, and locally divide or multiply the frequency by the same number in each chip, there is NO WAY to automatically assure synchronism between the chips. Your only solution is a separate communication link between the chips that enforces synchronism. (Once successful, the link becomes redundant, but it will be difficult to take advantage of that.) Far-out scheme: You could skip one period of the common clock, and locally detect that missing pulse as a synchronizing mark. But don't try that with DCMs... Peter Alfke, Xilinx ApplicationsArticle: 83961
Thank you for your advice. In fact, I just have to program the FPGA. I have no SPI to do it, just GPIO pins. On the FPGA board, I have access to PROG_B, DIN, CCLK, DONE, INIT_B and the JTAG pins. How would you program it using the slave serial configuration mode? What file you send on the FPGA, the .bit file or another? Which bit you send first? Are there any potential problems due to the 3,3V voltage I have on the GPIO pins or is it fine? (Spartan-3) Thank you for your helpArticle: 83962
Hi, a reload usually fixes this problem for me. PS: I will ask Digilent about the DDR speed, once I get a response to my first email question :) regards, BenjaminArticle: 83963
Hi Martin, do You store an entire frame in the fpga ram, or just one line and keep the DVI and Display LVDS synchronized using the variable hsync period of the LCD? Do You do any image processing in the fpga, overshooting or scaling? regards, BenjaminArticle: 83964
Sorry, I got carried away: When you multiply the frequency locally, the chips are of course in step, and if you need to refer to the lower frequency, you have it at the input. No problem. The unsolvable problem occurs only when you do a local divide. Then the result is ambiguous between the chips, and there is no way to resolve that.. I hope I caught this mistake in time Peter Alfke, Xilinx ApplicationsArticle: 83965
See below,
jeycrisis wrote:
>Thank you for your advice.
>In fact, I just have to program the FPGA. I have no SPI to do it, just
>GPIO pins.
>
GPIO will do as well, use a bit for generating the CCLK and one bit to
shift out the data, one byte at a time, msb first.
before you start you toggle PROG_B to erase the configuration. (toggle
low then high)
>On the FPGA board, I have access to PROG_B, DIN, CCLK, DONE, INIT_B and
>the JTAG pins.
>How would you program it using the slave serial configuration mode?
>What file you send on the FPGA, the .bit file or another?
>
*.bit
> Which bit you
>send first?
>
msb
>Are there any potential problems due to the 3,3V voltage I have on the
>
>GPIO pins or is it fine? (Spartan-3)
>
Add a 100 ohm in series with CCLK and D0 assuming 3.3V on your gpio pins.
>Thank you for your help
>
>
>
After you shift out all the *.bit content issue some extra CCLK periods
( ~20 ) to make sure that the part is starting.
and be careful to generate the bitstream with cclk as a startup
clock (not jtag) from ISE bitgen options
Have fun,
Aurash
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 83966Hi, I talked to Digilent on the phone. They didn't know exactly how fast the ram can go. Here is what I find in the users guide of the board: These memory modules are designed for a maximum clock frequency of at least 133 MHz and have a CAS latency of 2.5 (18.8 ns). The PLB Double Data Rate Synchronous DRAM Controller supports CAS latencies of two or three clock cycles. If the memory system is to operate at 100 MHz, then set the CAS latency parameter in the controller design to 2 (20 ns). If full speed (133MHz) memory operation is required, then set the CAS latency parameter in the controller design to 3 (22.6 ns). What I don't understand is, whether the 133 MHz is the maximum clock or not. Can it run 200 MHz as well? regards, BenjaminArticle: 83967
Thank youArticle: 83968
Peter - Thanks for the feedback. As I noted in my original posting, I can cleanly stop the input clock to the DCM, assert the DCM reset, then cleanly re-enable the clock. Since I am using the CLKIN_DIVIDE_BY_2 mode, my question is if that "input" divider on the DCM gets reset by the DCM RST pin or not. If it is reset by the RST pin, then all the DCMs in my system should be able to be "in-sync". Thanks for being a great resource in this forum! John ProvidenzaArticle: 83969
I'm about to use Virtex 4, and wonder if this is achievable. All literature seems to indicate that it is, but I'd like hear what others think and perhaps point out where I need to be careful in the design. I'd be receiving an LVDS clock pair @ 360Mhz, running part of the internal logic at 360. This internal logic includes DSP48 slices (but need to be pipelined in the fabric since I need more than 48-bit 'C' input for adder). Preliminary testing indicates that it can go above 360 with light user intervention. One thing I'm cautious about is, the rest of logic runs much slower, at 90Mhz. Initially was thinking of using /4 version, but Peter Alfke's post regarding added skews due to loading differences in DCM outputs is making me think about it carefully. For otuput, I'd be using ODDR to multiplex 360 Mhz logic, to send the data out at 360Mhz DDR (so the data can look like 360Mhz 'clock'). Data is LVDS, so is the forwarded LVDS clock pair @ 360Mhz. The receiving device will use both edges of the forwarded 360 Mhz clock to sample the data. Clock to output delay is not good, 3+ ns, but since the clock will be forwarded and will incur effectively the same delay as data (other than IOB-IOB clk skew), as long as I send out 180 deg version of internal 360 clock using ODDR, it should be ok. Not sure what kind of SI issue there will be, however. I have an option of running it at 180Mhz if 360 is risky. External device will be different. Am I playing too safe by going to 180? Will 360 be a challenge? I'd appreciate feedback.Article: 83970
<fastgreen2000@yahoo.com> wrote in message news:1115750937.589232.47940@f14g2000cwb.googlegroups.com... > I'm about to use Virtex 4, and wonder if this is achievable. All > literature seems to indicate that it is, but I'd like hear what others > think and perhaps point out where I need to be careful in the design. > > I'd be receiving an LVDS clock pair @ 360Mhz, running part of the > internal logic at 360. This internal logic includes DSP48 slices (but > need to be pipelined in the fabric since I need more than 48-bit 'C' > input for adder). Preliminary testing indicates that it can go above > 360 with light user intervention. One thing I'm cautious about is, the > rest of logic runs much slower, at 90Mhz. Initially was thinking of > using /4 version, but Peter Alfke's post regarding added skews due to > loading differences in DCM outputs is making me think about it > carefully. > Clock everything at the higher rate, use a clock enable for the /4. IIRC V4 can use a global clock net as an enable net. Well done Xilinx! > > For otuput, I'd be using ODDR to multiplex 360 Mhz logic, to send the > data out at 360Mhz DDR (so the data can look like 360Mhz 'clock'). > Data is LVDS, so is the forwarded LVDS clock pair @ 360Mhz. The > receiving device will use both edges of the forwarded 360 Mhz clock to > sample the data. Clock to output delay is not good, 3+ ns, but since > the clock will be forwarded and will incur effectively the same delay > as data (other than IOB-IOB clk skew), as long as I send out 180 deg > version of internal 360 clock using ODDR, it should be ok. Not sure > what kind of SI issue there will be, however. > > I have an option of running it at 180Mhz if 360 is risky. External > device will be different. Am I playing too safe by going to 180? Will > 360 be a challenge? > It's certainly within the realms of possibility. I do stuff like this at clocks >300MHz in V2PRO, with >600 Mbit outputs. So, gamble! You'll learn enough to get another job if it goes bad! ;-) Cheers, Syms.Article: 83971
Thanks for the reply. Questions about the clock enable : - Is there an easy way to specify it as clock enable, so the tool knows about it for timing analysis, and so you don't have to specify multi-cycle constraints for gobs of FFs? - And how do you make the enable signal go on the global clock net?Article: 83972
<fastgreen2000@yahoo.com> wrote in message news:1115753454.386148.6960@f14g2000cwb.googlegroups.com... > Thanks for the reply. > > Questions about the clock enable : > > - Is there an easy way to specify it as clock enable, so the tool knows > about it for timing analysis, and so you don't have to specify > multi-cycle constraints for gobs of FFs? > In Synplify there's an attribute, syn_direct_enable . Check out the reference manual. I imagine other synthesis tools provide something similar. In the UCF you then do something like:- NET "ENABLE_NET_NAME" TNM=FFS "ENABLED_FFS"; TIMESPEC TS1000 = FROM : ENABLED_FFS : TO : ENABLED_FFS : 11.1ns; > > - And how do you make the enable signal go on the global clock net? > You ask someone from Xilinx! I've not yet started my V4 design. I just remembered that from the marketing spiel we had. Cheers, Syms.Article: 83973
Looking to see if anyone out there has verilog or vhdl code that implements the "add on bus." Couldn't find any on opencores.Article: 83974
Thank you again, I thing I will try this option... Do I have to change something on MO, M1, M2, because on the board I am using there is no way to access these pins.
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