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Dave, DSP Builder 3.0 is still $1,995. Best Regards, Brian Jentz DSP Marketing Manager Dave wrote: > Hi All, > > Been trying to find out the cost of Altera DSP Builder 3.0.0. > > Can't find any pricing info anywhere on web (also tried calling but after > being shunted around gave up). > > V2.2 seems to have been $1995: > > http://www.altera.com/corporate/news_room/releases/releases_archive/2004/products/nr-dspbuilder.html > > Is this still the case for 3.0.0?Article: 82976
See the subject line. And, I have been posting, just not on your last thread, as I had nothing more to say. AustinArticle: 82977
Let us see if I can provide you with some guidance, Austin Benjamin Menküc wrote: > Hi, > > I am designing the following converter: LVDS -> some processing -> LVDS. > Each LVDS Interface has 3 channels and 1 clock channel at about 300 MHz > (differential clock rate). > > My question is if I should use GLCK pins for the incoming LVDS clock? Yes. Use an IBUFG for the clock, using a dedicated clock input pin. These have the lowest skew (delay) to get in the chip). > > Should I also use GLCK pins for the outgoing LVDS clock? No such thing. Any OBUF can duplicate a clock by using the DDR FF. Tie the top FF D input to a '1', and the bottom FF D input to a '0', and on the rising edge you will get an outgoing rising edge, and on the falling edge you will get an outgoing falling edge. All clocks internally should be on a BUFG so they may drive any IOB FF, or any CLB FF with the least skew. I don't think > so, because there is no OBUFGDS. Or does it make sense to use GCLK pins > for OBUFDS? > > Another question is the bank assignment. Should I put the complete > Interface (both LVDS) on the same bank? Yes. This is the least skew (delay) from the data bits to the clock (if they are adjacent). Or better each LVDS on its own > bank? Nope. Too much skew possible. Or do banks not matter at all? They do matter. > > regards, > BenjaminArticle: 82978
Austin Lesea wrote: > Coolrunner is a CPLD. > > Austin > > lecroy7200@chek.com wrote: > >>> There are no charge pumps in FPGAs now since Virtex (roughly 7.5 >> >> >> years). >> >> Just doing a quick search I find the Coolrunner is using a charge pump >> for the programming voltage. Just search the data sheet for "charge" >> and you will find it. .. and one hopes that this charge pump is only on, during programming. Otherwise it is turned off. -jgArticle: 82979
Jim, True. Charge pump in the CPLD is only needed for programming voltages of the EEPROM cells. AustinArticle: 82980
Hi Austin, thanks for the answer. >No such thing. Any OBUF can duplicate a clock by using the DDR FF. >Tie the top FF D input to a '1', and the bottom FF D input to a '0', >and on the rising edge you will get an outgoing rising edge, and on the >falling edge you will get an outgoing falling edge. How can I set the FF connections in the IOBs manually? In the lib.pdf I find only how to instantiate an OBUF, however I can only choose an input and output there. With this construction I have only a single clock, not a differential clk_n and clk_p. Is this correct? Shouldn't I generate the differential outgoing clock signal using a OBUFDS where I have just the clk_n or clk_p input. regards, BenjaminArticle: 82981
Hello Mohammed,
We will be adding support for unconstrained entity ports in 5.1,
due out later this year (we need to get 5.0 out first :-)). In the
interim please use the generic approach suggested by Ralf.
Hope this helps,
Subroto Datta
Altera Corp.
Article: 82982Teen, Quite frankly, you have not even scratched the surface of the issue you are asking about. There is probably ten years of research, results, products, etc. that you need to demonstrate a minimum of understanding of. There is another twenty years of hardware uP knowledge that you seem to be totally unaware of. The question itself speaks volumes. Open your mouth, and you remove all doubt of your competence. So, now that we know you know practically nothing, we can reply with something that will help you. FPGAs have long been known to take thirty transistors to do the job of a single transistor in an ASIC. The same is true for a microprocessor. It takes many more tranistors to the the job in an FPGA, than it does in a uP. Why would anyone in their right mind then use a FPGA? Because it can be anything, for anyone (it is programmable). An ASIC requires a great up front investment, and if anything is wrong, you pretty much throw most of it away, and start over. An ASIC also requires a task that is not going to change -- ever. Fine for a uP that has a language that no one will change (too many lines of code already written for it), but a system is always changing. NTT saved billions of dollars by using Xilinx FPGAs in their cellular base stations: they didn't have to remove all the equipoment from the field every time there was a change, they merely reprogrammed all the base stations. No genius required to see this advantage. So why use a soft uP at all? A uP is standard, so you don't need to change it, it uses software to program it (hence the flexibility is maintained), and it is going to be much faster, much smaller, and much lower power if the uP is hardened (made into a non-changing mask). Answer is, that unless you want to make a uP with a custom instruction set (that now limits us to probably less that .001% of all applications - and for them we offer the APU interface), there is no good reason. Hence why we offer the IBM 405 PPC in Virtex II Pro, and Virtex 4. But, what if I can replace a ton of gates and flip flops by a simple program (less than 1K words of instruction)? Hey, maybe there is a benefit to using a soft uP: I can actually use less area/power/gates/transistors in the FPGA with a soft uP, than I would use if I used FPGA logic to do the same job. Hence the fabulous sucess of the simple microcontroller core IP that we offer for both the 405 PPC, and MicroBlaze. Austin teen wrote: > Hello Antti, > > Thank you for your reply. I had disclosed my identity in > the mail(regards, Kishore) . Please read the mail again. > > Also I competely disagree with your assumption that I haven't done any > homework. After I had gone through a couple of pages collected through > I had some ambiguity in the differences between the two CPU's , So I > had asked the above question only to refine my web searching. > > Pease be straight forward while giving any suggestions. > > Regards, > Kishore >Article: 82983
We use the same inferencing independent of the target FPGA. The differences are in how we map the inferred abstract RAM to the target FPGA. - Ken McElvain Synplicity, Inc. neilla@ewst.co.uk wrote: > Well in the release notes for Synplify 8.0A (downloadable from the > Actel website) it has the following: > > For the Actel ProAsic Plus family, the synthesis software now extracts > single-port and dualport versions of the following RAM configurations: > > SA Synchronous write, asynchronous read > SST Synchronous write, synchronous read, transparent output > SSR Synchronous write, synchronous read, registered output > > For RAMS that are bigger than the basic block size of 256x9, the > software infers them by cascading similar kinds of basic blocks. For > wider RAMs, the software cascades basic blocks so that the same kinds > of inputs are tied together. For deeper RAMs, the software cascades > basic blocks and uses decoding logic. > > > So it looks like it is now possible to infer the RAMs, but I haven't > tried it yet, so am not sure how good it is, or what the HDL template > required is. >Article: 82984
Hi all, I would like to get into a CAM design for FPGA. Does any of you know about where can I find material on this subject? I will appreciate stuff like tutorials and reference designs (examples in any HDL).. Thanks in advance, Moti.Article: 82985
"Weng Tianxiang" <wtx@umem.com> wrote in message news:<1114014790.606879.149020@f14g2000cwb.googlegroups.com>... > DQ and DQS should have different clock-to-output timing. DQS rising > edge should be in the middle of DQ output window. So receiver can use > DQS rising edge to clock in data contained in DQ valid window. > > What DDR is different from normal SDRAM is DDR is source synchronous > driving device. DQS is used to clock in data sent by data sender. > > Weng I am NOT talking of DQ with regard to DQS. I am talking about the bits of the bus DQ and the bits of the bus DQS ! They have different tCO. I already know DDR basics ;o)Article: 82986
try the xilinx web-site, they have lots of information on CAMs, they also used to have reference designsArticle: 82987
Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you hardware architecture. I would be interested when do you decide for VHDL and when for Verilog. Are the special cases when it makes more sense to use one or the other language? Thanks for helpful tips ClemensArticle: 82988
Xpower will give a breakdown for logic, clocks and IO power
just run (place and route) the design with IO and ignore the power for
IO, eventually for CLOCKS
Aurash
parity wrote:
>Hi!
>
>I want to make a XPower Estimation of a Design which has no connection
>to the pins/pads of the FPGA. I tried to do this using a stimuli file,
>vcd-file and testbench but the Values I get are far of from reality.
>
>Does anybody know whether there is a way to do an estimation like this
>one?
>
>Thanks for help.
>
>parity
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 82989Another reason, of course, to use a soft processor.. is one like mine... I needed a processor.. nothing complex... But I have an FPGA only 1.2 full.. So I've got a picoblaze .. with a dual port RAM to handle inter processor communication, a simple interpreter to handle initialization, and an interrupt controller to handle unscheduled, but necessary events.. and a real cool SPI interface which automatically reconfigures itself depending on what external device is chip selected. And it was free.. because the FPGA has to be there, so I saved myself a few bucks and impressed my boss :-). Simon "austin" <austin@xilinx.com> wrote in message news:d46vol$kbs1@cliff.xsj.xilinx.com... > Teen, > > Quite frankly, you have not even scratched the surface of the issue you > are asking about. There is probably ten years of research, results, > products, etc. that you need to demonstrate a minimum of understanding of. > > There is another twenty years of hardware uP knowledge that you seem to > be totally unaware of. > > The question itself speaks volumes. > > Open your mouth, and you remove all doubt of your competence. > > So, now that we know you know practically nothing, we can reply with > something that will help you. > > FPGAs have long been known to take thirty transistors to do the job of a > single transistor in an ASIC. The same is true for a microprocessor. > It takes many more tranistors to the the job in an FPGA, than it does in > a uP. > > Why would anyone in their right mind then use a FPGA? > > Because it can be anything, for anyone (it is programmable). > > An ASIC requires a great up front investment, and if anything is wrong, > you pretty much throw most of it away, and start over. An ASIC also > requires a task that is not going to change -- ever. Fine for a uP that > has a language that no one will change (too many lines of code already > written for it), but a system is always changing. > > NTT saved billions of dollars by using Xilinx FPGAs in their cellular > base stations: they didn't have to remove all the equipoment from the > field every time there was a change, they merely reprogrammed all the > base stations. > > No genius required to see this advantage. > > So why use a soft uP at all? > > A uP is standard, so you don't need to change it, it uses software to > program it (hence the flexibility is maintained), and it is going to be > much faster, much smaller, and much lower power if the uP is hardened > (made into a non-changing mask). > > Answer is, that unless you want to make a uP with a custom instruction > set (that now limits us to probably less that .001% of all applications > - and for them we offer the APU interface), there is no good reason. > > Hence why we offer the IBM 405 PPC in Virtex II Pro, and Virtex 4. > > But, what if I can replace a ton of gates and flip flops by a simple > program (less than 1K words of instruction)? Hey, maybe there is a > benefit to using a soft uP: I can actually use less > area/power/gates/transistors in the FPGA with a soft uP, than I would > use if I used FPGA logic to do the same job. > > Hence the fabulous sucess of the simple microcontroller core IP that we > offer for both the 405 PPC, and MicroBlaze. > > Austin > > > > teen wrote: > > > Hello Antti, > > > > Thank you for your reply. I had disclosed my identity in > > the mail(regards, Kishore) . Please read the mail again. > > > > Also I competely disagree with your assumption that I haven't done any > > homework. After I had gone through a couple of pages collected through > > I had some ambiguity in the differences between the two CPU's , So I > > had asked the above question only to refine my web searching. > > > > Pease be straight forward while giving any suggestions. > > > > Regards, > > Kishore > >Article: 82990
Not really related to the original question but intresting nonetheless: austin wrote: > FPGAs have long been known to take thirty transistors to do the job of a > single transistor in an ASIC. The same is true for a microprocessor. It > takes many more tranistors to the the job in an FPGA, than it does in a uP. That is not entirely true. Similar to FPGAs uP are extremly inefficient because they are universal. If I want to add two numbers in a uP, something that basically takes a few dozen gates, thousands of of gates start working. Lot's of stuff that is there to preform the ISA abstraction like instruction reordering, scoreboards and reservation stations. Security measures like MMU, and stuff to hide memory access time like caches and translation lookaside buffers. At the same time many, many more gates are sitting around idle like unused cache parts and unused execution units. In a high and processor it takes half a billion transistors to execute something like six operations per clock cycle. But it is universal an can run any algorithm any time. On the other extreme you have an asic implementation of the algorithm that only does work that is required for the task but can do nothing else. This of course is a lot more efficient. (By a factor of 100.000 or so for many algorithms) The FPGA is a compromise between the two. It can use asic like algorithms getting away without all the CPU overhead stuff but you have to pay the factor of thirty for the implementation because you can change the algorithm universaly. As a result it takes a lot - and I mean a lot - less transistors per operation e.g. to perform a smith-waterman computation in an FPGA than in a uP. Kolja SulimmaArticle: 82991
Hi all... i have been trying to simulate some code in which there is a data bus that is declared to be of INOUT type. I have simulated my VHDL code and for both read and write operations it works fine, also the data bus gets tri-stated (Z) when not in use. Now this simulation was done by directly putting the values of signals in the ModelSim environment. Then I thought to write a testbench to simulate the same. In this case when I write some data on the databus it does not get tri-stated when not in use. So i tried to debug the problem and found that since in my testbench I am forcing some value on the bus say '3B' and also in code i force 'Z' when not in use, then STD_LOGIC being a resolved type resolves the value and gives '3B' since 'Z' has got least priority. Why it worked directly on ModelSim environment was bcoz i was "Depositing" the value on bus and not "Freezing" it. If i freeze the value there then in that case also i cud not make the bus tri-stated. So i would like to know how in our testbench we can write code such that i can see all the correct results. I think in practice this will work fine but it's better if in simulation also we can see the desired results. Hope somebody can help. Thanx a lotArticle: 82992
Thanks for the informative reply, Ron With the new information it seems that if my main goal is to transfer data into a pc (putting the TS aside for a moment) then in this perspective The LVDS is a rather exotic option which requires special handling compared to USB2.0 and TCP/IP. Can I get your opinion about this conclusion? Thanks in advance, Marc.Article: 82993
Hi clemens.... just go through the link below.... http://www.bawankule.com/verilogcenter/verilogvhdl.html Hope it helps... byeArticle: 82994
VHDL derives from Ada, Verilog from C. Consequently, VHDL is strongly typed. Some people like this (easier to catch errors), some don't (excessive complexity). It's largely a religious war. Somehow, Verilog has come to be more popular in the US, VHDL everywhere else. "Clemens Hagen" <ernte23@gmx.at> wrote: :Hello : :I have a very basic question. Normally you have the choice if you want to :use VHDL or Verilog for :describing you hardware architecture. I would be interested when do you :decide for VHDL and when for :Verilog. Are the special cases when it makes more sense to use one or the :other language? : :Thanks for helpful tips : :Clemens :Article: 82995
What about contacting a local Lattice FAE? Luc On 20 Apr 2005 07:39:34 -0700, ALuPin@web.de (ALuPin) wrote: >Hi, > >I am trying to use the "DDR_MEM" Lattice template which is responsable >for the datapath for DDR SDRAM controller. > >"DDR_MEM" can be found in the MODULE/IP MANAGER under >ARCHITECTURE_MODULES >--> IO --> DDR_MEM > >When instantiating that module and compiling my design I can see in >the timing analysis >that the bits on the bidirectional busses DQ and DQS have >different Clock-To-Output times. > >In my opinion the busses should be routed into IO register cells >when instantiating that special template. > >So there are three possibilities: > >1. They are not routed into IO register cells so that the PERFORMANCE > ANALYST does show different tCO >2. They ARE routed into IO register cells, but the PERFORMANCE ANALYST > does not take them into timing calculation >3. I have to make any assignment so that the busses are routed into > IO registers. But I have not found any assignment possibility in > the PREFERENCE EDITOR. > >Has someone experienced similar or same problems ? > >Thank you in advance. > >Rgds >AndréArticle: 82996
Hi Buddies,
I am running montavista linux on ml310 and its fine.But
each time I make new build (kernel Image), I see System.map file being
generated at the top level directory is an empty file .
I need this System.map file with address of all kernel
symbols for kernel profiling. hope some of you are doing similar work,
if you have any solutions for me please do convey me.
thanks a lot
regards
Jaggu
Article: 82997Question as subject. Can't find anywhere that explicitly says one way or the other so was wondering if anyone here knows? Thanks for your time, DaveArticle: 82998
I have an application that will probably use a XC3S200 part (probably only half filled). I need moderate DSP capability, so the hardware multipliers are nice, and I need about 50 Kbits block ram and about 2000 logic cells. Clock rates are in the 50-100 Mhz range. We are considering alternatives that we can use at minimum to beat up the Xilinx salesman, or if the price is better, we will use that instead of the Spartan3 part. The Cyclone-2 family looks really attractive in this regard, but the Arrow web site seems to not know that the EP2C5 or EP2C8 exist, although larger Cyclone-2 parts are listed. Can anyone shed light on if/when the smaller Cyclone-2 parts are available? Also, I was a little surprised that the Lattice EPC6 parts seem to be stocked in distribution and seem to be competitively prices ($14 in 100s), so I will probably consider this part also. I assumed only brand X and A have low cost DSP friendly FPGAs. Are there any other parts I should be considering? I couldn't get much pricing online for the Actel proasic family - I think it doesn't have hardware multipliers, but I could build those out of FPGA fabric if there were enough logic cells. -JeffArticle: 82999
Hi there, I created a CPLD design which works perfect in simulation, but does not work in hardware. There are many warnings from the Xilinx ISE looking like WARNING:Xst:1291 - FF/Latch <Sig> is unconnected in block <Blck>. or WARNING:Xst:1710 - FF/Latch <Sig> (without init value) is constant in block <Blck>. These come up only in the Low Level Synthesis processing step. There is one relevant solution record on the Xilinx website (see http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18396) with the following suggestion: >> When this warning occurs, a register or latch in your design has been created, but the output is never connected or the signals or logic it drives have been trimmed. Check the XST log for messages such as the following to find signals that have been trimmed out of the design: "WARNING:Xst:646 - Signal <my_sig> is assigned but never used." << However, there are no such warnings in my XST log. Any help would be appreciated. Christian
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Compare FPGA features and resources
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