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... Specially when you are talking about *re*-configurable devices :) I was going to suggest quantum encryption but even that is being tampered these days. Yep, I guess it is better to stay on the side of the good guys and attack the bad guys with the weight of the law. Since the bitstream is usually copied verbatim, sneaking a watermark in the IP may be a good way to hold your case in court. Regards. -- PabloBleyerKocik /"I believed that people would become programmers pbleyer / and not need companies as much. You can see how @embedded.cl / laughable that was." -- Steve WozniakArticle: 77676
Bret Wade wrote: > Grégory Mermoud wrote: > >> Hi all! >> >> I wonder if it is possible to run a FPGA editor script without >> graphical interface. Does it exist an option to run FPGA editor >> without its GUI ? >> >> Grégory > > > Check out the "fpga_edline" command. It accepts script files with the > "-p <scr_file>" switch. > > Example command to lock all macros in a design: > fpga_edline -p test.scr test.ncd > > Where test.scr is: > select macro * > setattr Locate LOCK:HARD:0:: > save > exit > > Commands available are documented here: > http://toolbox.xilinx.com/docsan/xilinx6/help/fpga_editor/fpga_editor.htm > > Does anyone remember hm2nmc? > > Cheers, > Bret > That's nice thank you.Article: 77677
On Thu, 13 Jan 2005 09:31:09 GMT, Ben Twijnstra <btwijnstra@gmail.com> wrote: >I suggest you read the following article: > >http://www.altera.com/literature/wp/wp_m2dsgn.pdf > >This uses a MAX II as a 'dongle'. The MAX II is - let's say - non-volatile >and generates a continuous stream of bits. The same algorithm runs in the >FPGA, and if there's a mismatch, the FPGA quits working. > >I also have an unofficial whitepaper plus reference design that uses a MAX3 >device to do something similar, albeit with a less cryptologically sound >algorithm. Contact me on bentw at chello dot nl if you want it. The gmail >address is a spam trap. > >Best regards, > > >Ben Thank you very much Ben, this white paper is very interesting. It will provide a fairly good level of reliability for our design. I shall contact you in a few days. Thank you again, you relieve me of a great pressure. NickArticle: 77678
>This discussion is not new, there is a article/website dicussing this very >problem (Sorry, dont have the link handy) . And the external PROM/uC/CPLD >ist not as secure as you might think. Sure it's not safe at all, but it increase by a small margin the cost of cloning. Anyway, Ben's white paper sounds very promising and i'll use a similar device. Regards NickArticle: 77679
Grégory Mermoud wrote: > Bret Wade wrote: > >> Grégory Mermoud wrote: >> >>> Hi all! >>> >>> I wonder if it is possible to run a FPGA editor script without >>> graphical interface. Does it exist an option to run FPGA editor >>> without its GUI ? >>> >>> Grégory >> >> >> >> Check out the "fpga_edline" command. It accepts script files with the >> "-p <scr_file>" switch. >> >> Example command to lock all macros in a design: >> fpga_edline -p test.scr test.ncd >> >> Where test.scr is: >> select macro * >> setattr Locate LOCK:HARD:0:: >> save >> exit >> >> Commands available are documented here: >> http://toolbox.xilinx.com/docsan/xilinx6/help/fpga_editor/fpga_editor.htm >> >> Does anyone remember hm2nmc? >> >> Cheers, >> Bret >> > That's nice thank you. You're welcome. I should also mention that it's possible to get examples of the command line syntax by monitoring the file design_fpga_editor.out (where design is your NCD design name) while performing the equivalent operations manually in FPGA Editor. There is some buffering going on, so you may have to perform extra operations before the editor dumps the commands you're interested in. You can also get the syntax by recording a script from the tool-->scripts menu. BretArticle: 77680
"Peter Alfke" <peter@xilinx.com> wrote in message news:1105645416.101820.302790@c13g2000cwb.googlegroups.com... > That last-mentioned idea is the equivalent of the classical > "one-time-pad", which is inherently unbreakable, but also not very > practical. Oh absolutely. I just used it as an example. OTOH, it is simple and each bit is decrypted at the place it is used. If you have decryption done in a specific region, sooner or later someone will find the cleartext exit point and intercept it as it emerges. Smartcard hardware and software does try to take defensive measures but none would claim to be uncrackable. One can only make it too difficult/expensive to be worth doing.Article: 77681
Eric Smith (eric-no-spam-for-me@brouhaha.com) wrote: : glen herrmannsfeldt <gah@ugcs.caltech.edu> writes: : > Wasn't there a story about some TLA (three letter agency) : > putting taps on fiber optic cables on the bottom of the ocean? : > (Without either end noticing.) : They almost certainly have the capability to do so, but if they've done : it we wouldn't know, would we? : The nuclear-powered attack submarine USS Jimmy Carter (SSN-23) is : specially equipped to allow undersea cables to be pulled into a payload : bay and worked on. Indeed. Quite a feat in itself, but then remember that before the advent of optically pumbed fibre amplifiers the fibre optic cores were encased in a high volage power supply for the amplifiers / regenerators! All change again soon, for short distances at least quantum entanglement based encryption (for key exchanges) is now a fibre based reality... - the USP of this tech. is that by the (current) laws of Physics we *would* know if the data traveling through the fibre is tapped. So they'll just have to tap it somewhere else... --- cdsArticle: 77682
Christopher, There's an article all about Quantum Cryptography in this month's SciAm. Google "Best-Kept Secrets" sciam These people can do it over 120km! http://www.magiqtech.com/press/qpn.pdf Cheers, Syms. "c d saunter" <christopher.saunter@durham.ac.uk> wrote in message news:cs75m8$g8$1@heffalump.dur.ac.uk... > > > All change again soon, for short distances at least quantum entanglement > based encryption (for key exchanges) is now a fibre based reality... - the > USP of this tech. is that by the (current) laws of Physics we *would* know > if the data traveling through the fibre is tapped. So they'll just have to > tap it somewhere else... > > --- > > cdsArticle: 77683
Symon, Crikey! I hadn't realised it was that commercial yet. This stuff must be the ultimate nightmare of some groups. I guess legislation will catch up soon enough. Weird seing the computer jagon crud mixed with quantum physics, much more of this to come... 9 times out of 10 it will probably still be breakable as managers will go for it without learning the science, and you'll end up with the same key being reused (QC is only tuely secure if all keys are varified as unsnooped, are used *once* and only once and are never stored in anything but very volatile memory :-) and the terminals at either end running some unpatched OS, being on some unsecured network and having a keyboard or video logger installed :-) I wonder which generation of X & A parts will have QC capable electro-optics (or just opto-optics) on the die? Cheers, Chris Symon (symon_brewer@hotmail.com) wrote: : Christopher, : There's an article all about Quantum Cryptography in this month's SciAm. : Google "Best-Kept Secrets" sciam : These people can do it over 120km! http://www.magiqtech.com/press/qpn.pdf : Cheers, Syms. : "c d saunter" <christopher.saunter@durham.ac.uk> wrote in message : news:cs75m8$g8$1@heffalump.dur.ac.uk... : > : > : > All change again soon, for short distances at least quantum entanglement : > based encryption (for key exchanges) is now a fibre based reality... - the : > USP of this tech. is that by the (current) laws of Physics we *would* know : > if the data traveling through the fibre is tapped. So they'll just have : to : > tap it somewhere else... : > : > --- : > : > cdsArticle: 77684
First Call for Papers
2005 MAPLD International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 7-9, 2005
The 8th annual MAPLD International Conference will present papers on
programmable logic devices and technologies, digital engineering, and
related fields, for military and aerospace applications. Devices,
technologies, logic design, flight applications, fault tolerance,
usage, reliability, radiation susceptibility, and encryption
applications of programmable devices, processors, and adaptive
computing systems in military and aerospace systems are topics for
papers. For 2005, MAPLD will be expanded to 3 full days and will
feature expanded "Birds of a Feather" Workshop Sessions. Full-day
seminars will be offered on September 6, 2005.
We are planning an exciting program with presentations by Government,
industry, academia, and consultants, including talks by distinguished
Invited Speakers. This conference is open to US and foreign
participation and is unclassified. For related information, please
see the NASA Office of Logic Design Web Site (http://klabs.org).
Abstract submittal info: http://klabs.org/mapld05/admin/cfp.html
Abstract deadline: April 25, 2005
Special Talks Include:
* Welcome and Opening Address
* Invited History Talk
* Invited Mishap Talk (new for 2005)
* The Application Engineers' View
* Panel Session: "Why Are Space Stations So Hard?"
Four Seminars Are Being Planned:
* Signal Integrity, Power Integrity, and Interfacing
* Real-Time, Hi-Rel Software Issues for Computer Designers
* Device Failure Modes and Reliability
* Reconfigurable High-Performance Computing
Planned Technical Sessions
* Applications: Military & Aerospace
* Verification of High Reliability Designs
* Radiation Effects and Mitigation Techniques
* Logic Design and Processors
* Reconfigurable Computing, Evolvable Hardware, and Security
* Poster Session
* BOF-L: Mitigation Methods for Reprogrammable Logic in the Space
Radiation Environment
* BOF-F: Reconfigurable Computing
* BOF-J: PLD Failures, Analyses, and the Impact on Systems
* BOF-S: NESC and Software
* BOF-G: Digital Engineering and Computer Design - A Retrospective
and Lessons Learned for Today's Engineers
Reservations are being accepts for the Industrial & Gov't Exhibits:
http://klabs.org/mapld05/exhibits/reservation_request_form.htm
For additional information:
Conference home page: http://klabs.org/mapld05
Richard B. Katz
NASA Office of Logic Design
mapld2005@klabs.org
Article: 77685What is possible use of FPGA Editor in batch mode !? .. i fail to understand. -- VarunArticle: 77686
This is good advice. If you have no timing constraints, Quartus will perform only minimal timing optimization on a design during place and route if you have "Auto Fit" (the default) selected. So you should definitely enter your required clock frequencies into Quartus, using the method Ben describes. At that point Quartus will flag timing violations (check the timing analyzer section in the compilation report) and will work to optimize the design to meet your constraints, so violations are less likely. Vaughn Altera [v b e t z (at) altera.com] "Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:ooXEd.314728$lN.313548@amsnews05.chello.com... > Hi vlsi_learner, > > > hi Ben > > > > i have compared the timing reports for both the cases ie with Stratix > > EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same > > except that the critical path delay is different > > > > for EP1S10F780C6 : critical path delay is 10.647 ns > > total cell delay is 4.956 ns > > total interconnect delay is 5.691 ns > > > > for EP1S10F780C5 : critical path delay is 9.468 ns > > total cell delay is 4.420 ns > > total interconnect delay is 5.048 ns > > > > wat should i do??? the results are correct for EP1S10F780C5..how should > > i reduce the critical path delay for stratix EP1S10F780C6 > > If your clock frequency is 100MHz, your clock period in 10ns. Ergo, the C6 > is too slow, and the C5 meets timing. > > From what I gather from your story, you don't seem to have put any > information regarding clock frequency into your Quartus project. This means > that Quartus will compile the circuit, do a few P&R iterations, and then > finishes, telling what it thought up as a possible solution. > > Once Quartus knows about your minimum clock frequency and, probably, the Tsu > and Tco constraints (I usually set them to about 2/3 of the clock period if > there are no special demands) it will try to meet these constraints and > will telly if it hasn't been able to find a P&R solution that met your > requirements. > > If you have indeed not entered any clock frequency constraints in your > project, you can do so by clicking "Assignments" on the menu bar and > selecting "Timing Wizard". Just follow the instructions. > > Another solution I have seen, but definitely not one for production > environments, is to apply a healthy dose of cold spray to the FPGA if the > circuit doesn't violate timing constraints too badly. The lower temperature > will make circuit timing faster. > > As stated, good for experimenting and testing your algorithm, but not for an > end product, unless of course you want to ship your crypto processor with a > lifetime supply of cold spray ;-) > > Best regards, > > > Ben >Article: 77687
Vladimir, I seem to recall a colleague of mine mentioning something about a similar issue. I can check with him and get back to you, unless you already have a solution... Cheers, - imaslackerArticle: 77688
Varun Jindal wrote: > What is possible use of FPGA Editor in batch mode !? .. i fail to > understand. > > -- Varun > Most things that can be done in FPGA Editor can be automated with a script. If you have a repetitive task such as changing the configuration of many IOBs in the same way, then you can do it manually for one IOB, capture the necessary commands involved, and then write a script to do the rest. I once wrote an interactive perl script to add probes to a design before the editor itself supported that feature. NeoCAD used this feature ages ago to convert Xilinx hard macros (.hm) to NeoCAD hard macros (.nmc) using EPIC, the predecessor to FPGA Editor. BretArticle: 77689
Hi Varun, the most prominent thing that comes to my mind is e.g. adding probes to a freshly inplemented (big) design. Saves you waiting for FPGA Editor to load and process the design-graphics. Cheers, Martin Varun Jindal wrote: > What is possible use of FPGA Editor in batch mode !? .. i fail to > understand. > > -- Varun >Article: 77690
On Fri, 14 Jan 2005 01:39:07 +0000, c d saunter wrote: > Symon, > Crikey! I hadn't realised it was that commercial yet. > This stuff must be the ultimate nightmare of some groups. I > guess legislation will catch up soon enough. > They'll just fall back to the standard BBB methods of intelligence gathering - burglary, bribery and blackmail. Mass-monitoring of communications has such an incredibly low signal-to-noise ratio that any useful information is drowned out by the rest of the world going about their business.Article: 77691
The message you see is a normal info-message, telling you that there might be paths that are not covered by timing analysis. From the message you posted it is not possible to tell if there are any or how many unconstrained paths there are. Did you set global timing constraints on the main clk(s)? If yes, check if there are any unconstrained paths that are critical in your design. Anyway, this message has nothing to do with a problem between mhs and mss. Regards DanielArticle: 77692
hi Everyone; What is the difference between Hard and soft Macro in Leonardo Spectrum Sysnthesis Process? Thank youArticle: 77693
Hello people, when having a look at the specification of FPGA integrated FIFOs (Altera Cyclone devices, Lattice ECP devices) which are built up of integrated RAM and some logic there is nothing said about how to reset a FIFO suddenly while working. Let us assume the FIFO has a wrclk (=50MHz) and a rdclk (=120MHz). What does happen if a synchronous reset signal is generated for one 120MHz clock cycle and is applied to the asynchronous fifo reset input ? Does the fifo reset correctly on both fifo buffers? What about the read and write flags during this synchronous reset ? Do they have to be inactive ? Or could it be a better strategy to make the reset signal longer than just one clock cycle ? To which clock should this reset signal be synchronous ? When starting up the FPGA the RESET applied to the FIFOs is long enough so that there is no problem but I would like to clarify the situation of an intermediate RESET. Thanks for your suggestions. Kind regards AndréArticle: 77694
Hi, I am just starting to use the ARMoid board (AT91 ARM based controller + spartan II http://armoid.com/store/catalog/product_info.php?products_id=28&osCsid=4f58554bddd3dd7b0e86fd94df0b2808). I have read their documentation but I can't find any information about how to configure the FPGA with the controller. It is said that the FPGA is configured by the AT91, but I can not find any info about how to configure the tools to join and download fpga binaries. I use an eclipse platform, and Ecos as OS. I have already used an Altera Excalibur SoC (ARM + fpga) and I had to set the GNUarm tool for it. Is it necessary to configure it separately? Can anyone tell me how to configure it? Thanks,Article: 77695
ALuPin wrote: > Hello people, > > when having a look at the specification of FPGA integrated FIFOs (Altera Cyclone > devices, Lattice ECP devices) > which are built up of integrated RAM and some logic > there is nothing said about how to reset a FIFO suddenly while working. > > Let us assume the FIFO has a wrclk (=50MHz) and a rdclk (=120MHz). > > What does happen if a synchronous reset signal is generated for one > 120MHz clock cycle and is applied to the asynchronous fifo reset input ? > Does the fifo reset correctly on both fifo buffers? > What about the read and write flags during this synchronous reset ? > Do they have to be inactive ? > > > Or could it be a better strategy to make the reset signal longer than just one > clock cycle ? > To which clock should this reset signal be synchronous ? > > When starting up the FPGA the RESET applied to the FIFOs is long enough > so that there is no problem but I would like to clarify the situation of > an intermediate RESET. > > Thanks for your suggestions. > > Kind regards > André Resetting a FIFO is tough because of the two clock domains. I made a robust circuit to do this once; it was a pair of concurrent state machines in different clock domains. An easier and fairly robust way would be to use the "aysynchronous reset, synchronous clear" circuit in both domains. This consists of two flops in each domain. When you want to reset, set both flops using the asynchronous preset. Then the first flop clears itself synchronously, because the D input is tied to zero. The second flop is connected to the first, so it clears on the next cycle synchronously. The output of that is connected to the async reset of the read or write side of the FIFO. I know this textual description may not be clear, but by using a pair of these you can reset both sides of the FIFO at the same time, but make sure that the reset is deasserted synchronously to the clocks on either side to avoid setup violations. -KevinArticle: 77696
Good morning, I'm a beginner with FPGA. I've found an 8051 IP core here : http://oregano.at/ip/ip01.htm , and want to put it in a Spartan 3 FPGA like XC3S50 or XC3S200 (they have impressive number of LUT, and I suppose it's possible). Now, how I can do this ??? I've installed the free version of Xilinx ISE, I suppose this can compile the .vhd files of the IP, it's right?Article: 77697
> Consider declaring each vector part separately. Thanks Mike, Hmm. I can do that. What though is happening when I do a clockless scheduled event, mem_input( 7 downto 0 ) <= blob_label; mem_input(15 downto 0) <= blob_volume; and so on, and with the mem_output going the other way? It would seem that I'm not creating any hardware, just new names for the same signals.Article: 77698
ALuPin wrote: > Hello people, > > when having a look at the specification of FPGA integrated FIFOs (Altera Cyclone > devices, Lattice ECP devices) > which are built up of integrated RAM and some logic > there is nothing said about how to reset a FIFO suddenly while working. > > Let us assume the FIFO has a wrclk (=3D50MHz) and a rdclk (=3D120MHz). > > What does happen if a synchronous reset signal is generated for one > 120MHz clock cycle and is applied to the asynchronous fifo reset input ? > Does the fifo reset correctly on both fifo buffers? > What about the read and write flags during this synchronous reset ? > Do they have to be inactive ? > I haven't seen the built-in FIFO's yet, but in the Xilinx CoreGen FIFO's the reset is always asynchronous for the dual-clocked FIFO's. The required pulse width of the reset input is very short and depends only on the reset timing parameter of the CLB flip-flops. > > Or could it be a better strategy to make the reset signal longer than just one > clock cycle ? > To which clock should this reset signal be synchronous ? > Generally resetting the FIFO does nothing to the memory array, but just asynchronously resets the pointers and flag logic. Generally making the reset synchronous to the write side is safer, assuming the logic prevents read pointers from changing when the FIFO is empty. In the case of CoreGen FIFO's, the EMPTY and FULL flags are both asserted during reset, which prevents writes or reads from affecting the pointers until each flag has been clocked into its proper state. This is a little like the reset flip-flop approach Kevin mentioned. > When starting up the FPGA the RESET applied to the FIFOs is long enough > so that there is no problem but I would like to clarify the situation of > an intermediate RESET. >=20 > Thanks for your suggestions. >=20 > Kind regards > Andr=E9Article: 77699
"Enzo B." <enzo_br@virgilio.it> schrieb im Newsbeitrag news:ZQTFd.406761$b5.19667001@news3.tin.it... > Good morning, > > I'm a beginner with FPGA. > I've found an 8051 IP core here : http://oregano.at/ip/ip01.htm , and want > to put it in a Spartan 3 FPGA like XC3S50 or XC3S200 (they have impressive > number of LUT, and I suppose it's possible). > Now, how I can do this ??? Just do it. Setup a new project, add the files, compile. But if you want a powerfull uC in a Xilinx FPGA, you better go for the famous KCPSM (xapp213). Its a very nice thing, much faster than any 8051 clone and MUCH smaller!!! Regards Falk
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