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Hi Does microblaze do all the LMB transfers synchronously (ie, it doesnt support variable latency). If so, why is there a ready signal. If not, how can the second transfer be performed back to back without looking at the ready signal (as shown in the reference guide)? Is there another bus which supports variable latency (OPB?? where is its timing diagram documented? ) Thanks MuraliArticle: 113151
Ashish wrote: > Hi Peter, > > I have a clock which will change in runtime(25 Mhz to 50 MHz to 100 > MHz) and expect DCM to take time in locking the clock. > > I just wanted a straight 180 deg ph shift and dont wish to have any > wait period for DCM to lock the o/p. > > Please correct me if my understanding is wrong. > > Thank You > > Ashish Since you have delays of 5, 10, and 20 ns to get 180 degree phase shifts, don't try anything funny. The inverted clock is better than any non-DCM solution in accuracy and better than the DCM solution in "lock time" since there is no delay.Article: 113152
By that reasoning, you should never buy any nationally-advertised brand. Companies do not waste money on ads, they figure that it increases revenue enough, so it really does more than pays for itself. Otherwise they would not spend the money. FPGAs have a very high development cost, but a healthy profit margin in volume production. That's why everybody tries so hard to increase revenue and market share. And that's why the smallest manufacturers have such a hard time, and are dropping out... No mystery, just Economics 101 Peter Alfke On Dec 5, 11:59 pm, lb....@telenet.be wrote: > Peter, > > You can always try to look at it from the other side: > Altera might be spending their money by taking the prices from their > devices down. As for Xilinx and Actel, well, they will probably be > more expensive? > And you didn't mention Lattice nor Quicklogic. They must be the > cheapest as they don't advertise... :o)) > > Luc > > On 5 Dec 2006 14:05:00 -0800, "Peter Alfke" <p...@xilinx.com> wrote: > > >Antti, regarding Electronica (the biggest electronic component show in > >the world): > > >the Actel booth was indeed surprisingly large and flat, and fairly > >empty. > >The Xilinx booth was more vertical and more crowded, also more crowded > >with customers and with serious conferences with customers. So we are > >quite happy (I was there). > >I am however amazed that Actel finds the money for such a large number > >of square meters... > >Altera, by the way, was hiding in a tiny cubicle next to some > >automotive guys, in a different hall. > >Everybody has different ideas about spending effort and money at > >shows... > >Peter Alfke, Xilinx > > >On Dec 5, 11:31 am, "Antti Lukats" <a...@openchip.org> wrote: > >> "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.kn...@xilinx.com> > >> schrieb im Newsbeitragnews:1165346298.454531.194840@16g2000cwy.googlegroups.com... > > >> > Antti wrote: > >> >> Antti schrieb: > > >> >> > as Xilinx PR ES samples are available, and tools support for S3A also, > > >> >> as usual - the documentation is not complete :( > > >> > [... snip ...] > > >> >> Antti > > >> > Hi Antti, > > >> > There was about a 2-3 hour span last night when the Spartan-3A > >> > technical documentation wasn't yet available on the Xilinx web site. > >> > The nearly 1,000 pages of documentation all went live about 11 PM > >> > Pacific time on 4-DEC-2006.[..] > >> no problems, I actually found all i was looking for, but I had already > >> posted before > > >> > You may also be interested in the associated article discussing how to > >> > use the Device DNA. > > >> > How to implement high-security in low-cost FPGAs > >> >http://www.pldesignline.com/howto/showArticle.jhtml?articleID=196601422 > > >> > --------------------------------- > >> > Steven K. Knapp > >> > Applications Manager, Xilinx Inc. > >> > General Products Division > >> > Spartan-3/-3E FPGAs > >> >http://www.xilinx.com/spartan3e > >> > E-mail: steve.kn...@xilinx.com > >> > --------------------------------- > >> > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Steven - you arent working for Altera? > > >> I clicked on the link to plddesignline and got a big flashing Altera > >> Stratix-III AD flyer !! > >> ok, well its beyound your control, but was amusing. > >> similarly as it was amysing to come to Xilinx booth at Electronica2006, all > >> it was to > >> see was a big Actel Logo as their booth was just befor Xilinx and way more > >> visible. > > >> AnttiArticle: 113153
hi all,
i am using spartan 3e fpaga xc3s100e -4 speed grade
i have a problem while i am doing PAR after that post PAR static
timing analysis i am getting -ve slack as my design needs 155mhz clock
internal i am using DCM and i am generating that clock and that
CLK2X_BUF of DCM is volating and as a result i am getting -ve slack
about 1ns i have tried optins like
place and route effort level medium....
palce and route mode -> multipass route...
and other optins that are there in timing closure report............
but still i am getting -ve slack so i tried option of changing speed
grade -5 that time slack is meetig but i have spartan 3e fpga which is
xc3s100e -4 grade ........
so i tried false path option ........ but in my design timing is
critical so i need to meet timing as false path will ignor that path i
am not sure whether i will get actul timing slack (0 or +ve) in
realtime on board...........
so anybody can plz help me in finding the solution for this and i have
a doubt whether spartan 3e xc3s100e will support freq of 155mhz
............
regards
srik
Article: 113154To myself. ##1 is equivalent to @ (posedge clk). So ##N is equvalent to repeat (N) @ (posedge clk) ? Thanks! Davy Davy wrote: > Hi Jonathan, > > Thanks a lot! Now I understand what's "vacuous success" :) > > Best regards, > Davy > > Jonathan Bromley wrote: > > On 10 Nov 2006 18:36:25 -0800, "Davy" <zhushenli@gmail.com> wrote: > > > > >Hi all, > > > > > >I have two problem of SystemVerilog Assertion. About property > > >implication and sequence. > > > > > >1. Is > > >//-------- > > >property rule (a,b,c); > > > @(posedge clk) a |-> b ##1 c; > > >endproperty > > >//-------- > > > > > >equal to > > >//-------- > > >sequence rule; > > > @(posedge clk) (a&&b) ##1 c; > > >endsequence > > >//-------- > > > > No. See the recent thread "implication operators in sva" > > on comp.lang.verilog. Also, you have parameterised the > > property but not the sequence. > > > > >2. I was told implication can be same or next cycle. Is same cycle > > >equal to "|->"? And is next cycle equal to "|=>"? > > > > Yes. See my post in the thread I just mentioned. > > -- > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.bromley@MYCOMPANY.com > > http://www.MYCOMPANY.com > > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated.Article: 113155
<snip> > Do anyone know if this dcm will behave the same way as it would have > using the wrapper for the Virtex II Pro? I have memory problems that I > can't track down so I'm trying to make sure this changes doesn't effect > how the memory and microprocessor are clocked. > I assume you are basically trying to instantiate DCM's with the same clocking structure as used by EDK. I think the code above is missing all the BUFG instantiation that is done inside the dcm_?_wrapper code. You might want to take a look at the VHDL file for dcm_module. /SivaArticle: 113156
> Does microblaze do all the LMB transfers synchronously (ie, it doesnt > support variable latency). If so, why is there a ready signal. If not, > how can the second transfer be performed back to back without looking at > the ready signal (as shown in the reference guide)? > > Is there another bus which supports variable latency (OPB?? where is its > timing diagram documented? ) You have not mentioned what exactly you are trying to do. Depending on what you want, the FSL or the OPB bus might be appropriate. The documentation for both of them should be available along with EDK. /SivaArticle: 113157
The altlvds Megawizard requires me to specify the data alignment to the input clock and the output clock. What are the values you entered? AvishayArticle: 113158
On Dec 7, 8:42 am, Jesper.Kristen...@tellabs.com wrote: > Hello Group. > > Not being that familiar with Altera's Quartus II, and it may be a > beginners problem... > Anyways... > I'm compiling a VHDL-based design for the MAX-II EPM1270F256C5, which > Ifinally managed to get error-free. > When trying to back-annotate the Fitter's suggestion for the pin > placing, the Pin Planner's list section actaully states two entries for > the same physical pin and signal like this: > > mpifdX[7] PIN_J14 > mpifdX[7]~0 PIN_J14 > These are internal signals, which represent the input (or OE, I'm not sure) and the output of the pin. They are automatically created by the synthesizer. In the pin planner, you should assign a pin location only to the name without the tilde. AvishayArticle: 113159
On 2006-12-07, johnp <johnp3+nospam@probo.com> wrote: > If I run PAR from the command line, it runs OK. If I use nmake or > wmake and my makefile, > it crashes. I've opened a WebCase, but I've little hope that they > will resolve anything. I've not run into your problem but I have run into other cases of programs not working correctly when I start them from a makefile in Windows. In my case I wanted to start modelsim from a cygwin based makefile and it complained about licensing or something similar, something it never did when started from the command line. I worked around this by using the "cmd" command to start a new shell that I could run the command in: sim: cmd /c start vsim mydesign Perhaps you might have better luck if you start par in this way? /AndreasArticle: 113160
Hi, After using PlanAhead a while I've got some problems: 1) when using ExploreAhead Trace does not start. I investigated the problem and noticed that this is caused by "-v" option of the Trace. When I run Trace under ISE with this switch it refuses to start as well. The problem is that I cannot ( or I don't know ) how to get rid of teh -v switch under ExploreAhead: it is always there. 2) How could I manually assign the logic to IOB resources (FFs). First of all, it does not show these resources as it does for CLBs. Second, it refuses to place any FF in IOB when working in SITE/BEL Constraint mode. Do you know how could I do it? 3) Floorplan under PlanAhead is not compatible with other Xilinx software. It rearranges the UCF file I created under PACE in the way that when I try to read it back under PACE it reports errors and many location constarints are lost. How to make it working exchangable? Regards WojtekArticle: 113161
Hi > I'm just doing my first steps trying to get a busmaster > example created with xps running. There is some example code > and i just tried to use it for the first test. However it just > refuses to work and the busybit of the busmaster seems to stay > set. Has anybody an idea? Ok, it is not the busy bit but the whole system is locked up. Nothing works anymore after writing to the go register. Has anybody an idea, why? Thanks STArticle: 113162
<ekavirsrikanth@gmail.com> wrote in message
news:1165475113.349703.320970@16g2000cwy.googlegroups.com...
> hi all,
>
> i am using spartan 3e fpaga xc3s100e -4 speed grade
> i have a problem while i am doing PAR after that post PAR static
> timing analysis i am getting -ve slack as my design needs 155mhz clock
> internal i am using DCM and i am generating that clock and that
> CLK2X_BUF of DCM is volating and as a result i am getting -ve slack
> about 1ns i have tried optins like
> place and route effort level medium....
> palce and route mode -> multipass route...
A better option to start with is to
(a) look at the static timing report
(b) analyse and understand what is the slowest path in your circuit
(c) redesign that part of your circuit so it has fewer logic levels
between synchronous elements and thus runs faster
(d) re-run MAP/PAR
(e) If timing is not met, goto (a) and repeat until it is.
Fiddling with PAR options should be the last resort, not the first thing to
try, unless you have very marginal timing. In your case (-1ns slack on
155MHz clock) you are off by 15%, which is far from marginal and indicates
that the problem lies with the design.
-Ben-
Article: 113163I am new to fpga design... and don't know the good practice to handle differential I/O. I am right using OBUFDS and IBUFDS component ? I have errors with ISE8.2 and my differential pairs (rx_pin and tx_pin) : I greatly appreciate any helps... or a link to example for S3E starter kit Unable to combine the following symbols into a single DIFFS component: PAD symbol "rx_pin_n" (Pad Signal = rx_pin_n) SlaveBuffer symbol "i_b/SLAVEBUF.DIFFIN" (Output Signal = i_b/SLAVEBUF.DIFFIN) Each of the following constraints specifies an illegal physical site for a component of type DIFFS: Symbol "rx_pin_n" (LOC=E8) Please correct the constraints accordingly. ucf: NET "rx_pin_p" LOC = "F8" | IOSTANDARD = LVDS_25 ; NET "rx_pin_n" LOC = "E8" | IOSTANDARD = LVDS_25 ; NET "tx_pin_p" LOC = "D7" | IOSTANDARD = LVDS_25 ; NET "tx_pin_n" LOC = "C7" | IOSTANDARD = LVDS_25 ;Article: 113164
Peter Alfke wrote: > Companies do not waste money on ads, they figure that it increases > revenue enough, so it really does more than pays for itself. Otherwise > they would not spend the money. The classic formulation is "Half the money spent on ads is wasted. But nobody knows which half."Article: 113165
Hi all, I want to add an Ethernet interface to my FPGA board for data transmission. But I'm not sure which scheme I should use. A) There's a PHY on the FPGA board, but I don't have much knowledge or experience on MAC. The protocol seems complicated and not easy to implement in a short time. Is it possible to develop a small and simple MAC? My idea is packing data to form a standard TCP or UDP packet and using the PHY to send out or receive it. Another reason I don't want using a full MAC is it costs too much resources (~2000 slices). If I use MicroBlaze+OPB MAC, I can't afford the license fee. B) Using another external Ethernet micro-controller, such as Rabbit microprocessor. I can develop an interface between FPGA and uC for data transmission. But I'm wondering how fast the speed is? C) Using micro-controller + (MAC+PHY Ethernet single chip). Then porting uClinux or lwip to the uC and hanging FPGA to the address/data bus of the uC. Any suggestions? Thank you. JJArticle: 113166
"Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message
news:el7d9h$lgn$1@news.lysator.liu.se...
> On 2006-12-06, Bill Burris <wburris@ualberta.ca> wrote:
>> I want something cheap (under $500), with PCI or PCIe. It needs to
>> include the interface to the PCI/PCIe. A $500 board is useless if it
>> requires spending $2500 for IP to communicate with the PCI/PCIe. It
>> also needs to include device drivers for Windows.
>
> For PCI you have a variety of open source IP cores, most notably the
> PCI bridge on opencores. For PCIe I'm not aware of any free core.
>
> Perhaps Enterpoint's PCI board could be interesting for you? It seems
> to be very cheap and does not include any of the features you say that you
> don't need :) http://www.enterpoint.co.uk/moelbryn/raggedstone1.html
>
>
> Otherwise, if you really need PCIe, one of the cheaper solutions might be
> to buy a PCIe based board with an FPGA that includes a PCIe core in
> hardware. I'm not sure if you can get one of those for less than $500
> though.
>
> As for windows device drivers, I can't say anything since I'm mostly
> a Linux user myself.
>
> /Andreas
HI Bill,
Our Raggedstone1 product would seem to be a good fit for your
requirements being one of the biggest logic intensive boards you can by
cheaply, as a side note we are in the final stages of cutting a PCI core
that will be shipped Free with Raggedstone1 to use with your board you
purchase. We are getting a driver written for windows also to use.
REGARDS IAN
Article: 113167Hi, I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project but i'm having difficulty in finding any information what so ever apart from an explanation as to what it does, can anyone help? Can anyone explain what logic would be required to create a CLZ, i've only found one point of reference on the web which uses a number of nested multiplexers with the output of one being fed back into the select line of the next. Any information regarding the hardware/ schema would be greatly appreciated. Thanks, DaveArticle: 113168
Siva Velusamy wrote: >> Does microblaze do all the LMB transfers synchronously (ie, it doesnt >> support variable latency). If so, why is there a ready signal. If not, >> how can the second transfer be performed back to back without looking at >> the ready signal (as shown in the reference guide)? >> >> Is there another bus which supports variable latency (OPB?? where is its >> timing diagram documented? ) > > You have not mentioned what exactly you are trying to do. Depending on > what you want, the FSL or the OPB bus might be appropriate. The > documentation for both of them should be available along with EDK. > > /Siva > I am trying to connect a variable latency memory to microblaze. I would like to use the LMB bus since the interface looks simple. But from the timing diagrams in the reference guide, it looks like the ready signal is not used in microblaze. I just want to clarify that - whether the microblaze LMB interface is a synchronous (read non variable-latency) interface, which doesnt look at the ready signal in the bus. Thanks MuraliArticle: 113169
Hi Steve, on Opencore there is a free MAC in hdl. so you can try to use it. The Ethernet protocol is not difficoult, you can found some usefull informations on www.trendcomms.com Francesco Steve wrote: > Hi all, > > I want to add an Ethernet interface to my FPGA board for data transmission. > But I'm not sure which scheme I should use. > > A) There's a PHY on the FPGA board, but I don't have much knowledge or > experience on MAC. The protocol seems complicated and not easy to implement > in a short time. Is it possible to develop a small and simple MAC? My idea > is packing data to form a standard TCP or UDP packet and using the PHY to > send out or receive it. Another reason I don't want using a full MAC is it > costs too much resources (~2000 slices). If I use MicroBlaze+OPB MAC, I > can't afford the license fee. > > B) Using another external Ethernet micro-controller, such as Rabbit > microprocessor. I can develop an interface between FPGA and uC for data > transmission. But I'm wondering how fast the speed is? > > C) Using micro-controller + (MAC+PHY Ethernet single chip). Then porting > uClinux or lwip to the uC and hanging FPGA to the address/data bus of the > uC. > > Any suggestions? Thank you. > > JJArticle: 113170
Steve <eejju@polyu.edu.hk> wrote: > Hi all, > I want to add an Ethernet interface to my FPGA board for data transmission. > But I'm not sure which scheme I should use. > A) There's a PHY on the FPGA board, but I don't have much knowledge or > experience on MAC. The protocol seems complicated and not easy to implement > in a short time. Is it possible to develop a small and simple MAC? My idea > is packing data to form a standard TCP or UDP packet and using the PHY to > send out or receive it. Another reason I don't want using a full MAC is it > costs too much resources (~2000 slices). If I use MicroBlaze+OPB MAC, I > can't afford the license fee. > B) Using another external Ethernet micro-controller, such as Rabbit > microprocessor. I can develop an interface between FPGA and uC for data > transmission. But I'm wondering how fast the speed is? > C) Using micro-controller + (MAC+PHY Ethernet single chip). Then porting > uClinux or lwip to the uC and hanging FPGA to the address/data bus of the > uC. Look at leon (www.gaisler.com) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 113171
davidc@ad-holdings.co.uk wrote: > Hi, > > I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project > but i'm having difficulty in finding any information what so ever apart > from an explanation as to what it does, can anyone help? > > Can anyone explain what logic would be required to create a CLZ, i've > only found one point of reference on the web which uses a number of > nested multiplexers with the output of one being fed back into the > select line of the next. Any information regarding the hardware/ schema > would be greatly appreciated. > In rough Verilog: casez(number) 4'1????: res = 0; 4'b01??: res = 1; 4'b001?: res = 2; 4'b0001: res = 3; 4'b0000: res = 4; endcase Cheers, JonArticle: 113172
> I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project > but i'm having difficulty in finding any information what so ever apart > from an explanation as to what it does, can anyone help? > > Can anyone explain what logic would be required to create a CLZ, i've > only found one point of reference on the web which uses a number of > nested multiplexers with the output of one being fed back into the > select line of the next. Any information regarding the hardware/ schema > would be greatly appreciated. I'd say there is two case : - If you have relatively short vector (like 4-8 bits) - Longer vectors. For the first one, just make a case statement, most likely your compiler will find a good implementation. For the second case, I guess you can use a priority encoder followed by a 1hot -> binary encoder. That will be 3 layer of luts. (2 for the prio encoder, one for the 1hot to binary converter). If N is you number of bit : Size of the encoder : N + N/4 (IIRC) Size of the 1hot to binary converter log2(N) * ceil(N/8) If you're interested, I'll try to be more precise when I get home and have more time.Article: 113173
get the following error while trying to create a test bench.
ERROR:Portability:90 - Command line error: Unexpected argument[12] "and" found.Usage: vhdtdtfi {-lib <libname> {<vhdfile>}} [-lang vhdl|verilog] [-module <module_name>] [-prj <project>] [-template <template_file>] [-o <tfifile>] [-err <errfile>] [-deleteonerror]
i've looked around the answers section but still no joy.
please help !
Article: 1131740 (edge aligned) for both see page 8 of this pdf for a picture: http://www.fast-vision.com/Downloads/bgawc4510/DS90CR288A.pdf good luck avishay wrote: > The altlvds Megawizard requires me to specify the data alignment to the > input clock and the output clock. What are the values you entered? > > Avishay
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Threads starting:
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