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Hi, I'm trying to devise an efficient method to generate a ones' complement sum of two 16 bit integers in a single cycle. I'm targeting a Xilinx device and right now I'm using a 32 bit adder. Suppose I want to add x and y : a,b,result : std_logic_vector(15 downto 0); x,y,result_32 : std_logic_vector(31 downto 0); a <= x & y; b <= y & x; result_32 <= a + b; result <= result_32(31 downto 16); Is there a better way to implement this?Article: 113426
Symon wrote: > Austin's advice is good; Hyperlynx has a great 'scope! :-) > HTH, Syms. And it's a steal at $47,500 per seat! What is the cheapest way into HyperLynx?Article: 113427
ma wrote: > Hello, > > I learned that when a signal is multiplied by an IQ signal, the signal can be down sampled by 2. So assume that I have a signal that samples at 100MS and I multiplied it by an IQ signal. Then I can down sample each I and Q to 50MS. How is it working? Do I need a filter before down sampling? Or can I down sample without any filtering? Any example design that show how I can do this preferably in FPGA? A signal needs two samples taken in the time of the period of its highest frequency. They can either be assembles as one stream at the given rate or as two streams at half that rate, one I and one Q. In different words, one complex sample can replace two real-only samples. What do you mean by "multiplied by an IQ signal"? I don't understand the procedure you allude to. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 113428
Metin wrote: > Hi Folks, > > I'm using the BLVDS_25 IO standard for some in/outs in a differential Bus System where the differential bus Lines outside terminated at both ends with 100 Ohm. When the Spartan3 drives the lines, I measure a Differential Voltage of about 2V in Amplitude. That means, I get 1 Volt of Differential Output Voltage from my BLVDS Pins even its specified as 250 - 450 mV in Spartan3 Datasheet. Do someone know why do i get such a high voltage? > > Best Regards Metin You get such a high voltage because you didn't bother to read any data sheet ever printed that includes the BLVDS I/O standard. This is a full-swing 2.5 V signal that explicitly requires specific series/parallel terminations like the early LVDS drivers in FPGAs that didn't have proper current sources. Read the data sheet, bask in the glory of the illustrations that show the required termination networks. Heck - these were so common that Bourns even produced special resistor network packs so designers wouldn't have to use those "bulky" discrete resistors. I hope your design can be hacked up easily. Good luck.Article: 113429
"Kim Enkovaara" <kim.enkovaara@iki.fi> wrote in message
news:VKSfh.926$8i5.325@reader1.news.saunalahti.fi...
> Symon wrote:
>
>> "bijoy" <pbijoy@rediffmail.com> wrote in message
>>>Hi In designing asynchronous FIFOs we have to use Gray code read/write
>>>pointers.
>>
>> Well, no, you don't _HAVE_ to. You can use ordinary binary counters just
>> fine, as long as you design the clock domain crossing bit properly.
>
> But crossing the clock domain with binary counter is hard to do correctly,
> it needs some kind of handshake protocol. It's not enough to just put
> dual flops to each counter bit like with gray coding.
A useful compromise is to have counters in binary, so you can have fast
arithmetic, and then convert from binary to Gray-code, cross the clock
domain, and then convert back again to do the pointer comparison. While
there is some latency, it is usually easier than a bi-directional handshake.
Cheers,
-Ben-
Article: 113430can you describe a little more your app... On Dec 13, 1:03 pm, "Jon Beniston" <j...@beniston.com> wrote: > rpons...@gmail.com wrote: > > I don't need your IP secrecies... > > > This is for my students : what, in your current design, requires using > > a fpga + softcore, in place of a COTS micro controler ? > > less IC -> lower footprint, lower power cons., parallelism,...The first two. > > Cheers, > JonArticle: 113431
rponsard@gmail.com schrieb: > I don't need your IP secrecies... > > This is for my students : what, in your current design, requires using > a fpga + softcore, in place of a COTS micro controler ? > less IC -> lower footprint, lower power cons., parallelism,... I/O Bandwidth. Kolja SulimmaArticle: 113432
On 12 Dec 2006 05:41:46 -0800, paulcullen@purewebsites.co.uk wrote: >What is the sign-and-magnitude of the following 4's complement >number? (Leave answer in base 4). > >The number: 33333210 (base 4) > >Hi, Ive been asked the following question and although slightly >familary with compure match and storage, i can't figure this. I gather >it needs converting Be aware that the answer depends on the word size - if it's a 16 bit number I'd give one answer; if it's larger (say 32 bit) I'd give another answer. - BrianArticle: 113433
Metin, Bus LVDS is not a standard. It is a specialized hack to create a multi-point bus with LVDS like signals. Yes, it is supported, but it requires resistors both at the transmit end, and the receive end. Bus LVDS also can not operate anywhere near the speeds that regular LVDS can. It is unfortunate that someone took a really good standard, like LVDS, and then hacked it to do the multi-point bus job. The fact that it still has "LVDS" in its name should not fool you: it is not a standard, but a solution that has to be customer engineered for every bus connection topology (resistors all change value when you change the drops). AustinArticle: 113434
You can read these papers by Cliff Cummings on aSynchronous FIFO design: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdfArticle: 113435
Hi guys,
I saw another thread with the same topic. but my situation is abit
different. let me explain myself
1) I am using EDK 7.1i and project navigator 7.1i
2) i am doing going by the method of by exporting the project to ISE
after synthesis and getting ISE to do the mapping and pnr.
3) i built a system with 2 interrupt sources around microblaze. here is
the snippets of my mhs file
BEGIN pwm
PARAMETER INSTANCE = pwm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x41310000
PARAMETER C_HIGHADDR = 0x413103ff
BUS_INTERFACE SOPB = mb_opb
PORT PWM_o = pwm_s
PORT PWM_dir_o = pwm_dir_s
PORT pwm_int_o = PWM_Interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = RS232_Interrupt & PWM_Interrupt
END
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_USE_FPU = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 1
PARAMETER C_USE_PARITY = 1
PARAMETER C_CLK_FREQ = 48000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = RS232_Interrupt
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
so i saw that, from another thread on this newsgroup that resource
could be a problem. so i downsized the local block ram size of this
microblaze system by half. unfortunately, i stil get this:
Started process "Map".
Using target part "3s1500fg320-4".
Mapping design into LUTs...
ERROR:MapLib:661 - LUT4 symbol
"opb_intc_0/opb_intc_0/INTC_CORE_I/INTR_DET_I/interrupts<1>1"
(output
signal=opb_intc_0/opb_intc_0/INTC_CORE_I/INTR_DET_I/interrupts<1>)
has input
signal "opb_intc_0/Intr<1>" which will be trimmed. See the trim
report for
details about why the input signal will become undriven.
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for
more
details. Output files will not be written.
Design Summary
--------------
Number of errors : 1
Number of warnings : 2
ERROR: MAP failed
Process "Map" did not complete.
the mapping and pnr goes through when I use only one interrupt source
instead of two:
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = RS232_Interrupt
END
can anybody kindly help me if he has encountered something similar? why
did some signal in my design suddenly get optimised away. it dun look
like resource problem
Chris
Article: 113436shareef.jalloq@lightblueoptics.com wrote: > Hi all, > > I have a requirement to implement a NOR flash controller in a > Spartan-3E. The interface will be 32-bits and will address 1GB of > flash. This means using 16 off 512Mb components connected in 8 banks > of 2. > > I understand that most designs interface the flash directly to an MCU > or CPU that controls the protocol conversion and polling etc. In my > case the MCU is outside of the system and is only acting as a system > controller. I have two high bandwidth datapaths from USB and to an > internal FIFO that need servicing from flash. Ideally, these > interfaces would connect directly to a flash controller within the FPGA > with no connection to the MCU. > > Can anyone point me at any IP blocks for hardware NOR flash > controllers? Or am I going to have to bite the bullet and write it > myself. > > Thanks. > A NOR flash memory controller is a standard asynchronous memory interface, and there are lots of those around. One issue you will run into is capacitive loading on the bus - check the datasheets. Cheers PeteSArticle: 113437
"Jerry Avins" <jya@ieee.org> wrote in message news:Ia6dnYHCE_-gkR3YnZ2dnUVZ_trinZ2d@rcn.net... > ma wrote: > > Hello, > > > > I learned that when a signal is multiplied by an IQ signal, > the signal can be down sampled by 2. So assume that I have a signal that > samples at 100MS and I multiplied it by an IQ signal. Then I can down > sample each I and Q to 50MS. How is it working? Do I need a filter before > down sampling? Or can I down sample without any filtering? Any example > design that show how I can do this preferably in FPGA? > > A signal needs two samples taken in the time of the period of its highest > frequency. They can either be assembles as one stream at the given rate or > as two streams at half that rate, one I and one Q. In different words, one > complex sample can replace two real-only samples. > > What do you mean by "multiplied by an IQ signal"? I don't understand the > procedure you allude to. > > Jerry > -- > Engineering is the art of making what you want from things you can get. > ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ Thanks for your reply. I have a real signal that sampled at say 100MSPS. I want to create an IQ signal from it. I am multiplying it with I and Q signals. After this multiplication, I have two signals one I and one Q. As you explained, it is a complex representation of my signal. So I can have 50MSPS on each stream. How can I do downsampleing in this case? Should I filter the signal before downsampling or not? If I am not doing any filtering, is there any chance for aliasing in this case? Where can I read more about this subject? RegardsArticle: 113438
Hello, I'm just curious whether people have preference when instantiating complex modules (i.e. modules with lots of parameters). Do most of you use GUI tools provided by the vendors to generate the modules, or do you simply code it yourself? Thanks.Article: 113439
Martin wrote: > Hello, > > I'm just curious whether people have preference when instantiating > complex modules (i.e. modules with lots of parameters). Do most of you > use GUI tools provided by the vendors to generate the modules, or do > you simply code it yourself? Thanks. For the mildly complex items, I'll often use the libraries template to code what I need. Sometimes an excerpt straight from the unisims.v file for the Synplify synthesis is simple enough. Occasionally I use the gui but take the generated code for cut & paste to get all the parameters. Almost never did I take a generated modules and include it as the black box element as it was ready to be used. But then I still code my UCFs by hand.Article: 113440
Hello,
I learned that when a signal is multiplied by an IQ signal, the
signal can be down sampled by 2. So assume that I have a signal that samples
at 100MS and I multiplied it by an IQ signal. Then I can down sample each I
and Q to 50MS. How is it working? Do I need a filter before down sampling?
Or can I down sample without any filtering? Any example design that show
how I can do this preferably in FPGA?
Best regards
Article: 113441Why do you need to connect the same clock to more than one clock input on your FPGA? What kind of FPGA are you using? If I had to buffer and translate, I would rather translate, then buffer. Unless you are very careful with your resistors and interconnect, a resistor translator may not work too well. Andy Kurt Kaiser wrote: > Hi there, > > I'm currently having a serious problem: I got an LVPECL clock synthesizer > and I want to connect it to several clock inputs on my FPGA. The FPGA > features 2 LVDS interfaces, whereas each LVDS pair is located at opposite > sides of the device, meaning there will be some extensive routing to do. I > designed a resistor network for the level conversion from LVPECL to LVDS. > What I'd like to know now is > a) Can I route the 2x2 lines (two times differential to the two opposite > sides of the FPGA) one-to-one out of my clock device to the inputs or should > I use a dedicated buffer / repeater IC for clock distribution? > b) If clock buffer are needed, should I use LVPECL buffers and do the > conversion to LVDS level afterwards or should I perfom the conversion before > the buffer and then use an LVDS IC? > c) Where should I place the level conversion network? Is is better to place > it right at the LVPECL output or is it more advisable to do it right before > the FPGA inputs after a transmission line length of about 7 cm? > Any help, comments, advice is highly appreciated! > > Thank you all very much. > KurtArticle: 113442
<snip> Its not a matter of resources. As the error message says - " output signal=opb_intc_0/opb_intc_0/INTC_CORE_I/INTR_DET_I/interrupts<1> has input signal "opb_intc_0/Intr<1>" which will be trimmed. See the trim report for details about why the input signal will become undriven" The signal - opb_intc_0/Intr<1> is undriven due to some reason; you need to figure that out why and see what needs to be changed. HTH.Article: 113443
I am using a digital scope and triggering on rising edge. I do a single sample and use two cursors to measure the reflection. One side of the probe is on the pin, the other side is on ground. BTW, 50 ohm source terminator cleaned up the data lines a lot (lowest it drops to now is 2.9V), but my 25mhz clock signal still has a lot of noise, since I didn't design my interface board to have a source terminator on the clock.Article: 113444
There is a wrong way and a right way to convert binary to Gray count values: The wrong way hangs the (simple!) combinatorial conversion logic (XORs) on the binary outputs. That does you no good, since the Gray code will just reflect the binary transient errors. The right way takes the D inputs of the binary counter (, converts them independently to Gray and registers them in their own flip-flops. Now you have two parallel rgisters, both counting in step, the first in binary, the other in Gray, and there are no funny decoding spikes. BTW, only Gray counter outputs have the feature that you can compare two asynchronous counters for identity, without transient errors. If the Gray code does not come from a counter, it might change multiple bits per transition... Fast asynchronous FIFOs with configurable flag values are definitely not a trivial design exercise. We got it right in Virtex-5, after a silly oversight in Virtex-4. Peter Alfke On Dec 13, 6:31 am, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "Kim Enkovaara" <kim.enkova...@iki.fi> wrote in messagenews:VKSfh.926$8i5.325@reader1.news.saunalahti.fi... > > > Symon wrote: > > >> "bijoy" <pbi...@rediffmail.com> wrote in message > >>>Hi In designing asynchronous FIFOs we have to use Gray code read/write > >>>pointers. > > >> Well, no, you don't _HAVE_ to. You can use ordinary binary counters just > >> fine, as long as you design the clock domain crossing bit properly. > > > But crossing the clock domain with binary counter is hard to do correctly, > > it needs some kind of handshake protocol. It's not enough to just put > > dual flops to each counter bit like with gray coding.A useful compromise is to have counters in binary, so you can have fast > arithmetic, and then convert from binary to Gray-code, cross the clock > domain, and then convert back again to do the pointer comparison. While > there is some latency, it is usually easier than a bi-directional handshake. > > Cheers, > > -Ben-Article: 113445
As of today, it is only useful whilie compiling. But that does not preclude it from being used in the future, say to pick up customized libraries during linkage. To be safe you should add it to both the compile and link steps. "Alfmyk" <alfmyk@hotmail.com> wrote in message news:eea0ff2.-1@webx.sUN8CHnE... > Hi all. > > I'm using ISE 8.2.03i & EDK 8.2.02i. Moreover I'm using a Spartan 3E > starter Kit board for software development. > > I'have seen compiling via EDK environment that now has been added this > option: -mcpu=4.00.b I know it's a machine dpendent option and generally > is enough add it to mb-gcc (or mb-g++) when user compile & link all > together. > > But in my case I have created some my makefiles with different steps of > compiling and then linking. > > Question: this new option -mcpu=<...> MUST be used ONLY in compiling, ONLY > in linking or it's important for BOTH (link & comp.) ? > > Thanks in advance for any answers. > > Al.Article: 113446
Nicolas Matringe wrote: > John Adair a écrit : > > >>Definately on the smaller end. Here is a picture >>http://www.geograph.org.uk/photo/270797 I found. > > > Looks like a stone to me ... (a rather big one, I admit) > ;o) > > Nicolas > I always thought stones were the same size... 14 lbs. RBArticle: 113447
"John" <seabass950@yahoo.com> wrote in message news:eea0f8b.6@webx.sUN8CHnE... >I am using a digital scope and triggering on rising edge. I do a single >sample and use two cursors to measure the reflection. > > One side of the probe is on the pin, the other side is on ground. > > BTW, 50 ohm source terminator cleaned up the data lines a lot (lowest it > drops to now is 2.9V), but my 25mhz clock signal still has a lot of noise, > since I didn't design my interface board to have a source terminator on > the clock. Keep in mind that a single destination doesn't care about how the source looks as long as the destination looks clean. It isn't clear from your description if you're talking about the source or the load. Look only at the destination and report if your signal still looks unclean or if - remarkably - you suddenly see very nice transitions.Article: 113448
ma wrote: > Hello, > > I learned that when a signal is multiplied by an IQ signal, the > signal can be down sampled by 2. Yes, no, maybe. Yes, if the conditions are right. No, if you're too simpleminded about it. Maybe you can downsample even more. > So assume that I have a signal that samples > at 100MS and I multiplied it by an IQ signal. Then I can down sample each I > and Q to 50MS. How is it working? Do I need a filter before down sampling? > Or can I down sample without any filtering? The Nyquist/Shannon theorem states that you need samples at a rate of 2*fo to accurately replicate a signal with a bandwidth of fo. It doesn't say this has to be straight sampling. So in the case of I & Q modulation you are getting two channels, which means you should be able to send the pairs at half the rate. A signal that 'fits' a 100MS/sec rate will have no significant energy above 50MHz. With no other knowledge of the signal, the smartest I & Q demodulation that you could do would be to use a carrier frequency of 25MHz. This means that your I & Q carrier channels would go I: 1 0 -1 0 1 0 -1 0 Q: 0 -1 0 1 0 -1 0 1 In this case, all you have to do to 'downsample' is discard the samples where the carrier is zero. Frankly, unless you need to do processing on the I & Q channels I don't see much value in this. What you _can_ do with I & Q downsampling is note that for any given _bandwidth_ of signal you can I & Q downconvert, then sample with half of the sampling rate that you could have used if you had just used undersampling -- and your analog filtering task is much easier. After the sampling is done, however, you spin off into pointless mathematical pondering that don't help you get product out the door. > Any example design that show > how I can do this preferably in FPGA? > > Best regards > > -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 113449
In the presence of numerous styles for designing asynchronous FIFOs, how does FPGA synthesis tools infer the FIFO specified in RTL? Thanks in advance. Ashish
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Compare FPGA features and resources
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