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Very interesting. Thanks John! We haven't done much research into the PowerPC. If only there were more hours in a day.... I have connected up the FSL to test some things. The only problem I see is that the FSL_Has_Data signal is not behaving as expected. I am routing that signal from the fsl core to my custom IP core so that I can output that as an interrupt. It basically just passes through the core and is assigned interrupt specific info in the mpd. This is connected to the intc IP from Xilinx. The signal goes high as expected and interrupts the MicroBlaze. I am just experimenting so the ISR just does 2 non-blocking reads (I've tried blocking and the same behavior occurs). Basically, the FSL FIFO is 8-bits wide and I put 2 bytes into it via the custom IP. I am also using ChipScope to monitor all the signals of interest. It triggers right before data is written into the custom core. So I can see the Has_Data signal go high, but it takes around 60 OPB clock cycles for it to go low. It seems that this would happen much sooner. The signal should interrupt MicroBlaze in a few clock cycles and then the 2 reads are essentially 6 assembly instructions so I can't see where the 60 clocks come from. I don't think the latency of the interrupt is that long. But I have to do some more detailed experimentation to find out. I need that Has_Data signal to go low in time for more data to come in to eventually set Has_Data high again. With this latency, the signal never goes low in time.Article: 115576
On 13 Feb 2007 20:30:40 -0800, "motty" <mottoblatto@yahoo.com> wrote: >Very interesting. Thanks John! We haven't done much research into >the PowerPC. If only there were more hours in a day.... > >I have connected up the FSL to test some things. The only problem I >see is that the FSL_Has_Data signal is not behaving as expected. I am >routing that signal from the fsl core to my custom IP core so that I >can output that as an interrupt. It basically just passes through the >core and is assigned interrupt specific info in the mpd. This is >connected to the intc IP from Xilinx. The signal goes high as >expected and interrupts the MicroBlaze. I am just experimenting so >the ISR just does 2 non-blocking reads (I've tried blocking and the >same behavior occurs). > >Basically, the FSL FIFO is 8-bits wide and I put 2 bytes into it via >the custom IP. I am also using ChipScope to monitor all the signals >of interest. It triggers right before data is written into the custom >core. So I can see the Has_Data signal go high, but it takes around >60 OPB clock cycles for it to go low. It seems that this would happen >much sooner. The signal should interrupt MicroBlaze in a few clock >cycles and then the 2 reads are essentially 6 assembly instructions so >I can't see where the 60 clocks come from. I don't think the latency >of the interrupt is that long. But I have to do some more detailed >experimentation to find out. I need that Has_Data signal to go low in >time for more data to come in to eventually set Has_Data high again. >With this latency, the signal never goes low in time. > Use the write control signal as an EDGE triggereed interrupt, in such a way the interrupt signal will last as long as you write data, but it will be alive until you acknowledge it. Regards, ZaraArticle: 115577
On Tue, 13 Feb 2007 18:11:52 GMT, "MikeJ" <mikej@fpgaarcade.nospam.com> wrote: >Hello all, > >I would like to do some simple and dirty DSP to roughly approximate a RC >audio filter. > >I think I can do it something like this (PSEUDO code here, ignoring bit >depths and multiplier instantiation issues) > >I am aiming for a cut of frequency of ~713 Hz > >Audio is an 8 bit unsigned output (from a YM2149 audio chip as it happens) >Ena_20K is a single clock enable at my desired sampling frequency (Freq) > >wait until rising_edge(clk) >if (Ena_20K = '1') then > Audio_sampled <= Audio; -- sample output > > Audio_filtered <= Audio_filtered + ( Audio_filtered_t1 - Audio_filtered) * >K > > Audio_filtered_t1 <= audio_filtered; -- previous value >end if; > > >Audio_out <= Audio_filtered(some top bits) > >Is this correct?? >Can I get away with n bit unsigned maths, or do I need to offset / sign? > >Does anybody know off the top of their head how I calculate K given Freq and >a cut of frequency? > >Anyone know of any good on-line resources? >I have looked around a bit, but everything needs Matlab nowadays which I >don't have handy at home :) > >I have done a lot of video filtering using FIRs, but I have forgotten the >little I used to know about IIRs.... >Any input gratefully received. > >Regards, >MikeJ >www.fpgaarcade.com > > If you do, every clock, out = out + (in-out)/k that approximates a single-pole RC lowpass filter. The divide by K can just be a right-shift by R bits. Ideally you should lose no bits, so if the input is digitized to N bits, do the math to N+R bits width. (in-out) is of course signed. If the clock period is T, then for a unit step input, the first output step has amplitude 1/k, so the effective tau is T*k, so the corner frequency is 1/(2*pi*T*K). I think. JohnArticle: 115578
hi, i am working on virtex 2 pro fpga i have a basic doubt 1. i am using bank 5 for my input and outputs. i have vref in the bank which is not connected to supply(3.3v). my doubt is whether i should connect it to the supply voltage. if i am not using the I/O of any bank do i have to connect the VREF of that bank to the corresponidng supply voltage or i can leave as unconnected. if u connect one pin of vref to supply voltage is enough as the other VREF are internally connected to each other. 2. what are VCCINT, VCCAUX, VCCO,VREF VIN,VTS in fpga any particular rules that need to be followd while working with them and each bank can have different VCCAUX supply and each bank can be supplied with different GCLK (say bank 5 has GCLK5S and GCLK4P should have same supply GCLK as internally they are connected to same GCLK right). if i can give different banks with different GCLK values then can i use GLK pin in one bank clock to the other bank. regards srikArticle: 115579
Himlam8484 schrieb: > > Hi Eilert, > > Thank you very much for your idea. i am using a IC XC3S400. I know it > get a Picoblaze inside. First, i only test program PCCOOMP to sure it > runs well. "open failed" means PCCOMP can not open file( for example, > I downloaded a file from the place i loaded PCCOMP soft). I open these > files with Borland C, and they are Ok. But when i compiled in PCCOMP , > it always failed. > > I have no occassion to get a code to load into Picobalze. > > By the way, i think you get much knowledge about FPGA, can you make me > clear somethings? i would like to program for Picoblaze In C, i have > to include "Spartan3.h" to be able to use Picoblaze languege in C, > wouldn't I? Please tell me with my stupid questions. > > have a nice day! > > Him Lam > Hi Him, Today I have tested PCCOMP 1.8.4 with two of its examples (sqrt and fibonacci) Two things have to be taken care of: the header files have either to be placed in a subdirectory called lib, or the includes hav to be changed to e.g. #include "spartan3.h" if the header files are in the same directory as the source file. whatever you prefer. i used the following commandline: pccomp -c -s example_sqrt.c pccomp -c -s ex_fibnacci_s3.c there was a little error in the fibonnacci source: on line 69 you have to add a missing #endif but then it compiles without errors. after all mi directory looked like this: 14.02.2007 08:02 <DIR> . 14.02.2007 08:02 <DIR> .. 14.02.2007 07:40 941 example_sqrt.c 14.02.2007 07:41 5.567 example_sqrt.fra 14.02.2007 07:41 5.574 example_sqrt.pod 14.02.2007 07:41 5.566 example_sqrt.psm 14.02.2007 08:02 2.105 ex_fibnacci_s3.c 14.02.2007 08:02 5.532 ex_fibnacci_s3.fra 14.02.2007 08:02 5.563 ex_fibnacci_s3.pod 14.02.2007 08:02 5.531 ex_fibnacci_s3.psm 03.12.2006 13:45 356.287 pccomp.exe 03.07.2005 14:41 211.332 pccomp_manual.pdf 28.01.2005 09:23 771 spartan3.h 04.02.2005 15:00 768 sqrt.h The *.psm files have to be assembled with the kcpsm3.exe In order to do so you have to rename or copy the *.psm files to dos-like 8.3 filenames. e.g. sqrt.psm and fibo.psm. Now kcpsm3 can assemble these sources, and your directory may look like this: 14.02.2007 08:16 148 CONSTANT.TXT 14.02.2007 07:40 941 example_sqrt.c 14.02.2007 07:41 5.567 example_sqrt.fra 14.02.2007 07:41 5.574 example_sqrt.pod 14.02.2007 07:41 5.566 example_sqrt.psm 14.02.2007 08:02 2.105 ex_fibnacci_s3.c 14.02.2007 07:41 2.097 ex_fibnacci_s3.c~ 14.02.2007 08:02 5.532 ex_fibnacci_s3.fra 14.02.2007 08:02 5.563 ex_fibnacci_s3.pod 14.02.2007 08:02 5.531 ex_fibnacci_s3.psm 14.02.2007 08:16 8.085 FIBO.COE 14.02.2007 08:16 5.703 FIBO.DEC 14.02.2007 08:16 8.876 FIBO.FMT 14.02.2007 08:16 7.168 FIBO.HEX 14.02.2007 08:16 13.806 FIBO.LOG 14.02.2007 08:16 4.309 FIBO.M 14.02.2007 08:16 7.179 FIBO.MEM 14.02.2007 08:02 5.531 fibo.psm 14.02.2007 08:16 23.300 FIBO.V 14.02.2007 08:16 19.273 FIBO.VHD 05.07.2005 08:33 90.308 KCPSM3.EXE 14.02.2007 08:16 228 LABELS.TXT 14.02.2007 08:16 25.517 PASS1.DAT 14.02.2007 08:16 25.517 PASS2.DAT 14.02.2007 08:16 30.702 PASS3.DAT 14.02.2007 08:16 39.894 PASS4.DAT 14.02.2007 08:16 53.003 PASS5.DAT 03.12.2006 13:45 356.287 pccomp.exe 03.07.2005 14:41 211.332 pccomp_manual.pdf 25.01.2002 15:17 857 ROM_form.coe 04.07.2005 17:05 15.275 ROM_form.v 05.07.2005 08:39 12.748 ROM_form.vhd 28.01.2005 09:23 771 spartan3.h 14.02.2007 08:14 8.085 SQRT.COE 14.02.2007 08:14 5.998 SQRT.DEC 14.02.2007 08:14 10.025 SQRT.FMT 04.02.2005 15:00 768 sqrt.h 14.02.2007 08:14 7.168 SQRT.HEX 14.02.2007 08:14 15.318 SQRT.LOG 14.02.2007 08:14 4.604 SQRT.M 14.02.2007 08:14 7.179 SQRT.MEM 14.02.2007 07:41 5.566 sqrt.psm 14.02.2007 08:14 23.300 SQRT.V 14.02.2007 08:14 19.273 SQRT.VHD The files SQRT.VHD/V/MEM etc. and FIBO.VHD/V/MEM etc. are the sources for your Picoblaze-ROM. Depending on the flow you use you have to include the right one to your ISE-Project. Now you can implement your design and download the bitfile to your FPGA. I don't know which source you have tried. The above examples work just fine. Have a nice synthesis EilertArticle: 115580
fpgabuilder schrieb: >> I know, it sounds kind of tricky, but a lot of designers are using >> circuits like this. >> > > Seems like a natural way to do it. I do it all the time. Actually, I > would not even use the internal RAM unless I needed a spatial > operation as it seems is the original poster's problem. > > I wasn't sure if you were talking about applying your solution to all > the array elements simultaneously. > > Best, > Sanjay > Hi Sanjay, I see you got my point. :-) In fact my posting was a little joke to pull CMOS back to reality by presenting a simple but cunny solution using big words like "virtual" etc. :-) Even his convolution can be done that way. Just needs an extra accumulating adder, no big deal. I really haa to smile when I read things like: parameter nColumns = 100; parameter nRows = 200; parameter RAM_WIDTH = 8; and later: "i did't think about doing it as the data arives, as it seems very complicated. the project im working on is not a commrcial one. i need to prove a concept." Well.. a simple calculation shows that he needs 100*200*8*2 FF to store the Input data. That's 320000 FFs! In the Xilinx Architecture that's like 160000 Slices or 80000 CLBs. Even a Virtex 5 LX330 can't handle that. And even if he reduces his array to a size that fits into his real existing chip, the resulting combinatorical circuit to duo the calculation fully parallel will be so complex that the resulting delay will be somewhere in the millisecond range. Great proof of concept. Brainless nonsense that is.Article: 115581
Dear All,
I have an ATM/SDH design that uses the Xilinx MGT with 8b/10b disabled
and a 10-bit wide interface.
I drive the Tx side from an external 62.208MHz clock source passed
through a DCM:
REFCLK => clock_62_208 -- pre DCM
TXUSRCLK => clock_31_104 -- post DCM [CLKDV ]
TXUSRCLK2 => inverted_clock_62_208 -- post DCM [CLK180]
This gives me a serial line rate of 622.08MHz with my internal logic
processing the data at 62.208MHz @ 10-bits wide.
I drive the Rx side from the MGT RXRECCLK. Since the RXRECCLK is 1/20
of the received line rate (1/20th of 622.208MHz = 31.104MHz) I pass it
through a DCM to get back to a 62.208MHz source (and inverted):
REFCLK => clock_62_208 --pre DCM (external 62.208MHz clock source)
RXUSRCLK => recovered_clock_31_104 -- post DCM [CLK0]
RXUSRCLK2 => recovered_inverted_clock_62_208 -- post DCM [CLK2X180]
Since processing data that is 10-bits wide is a pain I generate a
20/8ths clock from the RXRECCLK using the DCM to give me
(recovered_clock_77_76). I then put the data into a FIFO 10-bits wide
@ 62.208MHz and read it out 8-bits wide @ 77.76MHz.
This all works and my design operates correctly, the problem that I
have is that the recovered clock mechanism I have in place uses a lot
of Global Clock Resources (the 3 that are generated by the DCM with
RXRECCLK as the source are a real cause for concern).
When duplicating this mechanism for two MGT instantiations. Although
the Tx side of the two MGTs share the global clocking resources the Rx
sides cannot and as a result my design uses an extra 3 global clocking
resources.
Due to other areas of my design with one MGT instantiated I am using
13 Global Clocks. This rises to 16 Global Clocks with 2x MGT
instantiation, which is ok as the FPGA I am using XC2VP50 has 16
GCLKs.
Now I want to have 4x MGT instantiations and XST is reporting 22 GCLKs
and failing to map, which is obvious.
To me the key is to reduce the number of GCLKs used by the DCM that is
driven by the RXRECCLK. I assume that it is possible as with a design
containing 16x MGT instantiations (as available on the XC2VP50) would
clearly not be possible.
I have looked at XAPP763 for inspiration but cannot see how this will
help me.
Any ideas?
Regards,
Simon
---- CODE BELOW ----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all; -- used to instantiate the FDC and FDP
components
entity channel_rocket_io is
port (
cha_bit_stream_out_p : out std_logic;
cha_bit_stream_in_p : in std_logic;
cha_bit_stream_out_n : out std_logic;
cha_bit_stream_in_n : in std_logic;
word_stream_out : out std_logic_vector ( 9 downto 0 );
word_stream_in : in std_logic_vector ( 9 downto 0 );
rclk0_62_208mhz_mgt : in std_logic;
rclk0_62_208mhz_reset : in std_logic;
rclk0_62_208mhz_div2 : in std_logic;
rclk0_62_208mhz : in std_logic;
rx_buffer_error : out std_logic;
tx_buffer_error : out std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
nreset_niu : in std_logic;
rx_rec_clk_62_208 : out std_logic;
rx_rec_reset_62_208 : out std_logic;
rx_rec_clk_77_76 : out std_logic;
rx_rec_reset_77_76 : out std_logic
);
end channel_rocket_io;
architecture RTL of channel_rocket_io is
signal recovered_clock : std_logic; -- used to connect the recovered
clock from the MGT to the DCM
-- the recovered clock is always a 20th of the data rate (31.104MHz
= 1/20th of 622.208MHz)
signal recovered_62_208mhz_div2 : std_logic; -- used to connect the
DCM clock (31.104MHz) to the MGT
signal recovered_inverted_62_208mhz : std_logic; -- used to connect
the DCM clock x2 inverted (62.208MHz) to the MGT
signal inverted_rclk0_62_208mhz : std_logic := '0'; -- used to carry
the locally inverted rclk0_62_208mhz signal
signal rx_elastic_buffer_full : std_logic_vector( 1 downto 0 ) :=
B"00"; -- used to connect the rx elastic buffer error signal to the
rx_buffer_error
signal tx_elastic_buffer_error : std_logic := '0'; -- used to
connect the tx elastic buffer error signal to the tx_buffer_error
-- Component definition of MGT - START
COMPONENT chanel_rocket_io_mgt
PORT(
LOOPBACK : IN std_logic_vector(1 downto 0);
POWERDOWN : IN std_logic;
REFCLK : IN std_logic;
RXN : IN std_logic;
RXP : IN std_logic;
RXPOLARITY : IN std_logic;
RXRESET : IN std_logic;
RXUSRCLK : IN std_logic;
RXUSRCLK2 : IN std_logic;
TXDATA : IN std_logic_vector(9 downto 0);
TXINHIBIT : IN std_logic;
TXPOLARITY : IN std_logic;
TXRESET : IN std_logic;
TXUSRCLK : IN std_logic;
TXUSRCLK2 : IN std_logic;
RXBUFSTATUS : OUT std_logic_vector(1 downto 0);
RXDATA : OUT std_logic_vector(9 downto 0);
RXRECCLK : OUT std_logic;
TXBUFERR : OUT std_logic;
TXN : OUT std_logic;
TXP : OUT std_logic
);
END COMPONENT;
-- Component definition of MGT - END
-- Component definition of DCM - START
COMPONENT rec_clk_dcm
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
CLK2X_OUT : OUT std_logic;
CLK2X180_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
-- Component definition of DCM - END
signal nreset_niu_in : std_logic := '0'; -- used to register the
reset the nreset_niu global reset signal
signal reset_niu_in : std_logic := '0'; -- used to register the
inverted nreset_niu global reset signal
-- the following signal are used to synchronise the global reset to
the 77.76MHz recovered clock
signal rcclk_77_76_nreset_d : std_logic := '0';
signal rcclk_77_76_reset_d : std_logic := '0';
signal rcclk_77_76_inv_reset : std_logic := '0';
-- the following signal are used to synchronise the global reset to
the 62.208MHz recovered clock
signal rcclk_62_208_nreset_d : std_logic := '0';
signal rcclk_62_208_reset_d : std_logic := '0';
signal rcclk_62_208_inv_reset : std_logic := '0';
-- the following signals are used to connect the output of the DCM to
the global reset synchronisation logic
signal local_rx_rec_clk_77_76 : std_logic;
signal local_rx_rec_clk_62_208 : std_logic;
signal RCCLK_LOCKED : std_logic; -- used to indicate when the DCM has
a lock on the recovered clock from the MGT
begin
rx_buffer_error <= rx_elastic_buffer_full(1); -- to pipe the rx
elastic buffer overrun / underrun
tx_buffer_error <= tx_elastic_buffer_error; -- to pipe the tx elastic
buffer overrun / underrun
inverted_rclk0_62_208mhz <= not rclk0_62_208mhz; -- using the local
clock invertor as suggested by the Xilinx Rocket IO User Manual
-- Rocket IO Multi Gigabit Transceiver Instantiation
chanel_rocket_io_mgt_INST : chanel_rocket_io_mgt
port map (
LOOPBACK => B"00", -- 00 - NORMAL, 10 - SERIAL LOOPBACK, 01 -
PARALLEL LOOPBACK
POWERDOWN => '0', -- always remain powered
REFCLK => rclk0_62_208mhz_mgt, -- PRE DCMs 62.208MHz clock
source from the external oscillator
RXN => cha_bit_stream_in_n, -- negitive pin of the
differential receiver pair
RXP => cha_bit_stream_in_p, -- positive pin of the
differential receiver pair
RXPOLARITY => '0', -- no inversion of the rx differential
pair, as per the VMETRO instructions
RXRESET => rx_reset, -- 1 = RESET MODE, 0 = NORMAL MODE
RXUSRCLK => recovered_62_208mhz_div2, -- output of the local
DCM
RXUSRCLK2 => recovered_inverted_62_208mhz, -- output of the
local DCM
TXDATA => word_stream_in, -- 10-bit word provided for the
paralledl to serial conversion
TXINHIBIT => '0', -- always enable the transmitter
TXPOLARITY => '1', -- inversion of the tx differential pair,
as per the VMETRO instructions
TXRESET => tx_reset, -- 1 = RESET MODE, 0 = NORMAL MODE
TXUSRCLK => rclk0_62_208mhz_div2, -- output of the DCM inthe
pf03_clock entity
TXUSRCLK2 => inverted_rclk0_62_208mhz, -- output of the DCM
inthe pf03_clock entity
RXBUFSTATUS => rx_elastic_buffer_full, -- used to indicate a
rx buffer underrun / overrun
RXDATA => word_stream_out, -- 10-bit word provided after the
serial to parallel conversion
RXRECCLK => recovered_clock, -- input to the local DCM
TXBUFERR => tx_elastic_buffer_error, -- used to indicate a
tx buffer underrun / overrun
TXN => cha_bit_stream_out_n, -- negitive pin of the
differential transmitter pair
TXP => cha_bit_stream_out_p -- positive pin of the
differential transmitter pair
);
-- Digital Clock Manager Instantiation for the Recovered Clock from
the MGT
REC_CLK_DCM_INST: rec_clk_dcm PORT MAP(
CLKIN_IN => recovered_clock, -- this is the recovered clock from the
MGT
RST_IN => '0', -- Must be set to '0' to work
CLKFX_OUT => local_rx_rec_clk_77_76,
CLK0_OUT => recovered_62_208mhz_div2,
CLK2X_OUT => local_rx_rec_clk_62_208,
CLK2X180_OUT => recovered_inverted_62_208mhz,
LOCKED_OUT => RCCLK_LOCKED
);
-- OFF CHIP RESET
nreset_niu_in <= nreset_niu;
reset_niu_in <= not nreset_niu;
-- RCCLK 77.76 RESET LOGIC
RCCLK_77_76_NRESET_REG: FDC port map (Q=>RCCLK_77_76_nreset_d,
D=>nreset_niu_in, C=>local_rx_rec_clk_77_76, CLR=>reset_niu_in);
RCCLK_77_76_reset_d <= not RCCLK_77_76_nreset_d;
RCCLK_77_76_RESET_REG: FDP port map (Q=>RCCLK_77_76_inv_reset,
D=>RCCLK_77_76_reset_d, C=>local_rx_rec_clk_77_76, PRE=>reset_niu_in);
rx_rec_reset_77_76 <= not RCCLK_77_76_inv_reset when RCCLK_LOCKED =
'1' else '0';
rx_rec_clk_77_76 <= local_rx_rec_clk_77_76;
-- RCCLK 62.208 RESET LOGIC
RCCLK_62_208_NRESET_REG: FDC port map (Q=>RCCLK_62_208_nreset_d,
D=>nreset_niu_in, C=>local_rx_rec_clk_62_208, CLR=>reset_niu_in);
RCCLK_62_208_reset_d <= not RCCLK_62_208_nreset_d;
RCCLK_62_208_RESET_REG: FDP port map (Q=>RCCLK_62_208_inv_reset,
D=>RCCLK_62_208_reset_d, C=>local_rx_rec_clk_62_208,
PRE=>reset_niu_in);
rx_rec_reset_62_208 <= not RCCLK_62_208_inv_reset when RCCLK_LOCKED =
'1' else '0';
rx_rec_clk_62_208 <= local_rx_rec_clk_62_208 ;
end RTL;
Article: 115582> Great proof of concept. Brainless nonsense that is. im not trying to proove a concept regarding SIMULTANIOUS SUBSTRACTION using FPGA's. its bit more complicated and, this substraction thing (and total verilog code) is just a tool to prove it. thats why i dont bother about the best, most cost efficient way of doint it, as long as i can get results fast. and the code i mentioned is just an example. the actual matrix is maximum = 100 x 10, which allows me to do this in a real chip. and i dont mind waiting for 100 milliseconds for the calculation, as the current calculation takes 3 seconds to complete. (this is using direct convolution, without doing FFT). thank you.Article: 115583
In this message http://groups.google.it/group/comp.arch.fpga/browse_thread/thread/4b6b9f8a976483ec/8dbea4a95f3e91f7?lnk=gst&q=polybus&rnum=2&hl=it# Josh Rosen provided detailed information about comparative performance tests he made (see also http://www.polybus.com/linux_hardware/ index.htm). When he posted that message AMD processors were definitively the best choiche. Did something changed since then? Have Intel processors released in the meanwhile filled the gap? Thanks in advance, llandreArticle: 115584
Hi all, I have a problem with the CoreABC microprocessor from Actel. When I generate this core and program it with sample 2 (I work in the hard configuration on an M7A3PE600 FPGA - the CoreMP7 Dev. Kit Board) to blink a led I am only capable of connecting the output ports of the VHDL code to pins. It is not possible to connect PCLK to the correct clock pin... or even to connect the Input port to a input pin. Can someone help me out? Kind regards, Vince http://mobile.skynetblogs.beArticle: 115585
Hi groups, is there something special to get kcpsm3 running on linux/wine ? my wine conf seems ok (FileZila win edition is running fine) but KCPSM3.EXE faills (Unhandled page fault on read access to 0xffffffff...) any idea,Article: 115586
I am trying to design a system which has a BLOCK RAM on the OPB Bus , interfaced through a OPB_BRAM_IF_CNTLR. I first add an "opb_bram_if_cntlr_0" , and connected it as a slave on the OPB Bus . The system block diagram shows that I have made the slave connection properly, Next i add a "bram_block" and connect the PORT A of the bram_block with the PORT A of the "opb_bram_if_cntlr_0" . Now when i generate the system block diagram, my opb_bram_if_cntrl_0 is no longer on the OPB Bus. !!! More on the console window I get the following error message "Memory controller opb_bram_if_cntlr_0 has a floating bus interface " ... Does any one have any idea , why this could be happening. Thank You VenuArticle: 115587
Joe posted in response to a post from C.P.G.:
">>> Perhaps instead of having simply "Others", it could allow someone to write
something: e.g. "Others
(please elaborate): I use ABEL and Java".
[..] it isn't supported in major FPGA
software Quartus and ISE, so what's the point?"
What has that got to do with anything? You could ask what is one's
preferred way to write comments, and if a VHDL fan answers that his
preferred way is by bracketing with /* and */ the lack of support for
this in all VHDL standards except the most recent (Accellera) VHDL
standard does not affect the preference of how to comment -- which
is a very different concept of how one actually is allowed to
comment. I would like to not have to use the end of a line as a
bracket for a comment in VHDL, but I am disgusted that the /**/
comments in VHDL will not be nestable (thereby copying C by too far),
so I may stick to the traditional commenting form as it is much
easier for temporarily commenting out code which itself has comments.
" I try to include
languages supported by vendor software only."
A number of languages used for hardware description are not available
from vendors.
" But Java??? Isn't this a
computer language. I try not to include too many computer languages,
as in theory if I do then most computer languages can be used for
FPGA, ues even PERL.
[..]"
Java is a computer language. If you read the literature, you would
read that many computer languages or languages whose creators were
inspired by computer languages have been used for describing
logic, though such claims might not always be made honestly. Some examples:
R. Helaihel, K. Olukotun, "Java as a Specification Language
for Hardware-Software Systems", IEEE/ACM ICCAD, 1997;
APL; Scheme (I am referring to Verischemelog, not SKILL nor SKILL++);
Python (MyHDL) (Python is a major rival to Perl); Haskell (Hawk; and
Lava); ML (HDCaml); Ada (even if VHDL is not counted as Ada); and
others which I have forgotten having heard about.
N.B. I did not say that anyone really does have a preference for Java
(I most certainly do not), I gave an example of how someone could give
an answer in a better version of the "Others" option on your webpage
when I wrote "Perhaps instead of having simply "Others", it could
allow someone to write
something: e.g. "Others
(please elaborate): I use ABEL and Java""
Joe wrote:
"There's a difference. Usenet postings will be archived after a few
months, but my forum poll is mean to run FOREVER. So, people can keep
growing the poll results in time."
Many websites were meant to last forever but after many years they
ceased to be and their contents not preserved for interested parties
in the future. This may even apply to some archives of newsgroups such
as can be found from
HTTP://Usenet.derKeiler.com/Archive/Comp/comp.arch.fpga/2007-02/msg00332.html
and
HTTP://groups.Google.com
(and maybe
WWW.FPGA-FAQ.org/archives/threads_2007_02.html
but it is going up to only 2007 February 9th today)
but in some form or another, they may be accessible for considerably
larger, well maybe until Google might sometime charge for accessing
its archive.
">>>A number of other points: many people will not bother to create an
account just to vote on a forum ...
Registration is simple, there's no email activation required."
I concede that is less inconvenient than other websites.
" Please
help grow the poll vote count if you care, it takes less than i minute
to insert your "nickname" and "password" :)"
Ah, but the inconvenience of such websites: yet another account to
create, and yet another password to somehow remember. Ick.
">>> Another thing: one may prefer to not have a single language or to
always use the same one.
Yes, this is true. But there must be one that you like (favorite)"
My favorite is Ada. If VHDL is not to be considered as being Ada, then
my favorite is still Ada, but VHDL is not far behind in my preferences
though I do think that some parts of it are atrocious, e.g.
some_signal <=
no_good_effect_but_no_warning_and_will_have_a_bad_impact_on_the_simulation;
some_signal <= a_value_which_actually_wins;
and for anything which is called "erroneous" in the standard
"implementations are not
required to detect and report this condition"
and in
IEEE P1076/D3.2, December 10, 2006:
"NOTES:
1 - For parameters of array and record types, [..] If[..] there are
multiple access paths to
such a parameter (for example, if another formal parameter is
associated with the same actual parameter), then the value of the
formal is undefined after updating the actual other than by updating
the formal. A description using such an undefined value is erroneous.
[..]"
Feel free to place my vote for me on your website. If it is not
anonymous, feel free to identify me.
Regards,
Colin Paul Gloster
Article: 115588On Wed, 14 Feb 2007 03:40:23 -0800, llandre wrote: > In this message > http://groups.google.it/group/comp.arch.fpga/browse_thread/thread/4b6b9f8a976483ec/8dbea4a95f3e91f7?lnk=gst&q=polybus&rnum=2&hl=it# > Josh Rosen provided detailed information about comparative performance > tests he made (see also http://www.polybus.com/linux_hardware/ > index.htm). > When he posted that message AMD processors were definitively the best > choiche. Did something changed since then? Have Intel processors > released in the meanwhile filled the gap? > > Thanks in advance, > llandre I haven't gotten around to updating that web page yet however I have done the benchmarks. The Core2 with 4M caches is generally about 30% faster on a clock for clock basis then the Athlon 64 X2 with 1M caches. NCVerilog is very cache sensitive so it benefits more from the larger caches of the Core2. With recordvars on I see a 69% improvement on a clock for clock basis for NCverilog on a Core2 vs the Athlon 64 X2. With recordvars off the gain is the same 30% that I see with the Xilinx tools. One more thing, the Core2 is very overclockable. I'm running my E6700 (2.66MHz) at 3GHz and it's been completely stable under heavy load. I've been running it like that for a couple of months, and I've had overnight NCVerilog regressions running on both cores most every night for all of that time. I wrote a system stress test to make sure that the system was reliable in spite of the overclocking, it's available here http://www.polybus.com/sys_basher_web/Article: 115589
CMOS schrieb: >> Great proof of concept. Brainless nonsense that is. > > im not trying to proove a concept regarding SIMULTANIOUS SUBSTRACTION > using FPGA's. > > > its bit more complicated and, this substraction thing (and total > verilog code) is just a tool to prove it. > thats why i dont bother about the best, most cost efficient way of > doint it, as long as i can get results fast. > and the code i mentioned is just an example. the actual matrix is > maximum = 100 x 10, which allows me to do this in a real chip. > > and i dont mind waiting for 100 milliseconds for the calculation, as > the current calculation takes 3 seconds to complete. (this is using > direct convolution, without doing FFT). > > thank you. > Hi CMOS, who named this thread "substracting a whole array of values at once"? Why don't you tell us what your real problem is. Seems like my teasing was at least good for that purpose. So you have a big algorithm that needs 3 seconds on some hardware unknown to us, and you need to speed it up? Ok, tell us more. But instead you post tiny fractions of the problem and misleading questions. With my example I had no cost efficient solution in mind. Just an efficent one, and a practical one. You say milliseconds is ok if you see that part as a single operation, well if you split that operation into small pieces (like adressing the matrix) you can do these operations within nanoseconds (like 100MHz Clockrate). Both approaches may solve the problem in the same total amount of calculating time, but you have much less problems implementing the 100MHz approach. Give it a thougt and us better informations. Best regards EilertArticle: 115590
rponsard@gmail.com schrieb: > Hi groups, > > is there something special to get kcpsm3 running on linux/wine ? > > my wine conf seems ok (FileZila win edition is running fine) > but KCPSM3.EXE faills (Unhandled page fault on read access to > 0xffffffff...) > > any idea, > Hi, I also have a problem with kcpsm3, while kcpsm for spartan2 picoblaze runs fine under wine. I tried dosemu instead. (Version 1.2.2.0) It works. You have to start dosemu first and then enter the commands, or start a batch. Maybe newer versions do it better. Good luck EilertArticle: 115591
On Tue, 13 Feb 2007 18:41:00 +0100, Geronimo Stempovski <geronimo.stempovski@arcor.de> wrote: > Now I'm looking for a diagram like frequency (some MHz to 10 GHz for > example) versus loss tangent and / or epsilon R for FR4. I only found a > poor > black-and-white copy from 1991 in a paper which I searched with Google. I > wouldn't have thought it to be so hard to find a graph... Does anybody > know > where I can find that? Hello, I am sorry to tell that, but for frequencies of 1 to 10 GHz, FR4 ist not the right material, there are other PCB materials which are better for high frequencies, take a look here http://www.andus.de/Leiterplatten/Impedanz/hfmat.htm They write there that FR4 may be used up to 4 GHz. ByeArticle: 115592
ekavirsrikanth@gmail.com wrote: > hi, > > i am working on virtex 2 pro fpga i have a basic doubt > > 1. i am using bank 5 for my input and outputs. i have vref in the bank > which is not connected to supply(3.3v). my doubt is whether i should > connect it to the supply voltage. if i am not using the I/O of any > bank do i have to connect the VREF of that bank to the corresponidng > supply voltage or i can leave as unconnected. > if u connect one pin of vref to supply voltage is enough as the other > VREF are internally connected to each other. The Virtex 2 Pro datasheet is available online in pdf format. It has answers to your questions. In particular, it states that if you need to supply Vref, you must drive all the Vref pins in the bank. There are also tables that describe which IO standards require Vref as well as descriptions of the other pins from your original post. If, after reading the datasheet, you have additional questions, post them in this group. However, you should state what you have already read and why that information is not sufficient. That way, the replies can be specific to your question and not go over material that you already understand. --- Joe Samson Pixel VelocityArticle: 115593
On Wed, 14 Feb 2007 15:36:15 +0100, "Uwe Hercksen" <hercksen@mew.uni-erlangen.de> wrote: >On Tue, 13 Feb 2007 18:41:00 +0100, Geronimo Stempovski ><geronimo.stempovski@arcor.de> wrote: > >> Now I'm looking for a diagram like frequency (some MHz to 10 GHz for >> example) versus loss tangent and / or epsilon R for FR4. I only found a >> poor >> black-and-white copy from 1991 in a paper which I searched with Google. I >> wouldn't have thought it to be so hard to find a graph... Does anybody >> know >> where I can find that? > >Hello, > >I am sorry to tell that, but for frequencies of 1 to 10 GHz, FR4 ist not >the right material, there are other PCB materials which are better for >high frequencies, take a look here >http://www.andus.de/Leiterplatten/Impedanz/hfmat.htm >They write there that FR4 may be used up to 4 GHz. > >Bye FR4 can be used at 20 GHz, depending on what you're trying to do. JohnArticle: 115594
"CMOS" <manusha@millenniumit.com> wrote in message news:1171453059.474249.283780@v33g2000cwv.googlegroups.com... >> Great proof of concept. Brainless nonsense that is. > > im not trying to proove a concept regarding SIMULTANIOUS SUBSTRACTION > using FPGA's. > > > its bit more complicated and, this substraction thing (and total > verilog code) is just a tool to prove it. > thats why i dont bother about the best, most cost efficient way of > doint it, as long as i can get results fast. > and the code i mentioned is just an example. the actual matrix is > maximum = 100 x 10, which allows me to do this in a real chip. > > and i dont mind waiting for 100 milliseconds for the calculation, as > the current calculation takes 3 seconds to complete. (this is using > direct convolution, without doing FFT). So why don't you speed things up by using the fequency domain (or are you a troll)?Article: 115595
I have been unable to find a definitive answer for this in my searches. I would like to operated DDR2 SDRAM below its minimum specified clock rate, which is usually 125MHz (DDR250). I assume that the minimum clock rate specified has nothing to do with refreshing but has to do with the lowest rate at which the DRAM's DLL can lock. I am wondering if I can operate below the minimum rate if I turn off the DLL. As far as I can tell, the only purpose of the DLL is to ensure that the output DQS strobe and the data are aligned with the input clock, so if I don't care about that relationship I should be able to disable the DLL. Anybody know for sure? -KevinArticle: 115596
Hello , Several years ago when I designed my first PCI add -in card for a wintel platform I discovered that back to back CPU reads of the PCI card's memory address space did not get burst but instead where sent as two seperate frames. Each frame had only a single read. The result was that the CPU could only acheive a 6 Mbytes per sec read bandwidth vs 55 or so if the reads where burst. (32bit PCI bus @ 33 MHZ less overhead ) Now I am embarking on a PCI Express design. I would like to know if this has been corrected so that CPUs on wintel plarforms can do burst reads across the PCI Express bus. Thanks Dan,Article: 115597
Our design department basically split in the middle with half products were designed with Altera parts and half products were designed with Xilinx parts, when talking about choosing one main FPGA source, everyone voiced different opinions. I'm about to have a new design to process digital video signal which requires large external memory, either DIMM DDR/DDR2 SDRAM or component DDR/DDR2 SDRAM. First i go for Xilinx ISE9.1 webpack, quite large program, go to CoreGen, can't find place to generate memory controller, goto Xilinx and check MIG tool, nowhere to download MIG tool for ISE9.1. guess I have to use old tool, then import to ISE9.1 and tweak it by myself. downloaded Altera quartus6.1 webpack, go to megawizard, choose memory controller, then DDR SDRAM, right there, only thing I need is to customize it, looks like it's simpler so far, since I just get started, no sure the road ahead yet, but from the beginning, look like xilinx road is bumpy. I know if I get reference design of either one, It should get the job done, I want to listen to others out there, specially those who have experience on both, what are your thoughts about both companies in term of chip performance, development tool and supports, I'd like choose a company with overall better preformance, stick with it and forget the other oneArticle: 115598
Guys, I saw this from Steve Weir on SI-LIST and thought of you all! With special St. Valentine's love, Syms. xx http://www.teraspeed.com/publications.html (See! I _said_ a switcher works just fine!)Article: 115599
Joshua, thank you very much for these preciuos information. I'll try to convince my buying manager to get a E6700 with 4GB RAM and linux o.s. ... Best regards, llandre
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