Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi All, I want to use the flash on the P160 module, but I have to set the OPB EMC(External Memory Controller) for flash controller. Then how to set it? Does anyone have related materials about how to use it? Thank you very much! LinaArticle: 89476
As others have posted, there is a Cyclone II device with an LE count close to that of the APEX 20KE device you are using, and that's probably your best bet. If you use Cyclone I, the 1C6 device has ~6,000 LEs, while the 1C12 has approximately 12,000 LEs, so you'll have to pick between those two. Cyclone I and II each fit about 11% more logic than APEX 20KE per logic cell. So the 2C8 actually has more logic capacity than the 20K200E -- the 2C8 has the equivalent of over 9,000 APEX LEs. The reason is that the routing and multiplexers between the LUT and FF in the logic cell were redesigned between APEX and Stratix / Cyclone, and this redesign lets us use both the LUT and FF in a logic cell simultaneously more often than we could in the APEX FPGAs. The net impact is fewer LEs per design, and the last result I saw showed that we needed 11% fewer LEs in Cyclone than APEX, on average. In terms of speed, Cyclone and Cyclone II are much faster than APEX 20KE. Cyclone is approximately 50% faster than APEX 20KE, and Cyclone II is approximately 70% faster than APEX 20KE, again on average. So if you can close timing in a 20KE, it'll be very easy (generally trivial) to close in Cyclone. As well, if you're bringing data in at a high rate on I/Os and widening your internal datapath so the FPGA fabric can process it at a slower rate, the higher speed of Cyclone I/II mean you can probably run your datapath narrower and faster. If you can do this, it saves LEs, and lets you go down to a smaller device. So basically Cyclone I or II is a better choice than APEX for modern designs. Vaughn Altera [v b e t z (at) altera.com] "HamishR" <h.rawnsley@gmail.com> wrote in message news:1126760594.019460.259480@g43g2000cwa.googlegroups.com... > If you are not using the full resources of the APEX device then you > will hopefully fit your design into a EP2C8 (8256 LEs). You should > actually get better fitting with these newer devices due to more > advanced routing. These have embedded multipliers too so if you use > multiplication you'll save a ton of space. > > Hamish > > > htoerrin wrote: >> Eithout knowing anything about your application,... >> >> I believe that if you managed to run things in a 20KE, you will >> definetly be able to run it in a CycloneII. My experience is that >> CycloneII is more powerful than 20KE, although not as powerful as the >> Stratix families. But as long as you don't intend to actively use the >> DSP blocks, the large RAM's and lots of clocks, CycloneII will do the >> job. >> >> Havard >Article: 89477
DerekSimmons@FrontierNet.net wrote: > About a year and a half ago I came across a book on digital systems > design that I liked. I can't remember the title or the authors but in > one of the last chapters it had an example of JPEG/MPEG codec. I didn't > buy it because I was short on cash at the time, I think it was $130.00. > Does anybody recognize the book I'm looking for? > > Thanks in advance, > Derek A guy named Richardson had a book that had sections on both JPEG and MPEG. Good luck, DaveArticle: 89478
Udo schrieb: > Hello, > > I'm looking for small memory modules with > - SRAMs (normal and fast) > - FLASH > - DRAMs > which I want to use for tests with my FPGA-board. What's wrong with DIMMs for SRAM and DRAM and compact flash for FLASH? Kolja SulimmaArticle: 89479
Jim Granville wrote: > they call me frenchy wrote: > >> On 15 Sep 2005 10:35:32 +0200, David Brown >> <david@westcontrol.removethisbit.com> wrote: >> >>> Unless you have complex timing requirements, a small micro would be >>> the best for making 3 PWMs. Get a small msp430 processor - they are >>> cheap, easy to work with, and have good free tools (the gcc port is >>> excellent, and there are free versions of ImageCraft and IAR tools >>> for limited program sizes). >> >> >> >> >> David, >> Thank you very much for your response. I am new to programmable logic >> and I really appreciate the suggestion. Just to make sure that I >> paint the entire picture, here are my full requirements... >> >> 1) 3independent PWM generators running at the same frequency. I am >> starting with 8-bit, but I could justify going down to 7bit and >> maaaaaaybe 6 or even 5 bit if it will save me much grief. >> >> 2) The FSM will probably have 8 states (cylcled through with a simple >> pushbutton, no reset). State 1 will tell PWM1 to run at 90% and PWM2 >> and 3 to be off. The rest of the states will turn the PWMs off and on >> in a variety of ways. The most complex of the states will tell all 3 >> PWMs to cylce from 10% to 90% out of phase from each other at about >> 0.5Hz. I do not have complex timing requirements. >> >> 3) I would like to detect the battery voltage and when it is running >> semi low, I would like to scale down the values of ALL PWM signals to >> extend battery life. For example, full battery = all PWMs @ 100%, >> battery 1/2 dead = all PWMs @ 50%, battery pretty much dead = sleep >> mode until the batteries start to receive a recharge, which could be >> several hours away. >> >> I got a Coolrunner II development kit just to get going with a >> 256macrocell chip onboard. I will plan on testing my functionality on >> that even if I fill the whole damn thing and then perhaps migrate to >> your recommended MSP430 after some research to prove why that would >> indeed be better than a CPLD. >> >> My application is geared towards a very high quantity consumer part, >> so I would like to see the chip cost under US$1 at quantity. I know >> that I have an uphill climb in front of me and my boots are on. > > > This does not sound like a CPLD problem. A fundamental determinant in > cost is pin count, and there are no 8 or 14 pin CPLDs. > CPLDs also have narrow Vcc tolerance, and in some cases, need Two supplies. > You will also find the 10-20uA the CPLD vendors boast of, is MUCH higher > than the Static Icc of Microcontrollers. There are no CPLDs with low > power on-chip oscillators... > > You have not mentioned the PWM frequency, but the usage and action > sounds like a lighting effects one, so you do not need the 300Mhz clock > rates of a CPLD. > > Do a pin-count budget, and then choose a 8 pin or 14 pin > Microcontroller. [I'd start with 14, and then see if it will fit in 8, > when you are all done] > > For 8 & 14 pin Microcontrollers, look at > Atmel, Freescale, Microchip, Philips, ST, TI, Zilog (etc) > > This application will move across uC quite easily, so choose the > one that looks easiest for you to learn, and get it working on that, > then start the bidding process, when it hits real volume :) > > >> If I indeed switch over to a MSP430, will my VHDL code that I am >> writing now be able to come with me? > > > NO, but the ideas will. > Additionally, if you want to measure battery voltage, you'll need some sort of ADC. There are lots of small micros with an ADC, whereas with a CPLD you'd need an external ADC. I think Atmel have some new AVR chips aimed specifically at lighting applications, with very flexible PWM outputs. I don't know the details, but they'd be worth a look. Your software is going to be vastly easier to write and test in C on a microcontroller, rather than VHDL on a CPLD.Article: 89480
Paul Urbanus <urbpublic@hotmail.com> writes: > Mike Treseler wrote: > > Paul Urbanus wrote: > > > >> I have an FPGA design where the VHDL source code is a deliverable > >> item to the customer. One of the blocks in the FPGA must be > >> protected so that the customer can't see the source and modify it. > > Either source code is a deliverable or it isn't. > > Unreadable source code is useless so why > > bother creating it. > > -- Mike Treseler > > The idea isn't to deliver source code. Instead, the idea is to deliver > a netlist file which is generated by compiling the source code. The > block in question is implemented using proprietary info > > M NDA (with a chip manufacturer) states that this proprietary info > must be protected. Therefore, any code which utilizes this proprietary > info can't be redistributed in source form. So if I delivered a > synthesisized netlist I must make sure that the net names are > obfuscated, at a minimum. This can be achieved at either the source or > netlist level. > I'd fudge the netlist with a script that renames all the nets and component instances. Would that be enough? I seem to recall that at one point Nios was source code with all the nets named as long random combinations of 1lI0O, which was kind of weird to look at! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 89481
>FOR SOLUTION-2 that > Websites to Get economical chips of SDRAM nad VRAM Easiest way to get chips would be to strip them off a module >FOR SOLUTION-3 that > Links Where to get SSDRAM Socket.... > Suggestion to do it on Single sided PCB... Digikey stock a range of sockets. For a standard Unbuffered SDRAM, the part number is WM1712-NDArticle: 89482
>FOR SOLUTION-1 that > Websites to Get economical FPGA or Extention boards having >SDRAM Socket in it (I m using VHDl and FPGA of Xilinx (any)) This low-cost board has 32mbytes of SDRAM onboard : http://www.xess.com/prod034.php3Article: 89483
I've just started looking into getting our VHDL code into some sort of version control tool, and would like to get some information about which ones work best with VHDL & FPGA tools. All our designs are done using Actel Libero, and AFAIK it doesn't provide any helpful features for version control. I have previously used SourceSafe for a little while, but since we are just a small company I think the cost is a bit much. Our software team currently use PVCS, has anyone had any experience using this with VHDL?Article: 89484
I am using ISE 7.1 on linux Redhat Enterprise 3.0, During translate phase of design, ngdbuild fails, but there is no error reported. It just gives a message that ngdbuild failed. If I run translate again, it works fine. What may be the reason ?? AshokArticle: 89485
I have to say that version control is pretty much orthogonal to what programming language you're using, so long as you keep your programs in text files that are broken into lines separated by carriage returns (or line-feeds). That in mind, I _emphatically_ recommend darcs. http://abridgegame.org/darcs/ It won't coddle you with a GUI, but it has a higher power-to-simplicity ratio than basically every other piece of software I use on a daily basis. Actually there probably are GUIs for it if that's what you want. One killer feature is that it understands search-and-replace on tokens, so if one person changes a line of code and another person does a search-and-replace affecting a different part of the same line, darcs will merge the two changes correctly without human intervention. The other killer feature is that making and merging branches is really, really easy to understand -- unlike a lot of other systems where it's complex or hairy enough that people tend to never learn about it. There's no client/server (or repository/workspace) distinction in darcs; it's all peer-based. So to make a branch, you just "check out" a copy and use that copy as the branch. Your branches are directly visible in the filesystem as separate copies of the repository, so you can manage/view/browse/script them just like any other directory or file. - a "Neill A" <neilla@ewst.co.uk> writes: > I've just started looking into getting our VHDL code into some sort of > version control tool, and would like to get some information about > which ones work best with VHDL & FPGA tools. > > All our designs are done using Actel Libero, and AFAIK it doesn't > provide any helpful features for version control. I have previously > used SourceSafe for a little while, but since we are just a small > company I think the cost is a bit much. > > Our software team currently use PVCS, has anyone had any experience > using this with VHDL? > -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 89486
I have a question that is more theoretical than practical: The DCM uses the feedback loop so that it can create a 360 (= 0) degree phaseshift from CLKIN to CLK0, CLK90 etc. (or that is how I understood it) But why is this loop nessecary to create this behaviour? I know it's a bit vague, but I didn't find to much detailed info on it... Can someone please explain me the working of this system, or give me a link to a place on the net where I can find it? I have the standard VirtexII-Pro manual, but it doesn't say much about the whole system itself...Article: 89487
zoinks@mytrashmail.com wrote: > I have a question that is more theoretical than practical: > > The DCM uses the feedback loop so that it can create a 360 (= 0) degree > phaseshift from CLKIN to CLK0, CLK90 etc. (or that is how I understood > it) > > But why is this loop nessecary to create this behaviour? > > I know it's a bit vague, but I didn't find to much detailed info on > it... > > Can someone please explain me the working of this system, or give me a > link to a place on the net where I can find it? > > I have the standard VirtexII-Pro manual, but it doesn't say much about > the whole system itself... > Maybe that´s what you want... http://klabs.org/richcontent/Tutorial/MiniCourses/fsm_gsfc_march_2003/12_dll.ppt It is "only" a presentation, but very completeArticle: 89488
hi all, i am using a development board from Avnet featuring a Spartan 3. I am trying to download a bitstream to the board over the parallel port by using the EDK programmer provided by Xilinx. Even though it recognises the LPT port and the programming mode is set correctly (boundary scan mode), i get an error report that the cable connection fails. btw, I am using a laptop for programming the fpga. I don't know what is wrong. anybody got any ideas? thanks in advance!Article: 89489
"Paul Urbanus" <urbpublic@hotmail.com> wrote in message
news:4328ca81$1_6@news.uncensored-news.com...
> I have an FPGA design where the VHDL source code is a deliverable item
> to the customer. One of the blocks in the FPGA must be protected so that
> the customer can't see the source and modify it. The device is a
> Virtex2-Pro.
>
> I could obfuscate the VHDL identifiers, then generate a netlist, but
> that doesn't seem to be very strong protection. I also have a picoblaze
> processor in the design, so I'm not sure how well I can obfuscate the
> block RAM contents. I could swizzle the address/data bits (as the TOCOM
> 5507VIP cable box did) when hooking up the block rom to picoblaze, then
> write a script to convert the picoblaze object code to swizzled ROM init
> files.
>
> I heard a rumor (from a Xilinx FAE) that ISE 7 would have some facility
> for protecting blocks of code in situations such as this, but I haven't
> been able to find any info on the Xilinx website about this.
>
> Peter Alfke, I know you have the answer :)
>
> TIA
>
> Urb
>
Hi,
Only deliver the component declaration with the VHDL code and provide the
.ngo/.ngd encrypted netlist with it as well. In this case, the NGDBUILD
phase during synthesis will put your IP in place while protecting your
source code. Similarly, you might have to provide an encrypted file to allow
for simulation (depends on the customer's simulation tool). The main
disadvantage is that you're responsible for selecting the device and and
supported speed.
So to wrap up:
split the task into 2 "projects"
A) The protected IP:
1) code, test and so on
2) constrain (if you want to deliver a netlist)
3) generate the encrypted files
B) The main code
1) set up libraries and so on to invoke the encrypted blocks
2) use the component of the protected IP (don't include the source code)
3) code, test and so on
4) deliverables = encrypted files + readable project code
Most fun will be in looking in how to do the encryption for the various
tools.
Kind regards,
Alvin.
Article: 89490zoinks@mytrashmail.com wrote: > I have a question that is more theoretical than practical: > > The DCM uses the feedback loop so that it can create a 360 (= 0) degree > phaseshift from CLKIN to CLK0, CLK90 etc. (or that is how I understood > it) > > But why is this loop nessecary to create this behaviour? In case this is a homework problem, I'll pose a series of leading question to you: What does the DCM do with the feedback path? How else could you create a zero phase shift from CLKIN to CLK0 without using feedback? For what reasons would an implementation without feedback _sometimes_ produce zero phase shift? MarcArticle: 89491
Hallo, I have made a opb peripheral which generates some interrupts: 0001 0010 0011 0100 ...... until 1111 Every interrupt is high for 1 clock cycle. The trouble semes to be with xilinx interrupt handling. It does not recognize any interrupt. I have configured microblaze and the peripheral interrupt edge sensitive. But the software variable IntrStatus is always equal to 0. Many Thanks MarcoArticle: 89492
Sleep Mode wrote: > hi all, > > i am using a development board from Avnet featuring a Spartan 3. > > I am trying to download a bitstream to the board over the parallel port by > using the EDK programmer provided by Xilinx. > > Even though it recognises the LPT port and the programming mode is set > correctly (boundary scan mode), > i get an error report that the cable connection fails. > > btw, I am using a laptop for programming the fpga. > > I don't know what is wrong. > > anybody got any ideas? > > > thanks in advance! > > Could you send here the excat message you receive?Article: 89493
zoinks@mytrashmail.com wrote: > I have a question that is more theoretical than practical: > > The DCM uses the feedback loop so that it can create a 360 (= 0) degree > phaseshift from CLKIN to CLK0, CLK90 etc. (or that is how I understood > it) > > But why is this loop nessecary to create this behaviour? <snip> How else would the silicon know what 360 degrees is versus 300 or 450 degrees? If you want a continuous, stable output to look like the input to the DCM, the phase shift has to be precisely a multiple of 360 degrees. That's 360 degrees for the input to the output - the two need to be compared.Article: 89494
When it tries to connect, I get the following message (with autodetection enabled): ----- AutoDetecting cable. Please wait. Connecting to cable (USB Port). Cable connection failed. Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0. LPT base address = 0378h. ECP base address = 0778h. Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. Connecting to cable (Parallel Port - LPT3). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. Connecting to cable (Parallel Port - LPT4). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. Connecting to cable (Usb Port - USB21). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. ----- (thanx again) "Zara" <yozara@terra.es> wrote in message news:432AC1C0.9040504@terra.es... > Sleep Mode wrote: >> hi all, >> >> i am using a development board from Avnet featuring a Spartan 3. >> >> I am trying to download a bitstream to the board over the parallel port >> by >> using the EDK programmer provided by Xilinx. >> >> Even though it recognises the LPT port and the programming mode is set >> correctly (boundary scan mode), >> i get an error report that the cable connection fails. >> >> btw, I am using a laptop for programming the fpga. >> >> I don't know what is wrong. >> >> anybody got any ideas? >> >> >> thanks in advance! >> >> > Could you send here the excat message you receive? >Article: 89495
Sleep Mode wrote: > When it tries to connect, I get the following message (with autodetection > enabled): > ----- > AutoDetecting cable. Please wait. > Connecting to cable (USB Port). > Cable connection failed. > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Driver windrvr6.sys version = 6.0.3.0. LPT base address = 0378h. > ECP base address = 0778h. > Cable connection failed. > Connecting to cable (Parallel Port - LPT2). > Checking cable driver. > Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. > Connecting to cable (Parallel Port - LPT3). > Checking cable driver. > Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. > Connecting to cable (Parallel Port - LPT4). > Checking cable driver. > Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. > ----- This listing only tells us that it has located there is a free, real, parallel port at 0378h/0778h but it has been unable to locate any cable in it. It seesm your cable is not working at all, or is not connected to LPT2. If it is a Xilinx ParallelCable IV, you must connect it to PS/2 port or an external power source to have it working. Have you tested if the led on the pod lights? If it is a parllel cable III, then it is not connected at all. Check connections and everything. A connection OK shows the message "Cable connection established" And I have used a parallel Cable IV form a laptop, no problems. But I don´t know if a parallel Cable III might work in such case. Good luckArticle: 89496
Ok ... But what about the dynamic property of the routing. Is the PAR tool wil cnsider all the possibilites that may arise only at working time. Kolja are you suggesting a manual duplication or the method suggested by the Muravin.Article: 89497
Hello Zara. We have a ParallelCable IV but it seems that the "STATUS" led is not lighted at all. Could it be the problem? Moreover, there is no PS2 port since the board is connected to a laptop. Any ideas why ?? Thank you! Yannis "Zara" <yozara@terra.es> wrote in message news:432AD164.1030206@terra.es... > Sleep Mode wrote: >> When it tries to connect, I get the following message (with autodetection >> enabled): >> ----- >> AutoDetecting cable. Please wait. >> Connecting to cable (USB Port). >> Cable connection failed. >> Connecting to cable (Parallel Port - LPT1). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0. LPT base address = 0378h. >> ECP base address = 0778h. >> Cable connection failed. >> Connecting to cable (Parallel Port - LPT2). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> Connecting to cable (Parallel Port - LPT3). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> Connecting to cable (Parallel Port - LPT4). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> Connecting to cable (Usb Port - USB21). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> ----- > > This listing only tells us that it has located there is a free, real, > parallel port at 0378h/0778h but it has been unable to locate any cable > in it. > > It seesm your cable is not working at all, or is not connected to LPT2. > If it is a Xilinx ParallelCable IV, you must connect it to PS/2 port or > an external power source to have it working. Have you tested if the led > on the pod lights? > If it is a parllel cable III, then it is not connected at all. > > Check connections and everything. > A connection OK shows the message > "Cable connection established" > > And I have used a parallel Cable IV form a laptop, no problems. But I > don?t know if a parallel Cable III might work in such case. > > Good luckArticle: 89498
Hello Zara. We have a ParallelCable IV but it seems that the "STATUS" led is not lighted at all. Could it be the problem? Moreover, there is no PS2 port since the board is connected to a laptop. Any ideas why ?? Thank you! Yannis "Zara" <yozara@terra.es> wrote in message news:432AD164.1030206@terra.es... > Sleep Mode wrote: >> When it tries to connect, I get the following message (with autodetection >> enabled): >> ----- >> AutoDetecting cable. Please wait. >> Connecting to cable (USB Port). >> Cable connection failed. >> Connecting to cable (Parallel Port - LPT1). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0. LPT base address = 0378h. >> ECP base address = 0778h. >> Cable connection failed. >> Connecting to cable (Parallel Port - LPT2). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> Connecting to cable (Parallel Port - LPT3). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> Connecting to cable (Parallel Port - LPT4). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> Connecting to cable (Usb Port - USB21). >> Checking cable driver. >> Driver windrvr6.sys version = 6.0.3.0.Cable connection failed. >> ----- > > This listing only tells us that it has located there is a free, real, > parallel port at 0378h/0778h but it has been unable to locate any cable > in it. > > It seesm your cable is not working at all, or is not connected to LPT2. > If it is a Xilinx ParallelCable IV, you must connect it to PS/2 port or > an external power source to have it working. Have you tested if the led > on the pod lights? > If it is a parllel cable III, then it is not connected at all. > > Check connections and everything. > A connection OK shows the message > "Cable connection established" > > And I have used a parallel Cable IV form a laptop, no problems. But I > don?t know if a parallel Cable III might work in such case. > > Good luckArticle: 89499
Hi, 1. I dont know of any extention boards for DDR. I also don't know of any cheap development kits for DDR. Xilinx DDR Development ML361 cost around $2,500 (http://www.hitechglobal.com/xilinx/ml361.htm). 2. no clue here. 3.) I think you are looking for DIMM Socket Connectors - http://www.mouser.com/index.cfm?handler=displayproduct&lstdispproductid=633171&e_categoryid=619&e_pcodeid=82902 I think #3 would be very hard. If you have time and lots money I would do this (in fact I am for my Masters Project, but I am doing DDR2 with this board - http://www.hitechglobal.com/ted/virtex4ddr.htm). Building your own board is hard, requires board design skills, more importantly board design software. My best advice is go with number 1. Much easier. Good luck. I wish you the best. -Tony
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z