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Telenochek wrote:
> I was wondering if anyone has any recommendations for software that is
> designed for drawing architectural level diagrams or block diagrams for
> hardware design.
Unless there is a paying audience for a design review,
I just use a pen and notebook to block things out
then get on with the design and simulation work.
Most synthesis tools can draw block diagrams for
you once the top entities/modules are complete.
> Also does anyone know what software tools are used to draw the timing
> diagrams in various datasheets?
See: http://www.chronology.com/
But consider getting a working simulation before
handing out data sheets.
-- Mike Treseler
Article: 89526I'v got a couple of these boards in my basement, but very limited documantation and no demo projects. They were made by Insight in 2001 (I think) and featured a XC2S100PQ208. They also have a large, 2 digit, 7-segment display. The default behaviour is to display a count on power-up. I can't find any demo projects / UCF's for this. If anybody could point me in the right direction or send me the design files that would save me a couple of hours. ThanksArticle: 89527
> Unless there is a paying audience for a design review, > I just use a pen and notebook to block things out > then get on with the design and simulation work. Yes I did a lot of that. I am trying to get away from it as much as possible, paying audience or not. If you do the diagram on a computer, its already documented. Then its easy to change the design, keep track of versions, copy one block to another design, reuse your blocks. Major time saver even with a moderately user-friendly program. > Most synthesis tools can draw block diagrams for > you once the top entities/modules are complete. Yes, but the idea is to have a block diagram before touching VHDL/Verilog. Thanks for the TimingDesigner link! (No, I am not actually designing a datasheet, I am designing multithreaded process)Article: 89528
logjam wrote: > In fact all I found were > testimonials about Apple using PALs to slow down people copying their > computers. This can only slow down someone who copies blindly not knowing what the hardware does. You can copy an Apple ][ this way, but not //e due to LSI chips. However since it is well known what exactly the hardware is supposed to do, an engineer wouldn't have any trouble making a circuit to do it. Either using programmable logic or a bunch of off-the-shelf TTL chips. I guess I can say I know what I'm talking about: I did a clone of Apple 2 in a single FPGA chip for fun. Only took a couple of days. Of course I have access to design tools that are a far cry from what was hot in 1980. http://www.mirrow.com/FPGApple > tests. Would the program you suggest I write already have a hint of > what the PAL does and test for input sequences that make sense for THAT > PAL? There are PAL/HAL chips with no registers. Those are trivial to figure out. Now a chip like 16R8 has 8 registers. Let's assume all 8 outputs are used. The output after a clock pulse depends on 8 input signals and 8 current outputs that represent the internal state. The most brute force approach I can think of: Suppose you feed random numbers to the inputs till you get all possible 256 output states. Remember the input sequence to get to each state. From each of 256 states apply 256 different inputs and a clock. You have ALL the possible combinations. Now it is a simple matter of math to figure out which inputs cause a change to which outputs etc. -Alex.Article: 89529
Hallo, I'm trying to create a template with dma support using Xilinx tool "Create/Import Peripheral Wizard". When I open the file user_logic.vhd there aren't dma support signals. Instead driver files are created correctly. Has someone had the same problem? Many Thanks MarcoArticle: 89530
Philip Freidin wrote: > The other big problem for the Anti-Fuse folks is that they have a > hard time getting the attention of the high volume leading edge > foundaries. They end up at second tier foundaries that are willing to > do the special stuff for Anti-fuse, but then the usually do not yet > have the leading process node available. Is UMC considered a second tier foundry? I note that Xilinx builds devices there. -- rk, Just an OldEngineer and not a process guy. "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, WestworldArticle: 89531
rk, Yes, UMC is a nice little foundry. We have some wafers running there. Seriously, a foundry is not just one process, or one line, but many. At the 12" location of UMC, Tainan, in the south of Taiwan, there is a whole lot of advanced process node production going on. Most, perhaps all, of their capital budget is spent on these processes. It isn't so much your choice of foundry (I think UMC is a great choice), but it is also your choice (if you have a choice) of process. AustinArticle: 89532
Hello, The following is said in the documentation of Xilinx ISE (in the following place for ISE users: <Xilinx Istallation path>/doc/usenglish/help/iseguide/iseguide.htm#html/fd_inst_bram_vhdl.htm): The following VHDL code demonstrates how to infer a Dual Port BlockRAM component for Virtex™ devices when synthesizing with XST. Only XST supports RAM inference. entity dpblockram is port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(4 downto 0); dpra : in std_logic_vector(4 downto 0); di : in std_logic_vector(3 downto 0); spo : out std_logic_vector(3 downto 0); dpo : out std_logic_vector(3 downto 0)); end dpblockram; architecture syn of dpblockram is type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(4 downto 0); signal read_dpra : std_logic_vector(4 downto 0); begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(a)) <= di; end if; read_a <= a; read_dpra <= dpra; end if; end process; spo <= RAM(conv_integer(read_a)); dpo <= RAM(conv_integer(read_dpra)); end syn; ******************************************************* I have used this initialization method of array of std_logic_vector in trying to use the FPGA's BRAMs when designing a processor in VHDL, but I got the following info warning (which indicates that BRAMs are not used): INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal <memory>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. Any help on how to use Block RAMs in VHDL??Article: 89533
I think I can shed light on why the ISE 7.1 installer might not accept a valid install code under Linux. With 7.1, the ISIM simulator is not available under Linux. If you try to install using a code for ISE + ISIM under linux, then the installer will reject it. Use a straight Foundation install code without ISIM, and it should work just fine. I can also testify that it can be easier to install ISE on an older distribution (like RHEL3 or FC1) and then copy it to a newer distribution. John On Tue, 13 Sep 2005 19:51:37 +0000, Ram wrote: > Hi Josh, > > B. Joshua Rosen wrote: > >> The Xilinx installer is very distribution sensitive although the tools >> aren't. I keep Whitebox Linux 3 (RHEL3) on one of my older machines and do >> by Xilinx installs there, once the install is done I rsync the Xilinx >> directory to by other machines. > > Yes, seems like it! > > Which directories do you end up having to rsync? Just one installation > directory? > > I might go this route if I have to. > > Thanks, > Ram.Article: 89534
austin wrote: > rk, > > Yes, UMC is a nice little foundry. We have some wafers running there. > > Seriously, a foundry is not just one process, or one line, but many. > > At the 12" location of UMC, Tainan, in the south of Taiwan, there is a > whole lot of advanced process node production going on. Most, perhaps > all, of their capital budget is spent on these processes. > > It isn't so much your choice of foundry (I think UMC is a great choice), > but it is also your choice (if you have a choice) of process. Agreed, of course, was just commenting on the one point that Philip brought up. What you described is of course true at many foundries, nothing new, and not all designs call for the most modern deep submicron process. Philip Freidin wrote: > The other big problem for the Anti-Fuse folks is that they have a > hard time getting the attention of the high volume leading edge > foundaries. They end up at second tier foundaries that are willing to > do the special stuff for Anti-fuse, but then the usually do not yet > have the leading process node available. Is UMC considered a second tier foundry? I note that Xilinx builds devices there. -- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, WestworldArticle: 89535
You can do this very easily for the cost of $595 US. Just buy a Xilinx ML-403 board, and a couple of 32x3 .100" connectors to get the data in and out of the board. The XC4VSX35 fpga on the card has 192 hardware multipliers and adders, arranged in 2 columns of 96 each. One column should suffice for your requirements, and it will run as a 96 tap FIR filter at 400 MHz. Getting data in & out at 400 MHz would probably require using LVDS, but 105 MHz should be relatively easy using CMOS 3.3V or other single ended signaling. You'll probably spend more time getting the IO timing right than on the FIR filter, which can be generated as a monolithic core by the Coregen tool. You really don't want to use the MAC FIR, by the way. Just a standard FIR will work fine. John The ISE 7.1 coregen On Tue, 13 Sep 2005 19:17:03 -0500, seb_tech_fr wrote: > Hi everybody, > I'm working on a small project in which we want basically to filter > Input data (Input Data Rate = 105Mhz) with a FIR filter (64 > coefficients). > I've forseen to use the MAC FIR IP provided by Xilinx but there could > be a problem in the way input data are sampled. > > Indeed, MAC FIR IP provides an output named RFD(Ready For Data) which > indicates when the MAC FIR can accept new data. > > Does that mean ND (New Data signal) can't be stay at '1' to put new > data in FIR at each rising edge of clock sample (105 MHz)? > > Since my Input data flow is unbroken, how can I do to process this > flow in real time? > > Is there other free FIR IP more suitable for my application? > > Thank you in advance for your answers. > > > PS: I'm a french guy, so I hope my english is not too bad and you will > able to understand what I mean ... :oops:Article: 89536
> That's consistent with what I've seen. Note the 4000+ has a 1M cache which > is critical for the performance of EDA codes. For NCVerilog I've found > that when recordvars is off there is a 2 to 1 difference between an A64 > with a 1M cache vs one with a 1/2M cache. I now have a 4400+ in addition > to the 3400+ and the 3800+ shown on this page, > > http://www.polybus.com/linux_hardware/index.htm Interesting! Your experience seems consistent with relatively small, RTL (behavioral) designs. For SOC/ASIC designs of any reasonable size, I've found the difference between 0.5MB and 1MB cache to be non-existent (because the working data-set already exceeds larger cache.) I think one problem is the difficulty in producing publishable benchmarks. In the case of NC-Verilog and even Verilog-XL, I've found benchmarks almost useless. It's easy to find a 'test case' which runs 30-40% faster on a puny Pentium3/S 1.26GHz (512K L2 cache) than on a Ultrasparc III 750MHz (Linux 32-bit vs Solaris 32-bit.) And likewise, it's just as easy to find a 2nd RTL test-case where the USIII literally crushes the Pentium3 (2X as fast.) For SDF backannotated gate-level simulations, the results even out, with the US3 marginally faster than the Pentium3. And the US3 has an 8MB CPU cache (don't remember whether it's L2 or L3), so it looks like the pace of design-database 'bloat' already outpaces CPU cache-size improvements. In the case of Design-Compiler and Primetime, there seems to be less variation in runtimes (for a given design compared on 2 different platforms.) The almost all of the customer Verilog RTL designs I've crunched through DC, Primetime, and Tetramax, the wimpy Pentium3 1.25GHz outperforms the Ultrasparc III 750MHz. I'd suspect Xilinx's PAR shares a performance profile similar to Design Compiler. Incidentally, we've found the Athlon64 gets a +20-30% performance boost from 64-bit linux versions of EDA-tools (vs 32-bit linux.) This was our conclusion after re-running quite a few Verilog simulation and synthesis- jobs. It's curious to see the Intel EM64T CPUs take a small performance hit in the same 64-bit linux apps! Aside from the small increase in RAM footprint, the 64-bit EDA tools on Athlon/64 always comes out ahead. > I haven't updated my benchmark page with the the 4400+ results but they > are consistent with the other results. The 4400+ is about 10% faster then > the 3400+ on single threaded jobs like NC or Xilinx place and results > which is exactly what you would given that each core in the 4400+ runs at > the same clock speed and has the same cache size (1M) as the 3400+ but it > has dual memory channels vs a single channel on the 3400+. Looks like I'll need to rethink my upgrade plans. Originally I planned on 'cheapskating' on a system-upgrade (AMD dual-core X2 3800+, 2.0GHz, 512K), but it seems FPGA-tools benefit quite abit from the extra 512K cache.Article: 89537
Hello, as a totally newbie I asked my question about FPGA-Board one week ago, I am very glad that I got so much help from you, finally I know which type is suitable for our project, and we are going to start it. But there is a new problem with this job. As I said, we want to transfer the data from FPGA to the PC via USB-Interface, could we get a dll-device(API) for it somewhere? If not, we have to program it by ourselves, because I have no expericences with programming for usb, could someone give me some tips about how to start this kind of programming? Best regards, Le P.S: 1. The module, we want to use: http://shop.trenz-electronic.de/catalog/product_info.php?products_id=43&language=en 2. My last post: http://groups.google.de/group/comp.arch.fpga/browse_thread/thread/ae65e4f3ad7940ca/601516aef47cb9fe?q=Le+Wang&rnum=1&hl=de#601516aef47cb9feArticle: 89538
I'm becomming a little unhappy with the quality of some of the images,
there are about 3 fuses I can't quite make out. Having a microscope
HERE would help, I'd just 400x zoom instead of 200 and figure out whats
going on.
I've transcribed all 2048 bits, and I'm almost ready to make some GALs.
Regarding the order of the columns, I find it strange that IF they
didn't use the same column order from the data sheet that they would
keep the pattern going per pin. For example, what should be the fuse
map block for Pin #2 is actually #3. The inverting/noninverting inputs
and flip flop returns match what should be for pin 3, but are in the
spot next to pin 2.
I've found a pattern: (this needs to be viewed with a fixed font to
look good)
Fuse Block #: Fuse Indicated Pin #: Assumed Pin #:
1 3 2
2 2 3
3 5 4
4 4 5
5 7 6
6 6 7
7 9 8
8 8 9
That's a pattern IMO, and I think its worth reassembling the jedc file
assuming that the fuse blocks are not in order, but that the columns
are in the proper order.
What do you think?
Grant
Article: 89539If interested, here is the complete fuse map in one image: High Res: 20.3MP, 2.2MB http://media.diywelder.com/images3/091705-ASG-fuseblock-pano-fullres-cropped.jpg Low Res: 5MP, 800k http://media.diywelder.com/images3/091705-ASG-fuseblock-pano-fullres-cropped-halfsize.jpgArticle: 89540
logjam wrote: > I'm becomming a little unhappy with the quality of some of the images, > there are about 3 fuses I can't quite make out. Having a microscope > HERE would help, I'd just 400x zoom instead of 200 and figure out whats > going on. > > I've transcribed all 2048 bits, and I'm almost ready to make some GALs. > > Regarding the order of the columns, I find it strange that IF they > didn't use the same column order from the data sheet that they would > keep the pattern going per pin. For example, what should be the fuse > map block for Pin #2 is actually #3. The inverting/noninverting inputs > and flip flop returns match what should be for pin 3, but are in the > spot next to pin 2. > > I've found a pattern: (this needs to be viewed with a fixed font to > look good) > > Fuse Block #: Fuse Indicated Pin #: Assumed Pin #: > 1 3 2 > 2 2 3 > 3 5 4 > 4 4 5 > 5 7 6 > 6 6 7 > 7 9 8 > 8 8 9 > > That's a pattern IMO, and I think its worth reassembling the jedc file > assuming that the fuse blocks are not in order, but that the columns > are in the proper order. > > What do you think? Don't forget you can run Test Vectors, to compare your new GAL, with these devices [you do still have one that works ?] so you do not need 100.00% reverse engineer coverage. For simple SW that will create GAL JEDEC Test Vectors, look at Atmel's WinCUPL, or ICT's WinPLACE http://www.anachip.com/eng/supports/resources.html Most programmers that can pgm GALs can also run these test vectors. Better ones can edit and save test vectors in the programmer. -jgArticle: 89541
Greetings.
The source package from Xilinx leaves a bit to be desired as far as
being easy to use and integrate into your Linux distro. I have uploaded
a patch that includes a 'README' file and simplifies building and
installing. I also wrote an init script that does the 'start|stop|reload'
type stuff that all the Linux distros do. This patch will work with the
Linux 2.6.13 vanilla kernel. It patches up all the source code such that
it builds with no warning or errors. I hope people find it useful. You
can download the patch from here:
ftp://ftp.realitydiluted.com/Xilinx/linuxdrivers-xilinx-2.6.13.patch
The README text is shown below to give you an idea of what I did. Cheers.
-Steve
**********
DIRECTIONS
----------
1) Go to the 'xpc4drvr' directory.
2) After locating your kernel tree, build the driver with:
make KERNEL_SOURCE=<kernel-source-dir>
or edit your Makefile and hardcode the value for KERNEL_SOURCE
and then build your module.
3) Become the 'root' user.
4) Install the device driver, with:
make KERNEL_VERSION=<kernel-version> install
or again, edit your Makefile and hardcode the KERNEL_VERSION value.
The init script 'install_drv' will also be copied to your '/etc/init.d'
directory and be renamed to '/etc/init.d/xilinx'. Edit the Makefile
to change this behavior.
QUESTIONS
---------
1) Ask on the 'comp.arch.fpga' newsgroup after actually trying the
above steps 2 times.
2) You can email me, Steven J. Hill <sjhill@realitydiluted.com> with
questions. I may or may not be able to help you.
Article: 89542Hi, I have generated libraries in ModelSim 6.1 that my company is going to be distributing shortly. We need to protect our source code, and I have a few concerns about the distribution. Currently, we plan on distributing the library in an installed directory, and the end users link this directory either at the command prompt or add it to the modelsim.ini file. Everything works great. My concern comes from data stored in the _info file for the library, namely project file names and locations to the original source code. Of course, the end users won't have this code, but it appears as dead links to our source code under the "Files" tab in Modelsim. So, basically, what sort of project settings or flags should I use to prepare my libraries? I just want as clean and secure of a distribution as possible and I can't find anything in Modelsim's documentation or on the web. Thanks for any advice or pointers, GarrickArticle: 89543
Terry Fowler ha escrito: > Thanks for your help. I have another observation I would like to confirm. It seems that the MSR[29] carry bit, used to determine if the fifo has data, is set by control reads and is not set by data reads. Tbis bit is used by a lot of instructions and as such is not "sticky" like the FSL_Error bit. Has that been your experience? I have never tried it with control reads, only with data reads, and it works.Article: 89544
Garrick wrote: > I have generated libraries in ModelSim 6.1 that my company is going to > be distributing shortly. > > We need to protect our source code, and I have a few concerns about the > distribution. > > Currently, we plan on distributing the library in an installed > directory, and the end users link this directory either at the command > prompt or add it to the modelsim.ini file. Everything works great. As a user of many protected codes, please use the new "vlog +protect" functionality. It is supported from Modelsim 5.7 onwards. It's much easier for the customers (for example name clases are easier to handle). And be prepared to offer many different versions of the library if you use precompiled libraries, because -refresh command works only from older to newer versions. Everyone is not using the newest and greatest versions of the simulator. For example I don't like the new 6.x GUI and in many designs 5.8 is faster and consumes less memory. > So, basically, what sort of project settings or flags should I use to > prepare my libraries? I just want as clean and secure of a distribution > as possible and I can't find anything in Modelsim's documentation or on > the web. -nodebug and +protect are documented quite well in the manuals. The compilation paths and flags in the _info files are just noise. Actually the flags are quite nice to know even for protected code, it helps to pinpoint possible simulator bugs. --KimArticle: 89545
Hi, I want to use both PPC systems in a Virtex 4 device. Both have their own memory (physically). And the easiest way to work is to handle both devices seperatly. My question is: is this possible? Or will I get problems with JTAG for example. Is it allowed to have two different EDK projects or do I have to make one project with both processors? If I have two seperate processors, can I still debug through JTAG and GDB. And how does the jtag chain looks like in each project? Thanks in advance, FrankArticle: 89546
I had 2003 version on my PC, but it's giving me performance hassles on yesterday's simulations. What is the latest version of Modelsim for Xilinx? How is the performance? I am writing a 20K+ design for opencores, what free simulator can I use? Thanks for your info. FrankArticle: 89547
"Frank" <Francis.invalid@hotmail.com> wrote in message news:432e70c9$1@news.starhub.net.sg... > I had 2003 version on my PC, but it's giving me performance hassles > on yesterday's simulations. What is the latest version of Modelsim for > Xilinx? How is the performance? > > I am writing a 20K+ design for opencores, what free simulator can I use? > > Thanks for your info. > > Frank > > > BTW, I am dumb, so I need GUI to view waveforms during debugging.Article: 89548
Ben, John, Thank you for your replies. John, I think, as you said, MAC FIR is not relally suited for my application. And since I have an XC2VP30, the best is to manually program a FIR filter by myself. I think it's could be not too difficult. Ben, I agree with you (a s I said above). Concerning the hadrware Platform, it's an ADM-XPL board of Alpha-Data with a XC2VP30-5. Thank youArticle: 89549
hi i'm using modelsim (xilinx edition) and i was wondering how i can get my signals to show up in post translate simulation like in behavioral simulation. in behavioral simulation i just have to click on uut in the window "workspace" and i can get all my signals from my design or testbench. but in post translate simulation a lot of my signals have different names and vectors a split up into single signals. also if i try to use "add signal" it tells me it cant find it but i'm sure i'm using it in my testbench. can anybody help me here? thanks
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z