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Hi Ben, Tanks for the link, but i still need the GERBER files. HenriqueArticle: 89226
Hey,
I made a FSM with about 23 states (not the first time i've done vhdl
work, but never had this problem before with FSM => in fact it is not
really a problem) and i used following scheme:
sequencing:process(state,...)
begin
case state is
when ... =>
end case;
end process;
update:process(reset, clk)
begin
if (reset='1') then
state<=...;
elsif (clk'event and clk='1') then
state<=next_state;
end if;
end process;
logic:process(clk)
begin
if (clk'event and clk='1') then
...
end if;
end process;
so i don't think it is the way the fsm is build up ... so when i
compile it it does say :
Using one-hot encoding for signal <state>.
but i don't get a f.e.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 3
|
| Transitions | 7
|
| Inputs | 4
|
| Outputs | 3
|
| Clock | clk (rising_edge)
|
| Reset | reset (positive)
|
| Reset type | asynchronous
|
| Reset State | idle
|
| Power Up State | idle
|
| Encoding | automatic
|
| Implementation | LUT
|
-----------------------------------------------------------------------
and i was just wondering why XST does not find my FSM????
thank you in advance,
kind regards,
Tim
Article: 89227Sorry, my bad. I know I have programmed them using the ASMI interface in NIOS (is this what you are referring to by external prog. software?), but I haven't tried using the BB cable directly to the flash device. On the note that it must be shipped with something special in it.. .Altera clames the device is shipped with the memory all reset to FF's... where could they possibly store something? Jim's test definitely sounds like something interesting to try. It's a shame because I can't use anything more than a 4 Mbit flash device for configuration since Quartus only supports 1 and 4 (for me at least). I have a 32-mbit ST Micro flash device that I'm using as secondary flash holding user-code, but I can't seem to get it working as a primary configuration device. Maybe the $12 increase in price over the STM counterparts is actually something functionally different rather than a re-label :)Article: 89228
On Wed, 7 Sep 2005 10:26:23 -0400, "Matthew Plante" <maplante@iol.unh.edu> wrote: >XST 7.1i says that it has support for redhat linux enterprise 64 bit >edition. I installed enterprise 3 on a system we have, which is a quad >Itanium 2. However, I can't get the xst binaries to execute. Apparently >the binaries provided only work on AMD cpus? Is there an Intel 64bit >version available?? Yes and no. Intel supports the same 64 bit interface AMD 64 architecture defines in it's P4 cpus so yes but that's not what you want. AMD64 is not the same as IA64 and it is very doubtful that Xilinx will release binaries for a (slowly) dying architecture.Article: 89229
oh, and i forgot to mention that it found the FSM in ISE6.1 but not in
ISE7.1 ...
the result:
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 23
|
| Transitions | 82
|
| Inputs | 38
|
| Outputs | 28
|
| Clock | clk (rising_edge)
|
| Reset | reset (positive)
|
| Reset type | asynchronous
|
| Reset State | idle_st
|
| Power Up State | idle_st
|
| Encoding | automatic
|
| Implementation | LUT
|
-----------------------------------------------------------------------
Article: 89230Hi I am a student and trying my hands off xilinx virtex 2 multimedia board. I was trying to run an example "Character Mode SVGA" from xilinx website http://www.xilinx.com/products/boards/multimedia/examples.htm I am able to download the bit file to the board but now what do i do ? how do i see the picture on the computer screen ? i am bit lost , i tried to simulate the design using modelsim but it gives some errors :( i am a begineer and any advise would be highly appreciated ! thanks !! manmeetArticle: 89231
The "[15:0] ADCvals[i]" isn't correct syntax. If ADCvals is defined as "reg [15:0] ADCvals [12287:0]" then the [15:0] is implied but can be made explicit with most Verilog2001-capable tools by "ADCvals[i][15:0] <= ADCinVal;". The inAddr and rdAddr just have to be values. If you want to use an incrementing i, it works, but I'd recommend using a reg or wire with dimensions rather than an integer. You can read and write with different addresses or the same address. Just keep in mind that the read should be registered to match the registered memory model for the BlockRAM. Your synthesis tool will let you know if you're doing anything completely invalid, either by providing an error/warning or by using waaaaay too many resources by not mapping to BlockRAMs. <amir.intisar@gmail.com> wrote in message news:1126099407.645452.199140@o13g2000cwo.googlegroups.com... > Hey John, thanks for all the information and i will try that piece of > code you have given me, but how do i assign the FPGA pins to reg [15:0] > ADCvals [12287:0]; . Its basically - [data_in]ADCvals[inAddr]. DO i > just have to assign the "inAddr" to the SRAM address pins and not worry > about the data pins?. Also, can "inAddr" and "rdAddr" be incrementing > numbers?. I want to start at memory address 0 and store the incoming > data up to 12,000. Once completed, i want to start at 0 again and send > out the data until i reach memory address 12,000. I was hoping to just > have an number that increments, something like this, > > [15:0] ADCvals [i] <= ADCinVal; > i <= i + 1; > //wait for next value > > Thanks Mate !!! >Article: 89232
Hi, I am new to the Quartus II software and have trouble configuring the timing analyzer, would appreciate if anyone can help me out.. Below is what I need. My design includes an incoming clock of 122Mhz (clk0) that is then divided into 61Mhz (clk1) and 30Mhz (clk2) using a built-in PLL. Depending on two input pins (S0, S1) one of the three clocks is used to drive the main logic i.e. the main logic is still a single clock design. How do I tell the timing analyzer not to treat the main logic as a multiclock design, and prevent it from throwing tco and fmax violations? I get no errors if I removed the dynamic selection of clocks (between clk0, clk1 and clk2) and force the main logic to run at a given clock. Thanks -SanjayArticle: 89233
It has been down for two days now. Anyone know the story?Article: 89234
>>...I'm still waiting for the softies to come back, in the meantime I have >>modified my DDR2 controller, actually the PLB side of it (I didn't want to >>change the controller itself for this mess) such that when it detects a >>byte/16-bit word write it performs a read-modify-write access. It works! >> > > Hey, good job!! Sounds like something Xilinx might wanna add to their RAM > controllers in EDK! ;-) That's what's being done in ECC modes but in general it's not what you want to do for performance reasons. > So, me and one of the guys were talking about this last night. He reckons > that MIPS processors only ever do 32 bit accesses, i.e. no byte mask signals > come out of the device. How does Linux run on a MIPS processor? Does it do > read-modify-write, or does the software guy define all bytes as 32 bit words > in the compiler? The last time I looked at MIPS on an R4000 a long time ago the byte enables where encoded into a combination of Address and System Cmd Bus. I reckon this did not change too much since then. Further, on the MIPS you can not do unaligned accesses (i.e. access a word at address 1 or a halfword at address 1 or 3) whereas the PowerPC can do that without problems. Last but not least you can get a PowerPC embedded in an FPGA where you cannot get a MIPS ;-) - PeterArticle: 89235
Glen, Please check if you are getting the following message: Warning (10040): Verilog HDL or VHDL arithmetic warning at <location>: loss of carry in addition or borrow in subtraction If so, then this is a linting message that points out a potential design mistake. It's a related, but nevertheless distinct issue from simple truncation. If you get the truncation warning, you may be using a much older version of the software that didn't distinguish loss of carry from generic value truncation according to Verilog expression sizing rules. If you want you could mail the qar file for your project to me and can confirm. Hope this helps, Subroto Datta Altera Corp.Article: 89236
http://www.digilentinc.com/ works fine from here. Paul Pete Fraser wrote: > > It has been down for two days now. > Anyone know the story?Article: 89237
Hello all, I am designing a communications board based on a microblaze implementes on a spartan 3 400. I have 512kx32 external synchronous RAM, and I am trying to connect it to the microblaze by the LMB, both to data and instruction sides, so I have to multiplex both buses, giving priority to instruction bus. All this is easy and I have done it. Well, it seemed easy. When I test the external memorys, everything goes fine except when the interruption to MB activates one cycle before a memory read, so thtat INTERRUPT_TAKEN acknowledges the interrupt some 4-5 cycles after that (it is not a variable amount, it is fixed biut I have closed the chipscope window before writing this). Now at last, the *problem* or, as the C++ experts say the Really Bad Thing TM. Whenever this interlave of interrupt and memory fetch happens, register R14 does not save PC, but gets the value 0x00000000, thus causing a reset after the interrupt attention routine. By the way, all interrupt code and data lies within BRAM, and the external RAM cycle presents no anomalies, it end correctly. Has anyone any information to guide me to solution, or will I be forced to connect a fast synchronous RAM to OPB, thus working at half speed? Thanks to all Juan A. ZaratieguiArticle: 89238
jai.dhar@gmail.com wrote: > Sorry, my bad. I know I have programmed them using the ASMI interface > in NIOS (is this what you are referring to by external prog. > software?), but I haven't tried using the BB cable directly to the > flash device. > > On the note that it must be shipped with something special in it.. > .Altera clames the device is shipped with the memory all reset to > FF's... where could they possibly store something? Jim's test > definitely sounds like something interesting to try. It's a shame > because I can't use anything more than a 4 Mbit flash device for > configuration since Quartus only supports 1 and 4 (for me at least). I > have a 32-mbit ST Micro flash device that I'm using as secondary flash > holding user-code, but I can't seem to get it working as a primary > configuration device. Have you opened a case with Altera ?. That's a reasonably mainstream use of the config, and one they should be keen to support this obvious usage. -jgArticle: 89239
I tried to comiple the xilinx and EDK librariess for the first time by using the simulation library compilation wizard. I ran the wizard .everything works fine but when I press the compile button in the wizard I get nothing i.e. the compilation status bar displays that the ompilation has finished ( which is certainly not correct since the compilation gets doone in a jiffy). The destination folders where I stored the libraries are empty with nothing in it. I am using the modelsim SE 5.8d,EDK7.1 . I am using fedora core 2.Article: 89240
Tim Verstraete wrote:
> I made a FSM with about 23 states (not the first time i've done vhdl
> work, but never had this problem before with FSM => in fact it is not
> really a problem) and i used following scheme:
...
> and i was just wondering why XST does not find my FSM????
Perhaps XST is expecting a one or two process format.
But as you said, this is not really a problem if
sims and runs as you expect. A few dubious statistics
are not worth much extra work.
-- Mike Treseler
Article: 89241Have you considered XCL as the interface? "Xilinx CacheLink (XCL) is a high performance solution for external memory accesses." http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf Paul Zara wrote: > > Hello all, > > I am designing a communications board based on a microblaze implementes > on a spartan 3 400. > > I have 512kx32 external synchronous RAM, and I am trying to connect it > to the microblaze by the LMB, both to data and instruction sides, so I > have to multiplex both buses, giving priority to instruction bus. All > this is easy and I have done it. Well, it seemed easy. > > When I test the external memorys, everything goes fine except when the > interruption to MB activates one cycle before a memory read, so thtat > INTERRUPT_TAKEN acknowledges the interrupt some 4-5 cycles after that > (it is not a variable amount, it is fixed biut I have closed the > chipscope window before writing this). > > Now at last, the *problem* or, as the C++ experts say the Really Bad > Thing TM. Whenever this interlave of interrupt and memory fetch happens, > register R14 does not save PC, but gets the value 0x00000000, thus > causing a reset after the interrupt attention routine. > > By the way, all interrupt code and data lies within BRAM, and the > external RAM cycle presents no anomalies, it end correctly. > > Has anyone any information to guide me to solution, or will I be forced > to connect a fast synchronous RAM to OPB, thus working at half speed? > > Thanks to all > > Juan A. ZaratieguiArticle: 89242
In Quartus for the timing report have you ever gotten a timing violation to/from a signal ending with __Z - defining a false path using this doesn't fix this violation - ------------------------------------------------------- for e.g. say I have two signals "signal_abc" and "signal_xyz" I get a timing violation from signal_abc to signal_xyz__Z ------------------------------------------------------- any suggestions on what this means? Tristate condition perhaps ? how do I fix it ? defining a false path didn't help. thanks for your time.Article: 89243
I sent a PAL to MEFAS to be decapped. They e-mailed me this picture of the die before they sent it back. I just received fedex confirmation that the package arrived, but I'm out of state for the next few days. Here is the photo: http://media.diywelder.com/die%2520image.jpg Its a 16R8 HAL, not actually a PAL but it should be the same. I counted 8 groups, and 8 rows which makes 64 rows, and that sounds right. I only counted 16 olumns an not 32, but maybe when I get a higher power shot it will make more sense. Which areas would you like me to take a closer picture of? I will post some when I get back in. GrantArticle: 89244
Apparently the difference has to do with the WP pin! Regards, MarkArticle: 89245
sanjay.gajendra@gmail.com wrote: You need to use multi-cycle contraints! Regards, MarkArticle: 89246
The same thing happend to me also. But now the constrains are correct.Article: 89247
Mark McDougall <markm@vl.com.au> wrote in news:4320d893$0$14486$5a62ac22 @per-qv1-newsreader-01.iinet.net.au: > Apparently the difference has to do with the WP pin! > > Regards, > Mark > Mark, Do you want to comment further? -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 89248
What are you referring to Mark? The WP pin on the ST micro device is active low, and it's held at Vcc on the EPCS4 Config device (you are supposed to keep it at Vcc I mean).... meaning no write protect. This is essentially the same, correct? I just tried configuration with an ST Micro 4 Mbit device and it didn't work :( It was the M25P40.Article: 89249
"jai.dhar@gmail.com" <jai.dhar@gmail.com> wrote in news:1126241509.799550.314080@o13g2000cwo.googlegroups.com: > What are you referring to Mark? The WP pin on the ST micro device is > active low, and it's held at Vcc on the EPCS4 Config device (you are > supposed to keep it at Vcc I mean).... meaning no write protect. This > is essentially the same, correct? > > I just tried configuration with an ST Micro 4 Mbit device and it didn't > work :( It was the M25P40. > > I think there is a difference between an M25P40 & M25P40A. I'm not sure since we moved to SST for serial flash (for other purposes). -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
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Compare FPGA features and resources
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