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Hi Bob, Thanks, yep replacing my INST with NET fixes my problem. Regards Andrew Bob Perlman wrote: > I use something like: > > NET "net_name" LOC = "AB26" | IOSTANDARD = LVCMOS25 | PULLDOWN ; > > where net_name is the name of the I/O signal.Article: 89626
I know that NC has a gui. I have used it. I just don't think it is a nice gui. It's certainly not a complete or as powerful (or stable) as modelsim's. -ArlenArticle: 89627
Definitions of tHOLD, tSETUP can be found in the Static Timing Analysis Section of the Quartus Handbook. The URL is http://www.altera.com/literature/hb/qts/qts_qii53004.pdf In general when one sees the mesaage > The compiler report says "Required P2P time" is longer than actual "P2P > time". it means The clock skew is greater than his data delay, causing a hold violation. To fix this try the following: i) Check that the clock feeding the destination register is using a global clock line. ii) Check that there are no gated or ripple clocks in the design. If you have a gated or ripple clock a derived clock assignment should be made. While may not necessary fix the hold issue, but will better constraint the design. iii) Finally if you can copy and paste the list_path message, we can probably give more help. Hope this helps, Subroto Datta Altera Corp.Article: 89628
hi all, anyone know how to use digilent USB2 module in B1 connector of the spartan3 starter kit? CMOSArticle: 89629
Garrick wrote: > Within our Modelsim XE Starter Edition III program, any attempt to > compile or refresh a library generated by SE 6.0d gave an error message > that "this library is incompatible with this version of vlog." Even if > I created the resource library within SE 6.0d without any compiler > directives at all. Clearly, Modelsim XE is only designed to work with > open libraries. Did you try to manually set the optimisation level (-O0 or -O1 for example). SE defaults to a higer level than the cheaper versions. But I guess it's easiest to just ask from Mentor what they recommend. --KimArticle: 89630
nice job! You're referenced from the Mediatronix web site, but not from http://www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.htm You did not updated the "Last Changed" date at the bottom of your page since V0.3. M6 wrote: > I've created an IDE for the picoblaze-3 microcontroller (Xilinx TM). > The IDE is an open-source project (GPL-license) and works under the > Linux operating system. > > The IDE supports the following: > - Editor with syntax highlighting, > - Assemble and export to: HEX, VHDL or MEM files, > - Simulate the source code and see/modify the scratchpad, registers and > I/O ports. > > For those who are interested, checkout: http://www.xs4all.nl/~marksix > > Regards, > > Mark Six >Article: 89631
CMOS wrote: > hi all, > anyone know how to use digilent USB2 module in B1 connector of the > spartan3 starter kit? > > CMOS > Cut the trace from pin 6 on the USB board or it will hold PROG-B in the wrong state. Now you can use USB for fast i/o, but some other means to load the bitstream: JTAG only works in A1.Article: 89632
Hi, all. I'm using Xilinx FPGA with VHDL language. Now I try to build a system, and that system needs a counter which counts "1" bit in bit stream. like "11101001" => 5 I've tried several methods like adding all bits to one integer signal, (That is, result <= bit(0)+bit(1)+bit(2) ...;) or by using Xilinx bit correlator with all "1" reference bit stream. Is there any noble method for this problem? Thanx for any help.Article: 89633
Hi,
I have been using the following component for Lattice devices
when I want a signal to be routet into a fast output register:
ODDRXB_RASN : ODDRXB
PORT MAP ( Da =3D> ls_ddr_rasn_h1,
Db =3D> ls_ddr_rasn_h1,
Clk =3D> Clk90,
Lsr =3D> Reset,
Q =3D> DdrRasn
);
As you can see the module ODDRXB can be instantiated within the
VHDL module.
Now I want to do something similar in QuartusII version 5.0 software.
The only way I know is to tell the fitter in the Assignment Editor
that you want signals to be routet into output registers.
Is there a possibility to instantiate an output register module within
my VHDL module whithout using the Assignment Editor ?
Any hints are appreciated.
Rgds
Andr=E9
Article: 89634hetfield wrote: > Hi, all. > I'm using Xilinx FPGA with VHDL language. > > Now I try to build a system, and that system > needs a counter which counts "1" bit in bit stream. > like "11101001" => 5 > > I've tried several methods like adding all bits to one > integer signal, > (That is, result <= bit(0)+bit(1)+bit(2) ...;) > or by using Xilinx bit correlator with all "1" reference > bit stream. > > Is there any noble method for this problem? > Thanx for any help. > If you want to count the ones in an incoming bit stream, can you not just use the incoming data as an enable signal for a counter clocked with the same clock?Article: 89635
Thanks for your answer, but I want to count the "1" bits during only one or two clock cycles. I use 10 MHz clock in my system for synchronization. And the input bit stream is about 150 bits long. Moreover, input bit stream changes on every clock rising edges. That why I cannot apply simple counter on this problem.Article: 89636
Hi Austin, Please, have a look at an example, where I had used the attribute in XCF: Here "zbtcntr_double_width" is the entity name and RD_WRl_TRId2(0) is the register which I wanted to preserve. 1)MODEL "zbtcntr_double_width" equivalent_register_removal= false; #Use the above attr. , if you want it to be applicable to the whole module or entity. 2)BEGIN MODEL "zbtcntr_double_width" NET "RD_WRl_TRId2(0)" equivalent_register_removal= false; #Use the above attr. if you want to preserve a particular Reg. HTH Ajay Panicker CG-CoreEL Austin Franklin wrote: > I found "equivalent_register_removal", but so far, that hasn't worked > either...but that seems to be the right attribute, now I just have to get it > to work...as register_duplication is apparently not the right attribute. > > "Austin Franklin" <austin@darkr00m.com> wrote in message > news:EIZXe.347$X6.321@fe05.lga... > > Hi, > > > > What is the XST equivelent of Synplify's "synthesis syn_preserve = 1" (for > > Verilog)? I've tried using " > > synthesis attribute register_duplication xx "yes" " (closest thing I found > > so far that may be what I'm looking for) with xx equal to the module name, > > the module instance, the signal...nothing seems to work. I have register > > dulpication selected in the properties for "implement design"... > > > > Any help appreciated. > > > > Austin > > > >Article: 89637
hetfield wrote: > Thanks for your answer, but I want to count the "1" bits during only > one or two clock cycles. > I use 10 MHz clock in my system for synchronization. > And the input bit stream is about 150 bits long. Seems like a semantics issue. Normally the term "bitstream" implies data coming one bit at a time, serially. So you're saying every 100 nS you get 150 bits all at once? Normally we would say in this case the data is 150 bits "wide". > Moreover, input bit stream changes on every clock rising edges. > That why I cannot apply simple counter on this problem. 100 nS is a long time for modern FPGA's so you should be able to use many levels of logic, however serializing the data to 1500 MHz, 1 bit wide would not be an option (for the counter approach). So normally you'd use LUT's to group as many bits as possible into a sum in the first stage, possibly using block RAMs as LUTs if your architecture permits. Then use a tree of adders to finish the addition.Article: 89638
GPE wrote: > Wouldn't it be slick if Xilinx would offer USB as one of the available > configuration modes for their FPGA config memories! They do... You can buy the "USB Platform Cable" for about $150. It's the same as the Parallel Cable 4, just hooks up to an USB2 port. Works much more reliable than the parallel cable. cu, SeanArticle: 89639
Instead of making assignments using the Assignment Editor it is possible to
make these assignments inside your HDL. For examples please see Pgs 8-41 to
8-45 of the Quartus Handbook
http://www.altera.com/literature/hb/qts/qts_qii51008.pdf
The Section heading is "Setting Other Quartus II Options in your HDL source
code". The specific subsections that will be of interest to you are "Use I/O
Flip Flop" and "Altera Attribute".
Hope this helps,
Subroto Datta
Altera Corp.
<ALuPin@web.de> wrote in message
news:1127300678.339502.268800@o13g2000cwo.googlegroups.com...
Hi,
I have been using the following component for Lattice devices
when I want a signal to be routet into a fast output register:
ODDRXB_RASN : ODDRXB
PORT MAP ( Da => ls_ddr_rasn_h1,
Db => ls_ddr_rasn_h1,
Clk => Clk90,
Lsr => Reset,
Q => DdrRasn
);
As you can see the module ODDRXB can be instantiated within the
VHDL module.
Now I want to do something similar in QuartusII version 5.0 software.
The only way I know is to tell the fitter in the Assignment Editor
that you want signals to be routet into output registers.
Is there a possibility to instantiate an output register module within
my VHDL module whithout using the Assignment Editor ?
Any hints are appreciated.
Rgds
André
Article: 89640Sorry for my mistake. 150 bits wide - That's exactly what I just meant. Thank you very much for your help. I'll try LUT methods for my design.Article: 89641
hetfield wrote: > Thanks for your answer, but I want to count the "1" bits during only > one or two clock cycles. > I use 10 MHz clock in my system for synchronization. > And the input bit stream is about 150 bits long. > Moreover, input bit stream changes on every clock rising edges. > That why I cannot apply simple counter on this problem. So 1) how fast is the clock for your input bit stream and 2) why wait 100 ns before starting to count?Article: 89642
Hi, I figured out how to get it to work. There is a flag in the synthesis options to enable/disable this...that seemes to work, but obviously globally. To get it to work on individual registers, instead of globally, the directive seems like it has to be after the reg statement. I'm not sure why as the documentation shows that you have to name the register specifically in the directive...except that perhaps it's a single pass compiler. I had the directive just above the reg statement...and it complained it couldn't find the reg. Putting it on the same line worked. Austin "Austin Franklin" <austin@darkr00m.com> wrote in message news:Y1%Xe.409$X6.170@fe05.lga... > I found "equivalent_register_removal", but so far, that hasn't worked > either...but that seems to be the right attribute, now I just have to get it > to work...as register_duplication is apparently not the right attribute. > > "Austin Franklin" <austin@darkr00m.com> wrote in message > news:EIZXe.347$X6.321@fe05.lga... > > Hi, > > > > What is the XST equivelent of Synplify's "synthesis syn_preserve = 1" (for > > Verilog)? I've tried using " > > synthesis attribute register_duplication xx "yes" " (closest thing I found > > so far that may be what I'm looking for) with xx equal to the module name, > > the module instance, the signal...nothing seems to work. I have register > > dulpication selected in the properties for "implement design"... > > > > Any help appreciated. > > > > Austin > > > > > >Article: 89643
In article <1127305201.546845.85310@g43g2000cwa.googlegroups.com>, hetfield <magnacum@gmail.com> wrote: >Thanks for your answer, but I want to count the "1" bits during only >one or two clock cycles. >I use 10 MHz clock in my system for synchronization. I expect that a straightforward adder tree b[1:0] = a[0] + a[1] + a[2] b[3:2] = a[3] + a[4] + a[5] b[5:4] = a[6] + a[7] + a[8] ... c[2:0] = b[1:0] + a[3:2] c[5:3] = b[5:4] + b[7:6] ... [write perl to write the source code!] would happily add 150 bits together in the hundred nanoseconds you've got, using a total of about 150 adders of various widths (mostly small). If timing is critical, play around with the widths at the bottom; 3 LUTs will do a count-bits on a 4-bit word in one propagation delay. TomArticle: 89644
Try ArrowArticle: 89645
Is any using a Cyclone FPGA and NIOS II CPU? Specifically I'm having trouble booting from FLASH. THe boot sequence it to copy FLASH contents into DRAM then run out of DRAM. I can load directly into DRAM using the JTAG interface and all is OK. But running freestanding from a power up in NG. Is anyone able to accomplish this? GeorgeArticle: 89646
Hi Subroto, thank you for the link. One more question: I have put the attributes into my VHDL code. (in the ENTITY declaration). After compilation and synthesis I can see in the "Fitter Netlist Optimizations" that the signals have been routed into Fast Output Registers. But where do I see that in the Assignment Editor ? Is it visible there at all ? Are the attributes also valid if I use them in a submodule of my design ? Rgds Andr=E9Article: 89647
Hello group, How does one combine two models? Specifically, I have a Spartan3 with some models that I have made and connected to then Spartan3 is a NBT SRAM, which I have recently downloaded from the manufacturers web site. All in VHDL. And there is relatively short traces from the Spartan3 to the SRAM. Brad Smallridge aivision.comArticle: 89648
thank you. i noticed that. im wondering about the purpose of the JTSEL ( pin 6 you mentioned ) pin in USB2 module. No indication in the documentation. there might be a way to make it float from the microcontroller. CMOSArticle: 89649
please let me know the maximum speed that can be acheived using the supplied software dll and microcontroller firmware. I just need to transfer the whole memory at once thru the USB port. thank you. CMOS
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Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z