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Hi Vladimir, The circuit's being optimised away because the 'tool' doesn't understand that there's stuff outside the chip. It can't understand the output is current limited, so it thinks your circuit can be optimised away. If you make the outputs tri-state-able, and drive the tri-state line to turn them on from something the 'tool' doesn't optimise away, you'll have more success. Maybe. Have fun! Syms.Article: 88326
depending on the FPGA vendor, there are PLLs or DCMs that you can use. That is, applying a fractiponal rate of 2/5 gives you 10 MHz = 25 MHz * (2 / 5) Vladislav <alessandro.strazzero@gmail.com> wrote in message news:1124134866.696634.287180@o13g2000cwo.googlegroups.com... > Dear everybody, > > I'm a beginner in using VHDL to build hardware blocks. So, I > would like to submit you a problem about clock generation. > I have a 25MHz external clock driving a hardware block inside the > FPGA. I need a 10MHz clock to drive another hardware block inside the > same FPGA. How can I have a 10Mhz clock from the 25Mhz clock ? Is > it possible ? > > Your answers will be appreciated > > Best Regards > > /Alessandro Strazzero >Article: 88327
Brian, could you please paste your code here? Vladislav "Brian Dam Pedersen" <brian.pedersen@mail.danbbs.dk> wrote in message news:4300b246$0$67262$157c6196@dreader2.cybercity.dk... > Hi group > > I'm trying to infer an 18-bit rom to be put in a block RAM. I'm using a > case statement and a clocked address as described by Xilinx. My ROM is > 1024 words, so I was thinking that this could be done using only one BRAM, > but the ISE 7.1 webpack creates two BRAMs in this case. Isn't it possible > to fit more than 16 bits of ROM into a single BRAM ? I can fit 18 bits of > RAM so why not ROM ? > > -- BrianArticle: 88328
what the hell is this? quad-clock flip-flop? V "QRaheeL" <qraheel@gmail.com> wrote in message news:1124047644.745006.244770@o13g2000cwo.googlegroups.com... > Hi guys. > > An intesresting problem occured when I used "more than three" signals > in always block sens list. > > XST (ISE 6.1i) reported the following error: > > ERROR:Xst:1468 - dummy.v line 25: Unexpected event in always block > sensitivity list. > > Same code is successfully compiled & simulated in MOdelSim5.7SE. > > What kind of problem is this ? > Related to parser/editor/etc ?? > > //-------- C O D E - C O D E --------/// > > module dummy(x); > output x; > assign x = 1'b0; > > reg a,b,c,d; > reg z; > > initial > begin > a=0; b=0; c=0; d=0; z=0; > #100 $stop; > end > > always #10 a=~a; > always #15 b=~b; > always #20 c=~c; > always #5 d=~d; > > always @(posedge a or posedge b or posedge c or posedge d ) begin > if(a) z=~z; > else if(b)z=~z; > else if(c) z=~z; > else if(d) z=~z; > end > endmodule >Article: 88329
alessandro.strazzero@gmail.com wrote: > Dear everybody, > > I'm a beginner in using VHDL to build hardware blocks. So, I > would like to submit you a problem about clock generation. > I have a 25MHz external clock driving a hardware block inside the > FPGA. I need a 10MHz clock to drive another hardware block inside the > same FPGA. How can I have a 10Mhz clock from the 25Mhz clock ? Is > it possible ? > > Your answers will be appreciated > > Best Regards > > /Alessandro Strazzero > Alessandro, The CLKDV output of the Spartan or Virtex DCM may be used with DIV=2.5 to synchronously divide a 25 MHzz clock input to create a 10 MHz clock output. AustinArticle: 88330
Attached. Nothing special, just a set of FIR coefficients
>>>>>>>>>>>>>>>> Archive maintainer deleted 95% of this irrelevency
-- Brian
Vladislav Muravin wrote:
> Brian,
>
> could you please paste your code here?
>
> Vladislav
>
> "Brian Dam Pedersen" <brian.pedersen@mail.danbbs.dk> wrote in message
> news:4300b246$0$67262$157c6196@dreader2.cybercity.dk...
>
>>Hi group
>>
>>I'm trying to infer an 18-bit rom to be put in a block RAM. I'm using a
>>case statement and a clocked address as described by Xilinx. My ROM is
>>1024 words, so I was thinking that this could be done using only one BRAM,
>>but the ISE 7.1 webpack creates two BRAMs in this case. Isn't it possible
>>to fit more than 16 bits of ROM into a single BRAM ? I can fit 18 bits of
>>RAM so why not ROM ?
>>
>>-- Brian
>
>
>
filename="coef_rom.v"
module coef_rom(data,addr,clk);
output [17:0] data;
input [9:0] addr;
input clk;
reg [17:0] data;
reg [9:0] i_addr;
always @ (posedge clk) begin
i_addr <= addr;
end
always @ (i_addr) begin
case (i_addr)
10'h000: data = 18'h00000;
10'h001: data = 18'h00000;
10'h002: data = 18'h3FFE4;
10'h003: data = 18'h3FEA7;
>>>>>> some people are so thoughtless when they post :-(
10'h3FD: data = 18'h00000;
10'h3FE: data = 18'h00000;
10'h3FF: data = 18'h00000;
endcase
end
endmodule
Article: 88331Peter Alfke wrote: > I thought of this circuit, drew it with a pencil on a piece of paper, > and analyzed it in my head. > And I bredboarded it many years ago, without using any synthesis tool. > I know it works, but I have not tried to sneak it past the security > guards in the newer tools. Who claims that progress is always moving > forward ? > Peter Alfke <paste> > austin wrote: >> Of course we test the new software. In fact, we are adding test cases, >> and whole new test requirements with every service pack that goes out. >> >> Austin Probably a silly question, but shouldn't a Xilinx published circuit be part of the test cases used by Xilinx, in all their new software releases ? -jgArticle: 88332
-snip- > > Probably a silly question, but shouldn't a Xilinx published circuit be > part of > the test cases used by Xilinx, in all their new software releases ? > > -jg Jim, Not necessarily. Better test cases are the hundreds of real projects from our customers that better represent the majority of the features being used. AustinArticle: 88333
On 15 Aug 2005 12:41:06 -0700, alessandro.strazzero@gmail.com wrote:
>Dear everybody,
>
>I'm a beginner in using VHDL to build hardware blocks. So, I
>would like to submit you a problem about clock generation.
>I have a 25MHz external clock driving a hardware block inside the
>FPGA. I need a 10MHz clock to drive another hardware block inside the
>same FPGA. How can I have a 10Mhz clock from the 25Mhz clock ? Is
>it possible ?
>
>Your answers will be appreciated
>
>Best Regards
>
>/Alessandro Strazzero
You might want to look in the FAQ:
http://www.fpga-faq.org/FAQ_Pages/0019_Divide_Clock_By_N_point_5.htm
===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG
Article: 88334311f037@gmail.com wrote: > Hey! > > SUpposing im using Xilinx ISE 4.2, how do I go about creating an EDIF > file to load into this as thats the only thing I seem to be able to > import into the 4.2v > > So what do I need to do? somehow find a compiler? or a simulator? will > these output and EDIF from my VHDL? > > I did a google filetype:edif search to see whether this helps me > explain it further to myself, but it seems like a net list or something > that you create after placing the cells (or what ever its called) and I > havent done that, Ive typed my VHDL and made a UCF file, so what now? > > Can anybody give me an overview (ASSII flow chart?? heh) of what I need > to do from VHDL to sythesising with ISE 4.2? its the steps in the > middle I can't figure out! Sven, approximately the sequence of steps that you go through is this - You take your VHDL (and constraints file - ucf for a xilinx native flow), and run it through a synthesiser (AFAIK, this is XST for ISE). This gives you a file with a set of primitives relevant to the FPGA you are working with (EDIF for me)). You then dump it through another couple of tools to get an .ncd, which you run place and route tools on (You may get a few intermediate files - my toolflow differs). At the other end, you get a .bit, which is the file you load into your FPGA. Shouldn't the GUI handle this? You probably want to figure out how to get your vhdl files into your project - the ISE toolset should handle the whole process of going from VHDL to bitstream. The other point is that ISE 4.2 is quite old - you might want to consider getting a more up-to-date set of tools (ex: 7.1 is out at the moment). I know that schematic entry used to be popular - can you confirm that you actually have a synth. tool? You can download the webpack free from Xilinx, but if you're running foundation, then that has more tools, and you probably want to try getting the setup that you have working first. JeremyArticle: 88335
praetorian wrote: > Sven wrote: > >> Hi, >> >> i try to build a dynamic reconfiguration application with use of icap >> and the embedded powerpc. By reverse engineering i found a lot of the >> bit-combinations in the configuration-frames, which handle the routing >> in the switch-boxes. The reverse engineering process takes a lot of >> time. I think anybody can give me the remaining bit-combinations in the >> frames? >> Thanks, Sven >> > I've tried doing that as well. It's really hard to get the whole picture > with reverse engineering. I gave up after a few months. Try to follow > the approach in XAPP260 to do modular reconfiguration. The partial-reconfig list set up last year is having the intended outcome - a gathering of folks experienced in (or learning) the black art of partial reconfiguration, and coaxing the tools to give you what you want. Details here (including searchable archive): http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ Regards, JohnArticle: 88336
AHDL is a HDL just like VHDL and Verilog are. VHDL and Verilog are open HDL standards supported by many synthesis vendors, whereas AHDL is proprietary to Altera. Altera will continue to support synthesis of AHDL based designs, to ensure that legacy products using AHDL can be recompiled using newer versions of Quartus. DSP Builder and SOPC Builder are code generators from high level descriptions. DSP Builder works of the Matlab/Simulink system description and SOPC builder works of its own system description. In the end both DSP Builder and SOPC Builder tools generate VHDL or Verilog that is input into Quartus. We have chosen not to support AHDL as the output of DSP Builder or SOPC Builder as the generated systems could not be simulated using any of the standard HDL simulators like Modelsim, VCS, NCSim etc. If you want to use Modelsim for behavioral or timing simulation you are better of writing your code in VHDL or Verilog instead of AHDL. If you would like to perform timing simulation using the Quartus native gate level simulator you can write your code in AHDL. Quartus allows mising of languages therefore it is possible to have a mixture of VHDL entities, Verilog modules and AHDL subdesigns within the same project. Hope this helps, Subroto Datta Altera Corp.Article: 88337
Jim, what do you suggest: Whenever somebody in Xilinx suggests an application, all software is put onhold until the new idea has passed all software? Or: Whenever somebody in Xilinx suggests an application, it may not be published until it has passed all software implementations? The specific idea in this thread is over 30 years old, and had been proven in many TTL designs, but had not been synthesized, because synthesis did not exist at its birth. Nevertheless, I have gone back and made some circuit ideas more synthesis-friendly... Peter AlfkeArticle: 88338
John Larkin wrote: > On 14 Aug 2005 19:21:08 -0700, ScreamingFPGA@yahoo.com wrote: > > >Hello All, > > I'm three days into this configuration problem, > >so I think it's time to consult the experts. > >Problem's like this usually seem trivial in > >retrospect, but I've usually been looking in > >the wrong places... > > > > Briefly, INIT line goes low one CCLK pulse after > >DONE line goes high. Configuration loads and runs, > >but INIT line low indicates a CRC error. The signals > >look quite reasonable on a scope. > > > > Specifics: > > On a new prototype board I'm trying to congigure > >a Spartan-3 3s1000-5fg456 using a 3.3V IO micro- > >controller driving the fpga's config lines. Dedicated > >config lines have serial resistor (100 ohm), as > >per recommendation for 3.3V tolerant config. > > > > I'm using slave-serial mode to write config file, > >which is stored on the micro's flash memory. I've > >used the same micro and method successfully in other > >products (but using Spartan-2). > > > > I send all data frames ( FFFFFFFF , AA995566 , > >... 20000000 ) start to end of file. > > > > I'm not sure exactly _where_ the DONE line should > >go high. It would seem that it should go high at some > >point after the last 32-bit configuration frame, but > >in fact DONE transitions on the 7th CCLK pulse of the > >(N-4)th configuration frame. XAPP452 shows this as being > >[CMD Write Packet Data(DESYNC)] frame. The INIT line > >goes low on the 8th CCLK pulse, Fpga operation commences > >on the 9th CCLK pulse. > > > > All design tweaks (resistor value changes) and clock/ > >data timing tweaks result in the same behavior. I would > >have thought that the CRC error would have prevented > >startup of the fpga (CRC is _not_ disabled in bitgen), but > >I guess this is not the case... > > > > If the DONE line _is_ going high early, I suppose this > >would mean that extra CCLK transitions were seen by > >the FPGA, pointing perhaps towards signal integrity > >issues, but this would puzzle me, as under different > >circumstances, the transitions happen at the same > >points. > > > > The bit file is being generated by ISE6.2.02. > > > > Sorry, this post is longwinded, I'm hoping that someone > >in the group has encountered a similar situation and can > >perhaps point me in the right direction. > > > > Thanks in advance... > > > >Scott@sdeviation.com > > > You might try banging some extra dummy bits; sometimes that helps. > > John Thanks John, The Configuration file _does_ load, though. I think dummy bits might help if the DONE line didn't go high. But it does. The FPGA starts, but the problem is that the INIT line goes low subsequent to the DONE line going high. There are apparently differences in configuration programming between the Virtex/Spartan-2, and the Virtex-2/Spartan-3 that I don't understand well enough. Especially the CRC / AutoCRC differences. I've been studying the doc's, but at this point I'm just confused... Thanks for the suggestion though. -Scott bArticle: 88339
Subroto Datta wrote: > AHDL is a HDL just like VHDL and Verilog are. VHDL and Verilog are open > HDL standards supported by many synthesis vendors, whereas AHDL is > proprietary to Altera. Altera will continue to support synthesis of > AHDL based designs, to ensure that legacy products using AHDL can be > recompiled using newer versions of Quartus. > > DSP Builder and SOPC Builder are code generators from high level > descriptions. DSP Builder works of the Matlab/Simulink system > description and SOPC builder works of its own system description. > > In the end both DSP Builder and SOPC Builder tools generate VHDL or > Verilog that is input into Quartus. We have chosen not to support AHDL > as the output of DSP Builder or SOPC Builder as the generated systems > could not be simulated using any of the standard HDL simulators like > Modelsim, VCS, NCSim etc. > > If you want to use Modelsim for behavioral or timing simulation you are > better of writing your code in VHDL or Verilog instead of AHDL. If you > would like to perform timing simulation using the Quartus native gate > level simulator you can write your code in AHDL. Quartus allows mising that should be mixing ? > of languages therefore it is possible to have a mixture of VHDL > entities, Verilog modules and AHDL subdesigns within the same project. Altera could do AHDL to VHDL ? That is what I understand Xilinx do, on their newest webpacks, for the ABEL flows ? A commendable move, as it preserves code base, expands user language choice, and allows hooking into the simuators you mention above. -jgArticle: 88340
I am assisting in the debug of a board with XC5202 parts. The design is
done using Aldec schematics in the M1.4 environment. I have M1.5 set up
on Win2K in a VMWare virtual machine.
Q: Does anyone know the latest version of the Xilinx implemenation tools
which support the XC5200?
Q: Latest version of Foundation Express which supports XC5200?
Q: Can either of these older versions be installed/run from Windows 2000?
Q: How can I get the latest patches/service packs for tools with XC5200
support?
I have a valid license for Foundation Express version which supports
XC5200. Following is from my license.dat
PACKAGE FND-EXP-PC xilinxd 1.000 30A0C0B1948681FADED8 \
COMPONENTS="system-PC bit-PC \
xc3000D-PC xc4000X-PC xc5200X-PC \
ngd2vhdl-PC verilog-PC \
Foundation-PC X-VHDL-PC \
FPGA-Express:1997.110 \
FPGA-Express-VHDL-Base:1997.110 \
FPGA-Express-VLOG-Base:1997.110 \
FPGA-Express-XC3k-Optimizer:1997.110 \
FPGA-Express-XC4k-Optimizer:1997.110 \
FPGA-Express-XC5k-Optimizer:1997.110 \
FPGA-Express-XC9k-Optimizer:1997.110 \
FPGA-Express-Constraint-Mgr:1997.110 "
Does anyone know what version of Foundation Express this license applies to?
To Xilinx: How can I get this license renewed? How can I get a copy of
the install CD and patches for this version of Foundation Express?
TIA
Urb
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Article: 88341On 15 Aug 2005 17:48:35 -0700, ScreamingFPGA@yahoo.com wrote: >John Larkin wrote: >> >> You might try banging some extra dummy bits; sometimes that helps. >> >> John > >Thanks John, > > The Configuration file _does_ load, though. I think dummy bits >might help if the DONE line didn't go high. But it does. The FPGA >starts, but the problem is that the INIT line goes low subsequent >to the DONE line going high. > There are apparently differences in configuration programming >between the Virtex/Spartan-2, and the Virtex-2/Spartan-3 that >I don't understand well enough. Especially the CRC / AutoCRC >differences. I've been studying the doc's, but at this point I'm >just confused... > >Thanks for the suggestion though. > >-Scott > >b We just take a .RBT file from ISE and pass it through a little program that packs it verbatum into our ROM image as binary stuff, up above the uP code (sort of a linker, sort of.) At powerup we bit-bang this into the FPGAs in slave serial mode, plus maybe 32 extra bits for luck. This has worked every time so far, on 4000's and S2's and S3's. Does the INIT thing matter? JohnArticle: 88342
Hi All, I have just found out about the GSPx 2005 conference and workshop to be held in Santa Clara. Has any one been to this conference before? Is it worth while attending if you are interested in DSP on FPGA systems for wireless applications? Thanks SudhirArticle: 88343
John Larkin wrote: > On 15 Aug 2005 17:48:35 -0700, ScreamingFPGA@yahoo.com wrote: > > >John Larkin wrote: > >> > >> You might try banging some extra dummy bits; sometimes that helps. > >> > >> John > > > >Thanks John, > > > > The Configuration file _does_ load, though. I think dummy bits > >might help if the DONE line didn't go high. But it does. The FPGA > >starts, but the problem is that the INIT line goes low subsequent > >to the DONE line going high. > > There are apparently differences in configuration programming > >between the Virtex/Spartan-2, and the Virtex-2/Spartan-3 that > >I don't understand well enough. Especially the CRC / AutoCRC > >differences. I've been studying the doc's, but at this point I'm > >just confused... > > > >Thanks for the suggestion though. > > > >-Scott > > > >b > > > We just take a .RBT file from ISE and pass it through a little program > that packs it verbatum into our ROM image as binary stuff, up above > the uP code (sort of a linker, sort of.) At powerup we bit-bang this > into the FPGAs in slave serial mode, plus maybe 32 extra bits for > luck. This has worked every time so far, on 4000's and S2's and S3's. > > Does the INIT thing matter? > > John Yeah, that's what we do too, just bang out the bit file verbatim. Maybe it doesn't matter. I checked my older designs, and see that I never monitored the INIT line, so the S2's could be behaving the same way, and I wouldn't know it. Ignorance is bliss? Maybe I should check... I noticed that the Parallel Programmer 6 pin interface adaptor doesn't use the INIT pin either. That says something... It only matters in that: 1) The fpga is complaining. I'd hate to get bit by it later on (no pun intended). 2) In this design I use INIT (a dual purpose pin) as an input after config, but it persists as an output. I guess I could cut and jumper, but it would be nice to sort it out and save a board rev. As a practical matter, maybe I should just ignore it for the time being. File it in the conundrum bin and move on... Again, thanks for the fresh perspective. -ScottArticle: 88344
I figured out what the problem is. Instead of just having inout ports in the module mapped onto the inout ports of the top level entity, I had 3 ports for input,output and control signal from the module and used these signals in the top level design for the inout port.Article: 88345
Peter Alfke wrote: > Jim, what do you suggest: > Whenever somebody in Xilinx suggests an application, all software is > put onhold until the new idea has passed all software? > Or: Whenever somebody in Xilinx suggests an application, it may not be > published until it has passed all software implementations? > > The specific idea in this thread is over 30 years old, and had been > proven in many TTL designs, but had not been synthesized, because > synthesis did not exist at its birth. > > Nevertheless, I have gone back and made some circuit ideas more > synthesis-friendly... > Peter Alfke Peter, If it was me, I would not take Austin's stance, that 'too simple' circuits somehow exclude themselves from the test suites.. Nor the approaches above [no smileys?], but I'd apply some "common sense", and try and ensure that ideas are both tested, and continue to be tested, as software iterates - rather a more pro-active, parallel approach, than the ON-OFF your and Austin's replies suggested. -jgArticle: 88346
On 15 Aug 2005 19:15:42 -0700, ScreamingFPGA@yahoo.com wrote: >John Larkin wrote: >> On 15 Aug 2005 17:48:35 -0700, ScreamingFPGA@yahoo.com wrote: >> >> >John Larkin wrote: >> >> >> >> You might try banging some extra dummy bits; sometimes that helps. >> >> >> >> John >> > >> >Thanks John, >> > >> > The Configuration file _does_ load, though. I think dummy bits >> >might help if the DONE line didn't go high. But it does. The FPGA >> >starts, but the problem is that the INIT line goes low subsequent >> >to the DONE line going high. >> > There are apparently differences in configuration programming >> >between the Virtex/Spartan-2, and the Virtex-2/Spartan-3 that >> >I don't understand well enough. Especially the CRC / AutoCRC >> >differences. I've been studying the doc's, but at this point I'm >> >just confused... >> > >> >Thanks for the suggestion though. >> > >> >-Scott >> > >> >b >> >> >> We just take a .RBT file from ISE and pass it through a little program >> that packs it verbatum into our ROM image as binary stuff, up above >> the uP code (sort of a linker, sort of.) At powerup we bit-bang this >> into the FPGAs in slave serial mode, plus maybe 32 extra bits for >> luck. This has worked every time so far, on 4000's and S2's and S3's. >> >> Does the INIT thing matter? >> >> John > > Yeah, that's what we do too, just bang out the bit file verbatim. > > Maybe it doesn't matter. I checked my older designs, and see that I >never >monitored the INIT line, so the S2's could be behaving the same >way, and I wouldn't know it. Ignorance is bliss? Maybe I should >check... > > I noticed that the Parallel Programmer 6 pin interface adaptor >doesn't use the INIT pin either. That says something... > > It only matters in that: >1) The fpga is complaining. I'd hate to get bit by it later on > (no pun intended). >2) In this design I use INIT (a dual purpose pin) as an input > after config, but it persists as an output. I guess I could > cut and jumper, but it would be nice to sort it out and save > a board rev. > > As a practical matter, maybe I should just ignore it for the time >being. File it in the conundrum bin and move on... > >Again, thanks for the fresh perspective. > > -Scott Are you pulling up INIT? JohnArticle: 88347
Jim, I really agree with you (sorry for the missing smileys). On one hand it is embarrassing when an old hand describes a proven circuit, and the younger crowd finds that it "doesn't work". On the other hand, I think that, especially with such a simple and peripheral circuit, it would be nice if engineers retained some basic understanding of physics and circuitry. I have a running battle with people who think the X at the latch output (or flip-flop Q when the set-up time is violated) is an undefined, in-between mysterious level, instead of just an unknown (but physically real) state. Or with people who try to analyze metastability with logic simulation tools. Designers should realize that real digital signals are High or Low (and rarely in-between), while 0 and 1 and X are just convenient abstractions that work most of the time, but not always. But I try my best not to become a cranky old fart. Hell, I am still proud of that cheap de-bouncing trick! PeterArticle: 88348
Possibly this is what John is suggesting in his previous post, but how do you know it is the FPGA pulling Init low? You mention that the Init pin is used as an input after config. What drives the Init pin externally? John Larkin wrote: > On 15 Aug 2005 19:15:42 -0700, ScreamingFPGA@yahoo.com wrote: > > >John Larkin wrote: > >> On 15 Aug 2005 17:48:35 -0700, ScreamingFPGA@yahoo.com wrote: > >> > >> >John Larkin wrote: > >> >> > >> >> You might try banging some extra dummy bits; sometimes that helps. > >> >> > >> >> John > >> > > >> >Thanks John, > >> > > >> > The Configuration file _does_ load, though. I think dummy bits > >> >might help if the DONE line didn't go high. But it does. The FPGA > >> >starts, but the problem is that the INIT line goes low subsequent > >> >to the DONE line going high. > >> > There are apparently differences in configuration programming > >> >between the Virtex/Spartan-2, and the Virtex-2/Spartan-3 that > >> >I don't understand well enough. Especially the CRC / AutoCRC > >> >differences. I've been studying the doc's, but at this point I'm > >> >just confused... > >> > > >> >Thanks for the suggestion though. > >> > > >> >-Scott > >> > > >> >b > >> > >> > >> We just take a .RBT file from ISE and pass it through a little program > >> that packs it verbatum into our ROM image as binary stuff, up above > >> the uP code (sort of a linker, sort of.) At powerup we bit-bang this > >> into the FPGAs in slave serial mode, plus maybe 32 extra bits for > >> luck. This has worked every time so far, on 4000's and S2's and S3's. > >> > >> Does the INIT thing matter? > >> > >> John > > > > Yeah, that's what we do too, just bang out the bit file verbatim. > > > > Maybe it doesn't matter. I checked my older designs, and see that I > >never > >monitored the INIT line, so the S2's could be behaving the same > >way, and I wouldn't know it. Ignorance is bliss? Maybe I should > >check... > > > > I noticed that the Parallel Programmer 6 pin interface adaptor > >doesn't use the INIT pin either. That says something... > > > > It only matters in that: > >1) The fpga is complaining. I'd hate to get bit by it later on > > (no pun intended). > >2) In this design I use INIT (a dual purpose pin) as an input > > after config, but it persists as an output. I guess I could > > cut and jumper, but it would be nice to sort it out and save > > a board rev. > > > > As a practical matter, maybe I should just ignore it for the time > >being. File it in the conundrum bin and move on... > > > >Again, thanks for the fresh perspective. > > > > -Scott > > Are you pulling up INIT? > > JohnArticle: 88349
Thanks Hubble. This worked and forgot that the signals have an additional delay compared with variables which can change instantaneously. Cheers, Pino Hubble wrote: > Your code produces a delta between assigning refmemdata and write. Note > that signal assignments only update the signal drivers, which update > the signal value at the next cycle. > > You can insert a wait for 0 ns; statement to let the signal settle: > > ... > -- Array accessing and file storage > stimulus: process() > variable data_file_line: line; > begin > for k in 0 to 4 loop > wait until (clk'event) and (clk = '1'); > refmemdata <= mem_arr(k); > WAIT FOR 0 ns; -- let refmemdata settle > write(data_file_line, to_bitvector(refmemdata)); > writeline(data_vector_file,dat a_file_line); > > end loop; > > end process; > > > or you can use a local variable, the preferred solution here: > > stimulus: process() > variable data_file_line: line; > VARIABLE refmemdata :std_logic_vector(2 downto 0); > begin > for k in 0 to 4 loop > wait until (clk'event) and (clk = '1'); > refmemdata := mem_arr(k); -- USE := instead of <= here > write(data_file_line, to_bitvector(refmemdata)); > writeline(data_vector_file,dat a_file_line); > > end loop; > > end process; > > Hubble.
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