Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
air_bits@yahoo.com wrote: > Eric Smith writes: > >How would you write it if you did NOT want a flip-flop, but only > >a combinatorial output? > > Depends on the tool. TMCC/FpgaC registers the state of every > variable by default, and it takes a minor edit of the output netlist > to remove the register. Seems to me that editing the output netlist is akin to editing a PCB design's Gerber files. There's a disconnect between the source, which in the FpgaC case is the C source file and in a PCB design the schematic, and the result, meaning either the final FPGA load or the finished PCB. In other words, I want to look at the source and know that it matches the hardware. -aArticle: 91751
I've been thinking about two months in buying a FPGA KIT and I've finally decided to buy this board http://www.digilentinc.com/info/XUPV2P.cfm . I don't know if it's a good election. I'm coursing the first university studies and I've doing doing a subject about building a simply general purpose processor. I liked it and now I want to do my own mini-projects. I'm interested also in the usb module to learn about usb memories,bluethoot modules,game pads,etc. I don't know if there are good documentation and tutorials for this boards. I know that it is a little expensive (299$ , 349$ with the usb module) but I don't want to change the board in a few months. I've managed some protocols like ATA/ATAPI but I don't know if it can be too complex. Thanks you very much, JordiArticle: 91752
"Jordi" <a80x86@hotmail.com> schrieb im Newsbeitrag news:1131736588.556776.166780@f14g2000cwb.googlegroups.com... > I've been thinking about two months in buying a FPGA KIT and I've > finally decided to buy this board > http://www.digilentinc.com/info/XUPV2P.cfm . I don't know if it's a > good election. I'm coursing the first university studies and I've doing > doing a subject about building a simply general purpose processor. I > liked it and now I want to do my own mini-projects. I'm interested also > in the usb module to learn about usb memories,bluethoot modules,game > pads,etc. I don't know if there are good documentation and tutorials > for this boards. I know that it is a little expensive (299$ , 349$ with > the usb module) but I don't want to change the board in a few months. > I've managed some protocols like ATA/ATAPI but I don't know if it can > be too complex. > > Thanks you very much, > > Jordi > Hi this module at academic pricing is not expensive, it is actually sold below or at self cost of the components. The academic pricing is 5 times lower than this kind of board would cost normally. AnttiArticle: 91753
I am currently doing a research project that involves simulating a oggvorbis codec on quartus2 V5. My source files were taken from a "oggonachip" porject. They developed their system on the LEON platform and simulated it using TSIM. My problem is on porting the codec core (VHDL code) to Quartus it keeps falling over during compilation. The error message states that it cannot find the library files which of course I have already added to the project. Can anyone give some insight into why these library files are invisible to Quartus? Any help would be appreciated. BryanArticle: 91754
I wrote: > How many real-world designs have NO combinatorial outputs? air_bits@yahoo.com writes: > How many PIC's and other microprocessors have combinatorial outputs? > Maybe None? Actually I've used the analog comparators that are available on many PICs as combinatorial logic.Article: 91755
>From time to time I'm given a Xilinx project directory (project file, ucfs, cores, source) and have to add my own components to the project. Is there a way to add files to a Xilinx ISE 7.1 project with a script file or the command line instead of using the "Add Source ..." option in the Project menu? Thanks, AndrewArticle: 91756
air_bits@yahoo.com wrote:
> Mike Treseler wrote:
>>This style feels somewhat C-like but the
>>template keeps me in "think hardware" mode.
>
> Yep. Then the big difference starts, debugging in "think hardware"
> mode, or debugging in "think software" mode using source level
> debuggers with break points, single stepping and variable watching
> at a high level.
Modelsim does all of that for vhdl or verilog source code as well.
In a single-process (or always block) design, tracing just
one thread and watching variable values is very
effective way to debug the logic description.
-- Mike Treseler
Article: 91757Hi stephane, Which OS are u planning to boot ? U boot has a port done for the xilinx ML300 Board. Take a look at the source code of Uboot , will be a good starting point. I am looking in exactly to do something similar like yours.Article: 91758
We've got a couple of those boards in the lab and I've been impressed. They have a faster 2vp30 than the ml310 boards. I'm not certain, however, that you can use the USB in designs or if its just for configuration. There may be a long lead time on them as well. StephenArticle: 91759
sharpa17@gmail.com wrote: >>From time to time I'm given a Xilinx project directory (project file, > ucfs, cores, source) and have to add my own components to the project. > Is there a way to add files to a Xilinx ISE 7.1 project with a script > file or the command line instead of using the "Add Source ..." option > in the Project menu? I don't have an answer. But since I am still annoyed about it...;) Up through ISE6.3, this was trivial to do, because the project file was plain text. I frequently added and removed things with a text editor, which I found to be easier than the "Add Source ..." stuff. Then someone decided to to change to a binary file for ISE 7.1 :-(Article: 91760
sharpa17@gmail.com wrote: > >From time to time I'm given a Xilinx project directory (project file, > ucfs, cores, source) and have to add my own components to the project. > Is there a way to add files to a Xilinx ISE 7.1 project with a script > file or the command line instead of using the "Add Source ..." option > in the Project menu? > > Thanks, > > Andrew I don't know about a script, but do you realize you can add multiple files at once using the "Add Source" if they're in the same folder. I'm assuming you're looking for a way to reduce the tedium of adding a lot of new source files?Article: 91761
Stephen Craven wrote: > We've got a couple of those boards in the lab and I've been impressed. > They have a faster 2vp30 than the ml310 boards. I'm not certain, > however, that you can use the USB in designs or if its just for > configuration. > > There may be a long lead time on them as well. > > Stephen > I use this board. It's great. USB is for configuration only. -EliArticle: 91762
Andy Peters wrote: > air_bits@yahoo.com wrote: > > Eric Smith writes: > > >How would you write it if you did NOT want a flip-flop, but only > > >a combinatorial output? > > > > Depends on the tool. TMCC/FpgaC registers the state of every > > variable by default, and it takes a minor edit of the output netlist > > to remove the register. > > Seems to me that editing the output netlist is akin to editing a PCB > design's Gerber files. There's a disconnect between the source, which > in the FpgaC case is the C source file and in a PCB design the > schematic, and the result, meaning either the final FPGA load or the > finished PCB. > > In other words, I want to look at the source and know that it matches > the hardware. If that is what you want, you are certainly free not to do anything special. >From a software perspective it's pretty common to use a tool to produce the prototype, and then to use a script to fix/edit that prototype to create the final form for production. The general key is to document the process well, and manage it. The whole Xilinx tool chain used to be a series of net list edits from front to back, including the back annotation. I assume there are others that are also comfortable with post processes net lists with C and Perl tools to fix vendor bugs and to implement design requirements the vendor tool chain can not handle directly. In comes down to understanding the process you have, the changes needed to effect the desired results, and documenting the modified process carefully. Post processing even Gerber files is very common. PCB houses used to do it regularly to adjust soldermasks and still do it for panalizing and inserting dead or active copper to manage plating density. Again, managed editing of the bit stream to finished product. For years we used to post process C compiler output to fix known bugs on binary compiler products, and to do custom peep hole optimizations for specific target architectures. We used to use perl scripts to insert a new wrapper for C coded interrupt routines instead of having a lame asm wrapper. Of course, you can always bug report it, and wait till the next release to continue development or get the bugs fixed in the field. Everyone has there own comfort level and standards.Article: 91763
Hello, when I restart my simulation the little blue arrow is missing in the VHDL-testbench source window during single stepping. Transcript pane shows the number of breakpoint, so the arrow should be visible. Any hint? Thanks and kind regards UdoArticle: 91764
This may be related to the way in which the VHDL files are ordered. Please refer to this post as it may be relevant. http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/32e686e201ce78ab/57040b828259c463?lnk=st&q=group:comp.arch.fpga+author:subroto&rnum=121&hl=en#57040b828259c463 Hope this helps, Subroto Datta Altera Corp. "Bryan" <altras@yahoo.com> wrote in message news:0sSdnQzX7ftqbOneRVn-rw@giganews.com... >I am currently doing a research project that involves simulating a > oggvorbis codec on quartus2 V5. > > My source files were taken from a "oggonachip" porject. They developed > their system on the LEON platform and simulated it using TSIM. > > My problem is on porting the codec core (VHDL code) to Quartus it keeps > falling over during compilation. The error message states that it cannot > find the library files which of course I have already added to the > project. > > Can anyone give some insight into why these library files are invisible to > Quartus? > > Any help would be appreciated. > > Bryan > > >Article: 91765
"Jordi" <a80x86@hotmail.com> wrote in message news:1131736588.556776.166780@f14g2000cwb.googlegroups.com... > I've been thinking about two months in buying a FPGA KIT and I've > finally decided to buy this board > http://www.digilentinc.com/info/XUPV2P.cfm . I don't know if it's a > good election. I'm sure it will be fine. I chose the BurchEd B5 board. http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm It just gives you an FPGA and a few essentials. Thus you don't pay for features that you do not need or want. If you want a feature, there are expansion boards for each. http://www.burched.biz/products.html The kind of projects I make, I want all the pins free for my application, not tied to on-board features I don't want. With the B5, you could for example buy expansion boards for more than one VGA port, keyboard port, mouse port, etc. It is a lot more flexible.Article: 91766
How are you doing your byte alignment and your framing? Are you meeting the minimum transition density for the CDR? Have a look at Xilinx's Aurora design as a starting point. Cheers, Meng Jdon wrote: > Hello, > I currently work on Rocket IO in vertex II pro with eval board. > I succeed loopback test in parallel mode, but when I extend to the serial > path, > it didn't work quite well. In particular, > When push the reset button, everything become chaos. > So, I have to push it several times to get the system back. > Once it get back, it receives data correctly. > > I couldn't find the mistake. > I terminated SMA and gave reset signal after dcm phase is locked. > Does anybody has any reference code to start with ? > > Any inputs will be appreciated. > > Jdon.Article: 91767
Some weeks ago I posted a question, the answer turned out to be a dodgy SDRAM controller. Any that's working well now [runs out and hugs tree]. However at the time I suspected Kingston ValueRAM which turned out to be unfounded. However there is something very strange about them. They seem to be built, not only using re-painted chips but having them two high. The modules we thought had sixteen chips (plus prom) in fact has thirty two when you look more closely. A few pins don't connect between the two decks and there seems to be a wafer in between. Of course this does put twice the capacitive loading on the control lines which wouldn't help if we wanted to run at a decent speed. Am I being paranoid are do they do some sort of re-manufacturing using dodgy chips by perhaps fusing data lines on bad chips to end up with a module that works properly ? JonArticle: 91768
>Of course this does put twice the capacitive loading on the control >lines which wouldn't help if we wanted to run at a decent speed. Am I >being paranoid are do they do some sort of re-manufacturing using >dodgy chips by perhaps fusing data lines on bad chips to end up with a >module that works properly ? It's a reasonably common hack to get 2x as much memory on a stick. I've seen it used on servers where they really really want more memory. You have to decide if it works for your application. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 91769
>Does anyone have some advice for the fastest say to get many MBytes of >data from a Spartan3 fifo to the hard disk of a PC via usb. I assume >that it is a combination of the best USB interface next to the FPGA and >perhaps a USB chipset in the PC that can do some very clever DMA. >I don't want to mess with custom RAID stuff I just want to dump it to a >standard hard disk & controller. How fast do you expect to go? How fast is your disk? How fast is your USB? How fast is your PCI? My guess is that your disk is the limiting factor. If your PCI bus is twice as fast as your disk, then you can read the bits into memory and write them out to disk. If you have a driver for your USB gismo, that's probably the simplest overall. Write some hack code to test/measure it. If anybody needs it, I'll dredge out some linux/unix code that I used to measure disk transfer rates. (Hint: The outside edges are much faster than the inside edges.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 91770
Hi, thanks for the answers. I've seen that buying the digilent board is cheaper than buying another board and expansion boards but it's true that it have less free pins. I hope that with three expansion ports plus 60 digital i/o pins will be enough. About the usb, I was referring to the usb expansion board.I don't know if this board is only to connect the board to a host or can act as a host,I mean if this module is to connect the board to a computer or connect usb devices like pendrives to the board.I'm interested in the second option or if it's possible in both options.This expansion board has the Cypress CY7C68013 USB controller. Thanks to all again, JordiArticle: 91771
Hi, I'm tring to use my PCI core, with AVNET's Spartan3 400 evaluation kit. What value should have 'Drive strenght' & 'Slew rate' in constrains? Currently drive strenght is 12mA which is default for PCI33_3.3V. But betwen FPGA and PCI slot there are level translators 3.3V->5V, so maybe should be 24mA, or somethig else? Board's documentation states that, board is not 100% compilant to the PCI specification but should works in most systems. Anybody knows in what areas this board is not 100% compilant? And at which systems don't work? Currently I'm tring use it with BX based motherboard. And actually system don't boot up. When I've try on NForce3 chipset motherboard system have worked, but my board haven't been detected. Best Regards Krzysztof PrzednowekArticle: 91772
We use bus switches in our PCI development boards and they are a good solution. You should not have to alter your drive because they are in series. A typical bus switch is usually represents a series resistance of about 5 ohm or less and generally does not have much effect. Timing wise most are quoted with a through propagation time of less than 250 pS. As to compliance you probably find it is either the capacitive load, or the trace length from the connector that don't meet the specification. We have never seen or heard of an issue with our own boards when using bus switches in the PCI interface. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 PCI Development Board. http://www.enterpoint.co.uk "Krzysztof Przednowek" <nospam@gazeta.pl> wrote in message news:dl4lej$ham$1@inews.gazeta.pl... > Hi, > I'm tring to use my PCI core, with AVNET's Spartan3 400 evaluation kit. > What value should have 'Drive strenght' & 'Slew rate' in constrains? > Currently drive strenght is 12mA which is default for PCI33_3.3V. But > betwen FPGA and PCI slot there are level translators 3.3V->5V, so maybe > should be 24mA, or somethig else? > Board's documentation states that, board is not 100% compilant to the > PCI specification but should works in most systems. Anybody knows in > what areas this board is not 100% compilant? And at which systems don't > work? Currently I'm tring use it with BX based motherboard. And actually > system don't boot up. When I've try on NForce3 chipset motherboard > system have worked, but my board haven't been detected. > > Best Regards > Krzysztof PrzednowekArticle: 91773
"Krzysztof Przednowek" <nospam@gazeta.pl> schrieb im Newsbeitrag news:dl4lej$ham$1@inews.gazeta.pl... > Hi, > I'm tring to use my PCI core, with AVNET's Spartan3 400 evaluation kit. > What value should have 'Drive strenght' & 'Slew rate' in constrains? > Currently drive strenght is 12mA which is default for PCI33_3.3V. But > betwen FPGA and PCI slot there are level translators 3.3V->5V, so maybe > should be 24mA, or somethig else? > Board's documentation states that, board is not 100% compilant to the > PCI specification but should works in most systems. Anybody knows in > what areas this board is not 100% compilant? And at which systems don't > work? Currently I'm tring use it with BX based motherboard. And actually > system don't boot up. When I've try on NForce3 chipset motherboard > system have worked, but my board haven't been detected. > > Best Regards > Krzysztof Przednowek 1) does the board worj when you use Avnet ref design image ? 2) the 24ma would not help, you have some problem with your core that is the reason for the freeze * the 3.3 <> 5V translators dont much matter * the not fully compliant most likely is also not a problem at all ! make sure you have "unused IOB FLOAT" in the bitgen options or some unused PCI pin may get pulled and I suggest you start testing and analyzing some existing and working PCI design before trying your own, and for your own core make sure it works in testbench http://ebook.openchip.org/ there is included a very simple PCI core that we have verified on several boards - I am pretty sure it would work as soon as you setup the .ucf pin locations properly AnttiArticle: 91774
ISE 7.1 will automatically convert .npl to .ise project, so a hack would be to create a .npl as you would and then let the tool deal with the format. HTH, Jim "Duane Clark" <dclark@junkmail.com> wrote in message news:BF8df.10674$BZ5.4399@newssvr13.news.prodigy.com... > sharpa17@gmail.com wrote: > >>From time to time I'm given a Xilinx project directory (project file, > > ucfs, cores, source) and have to add my own components to the project. > > Is there a way to add files to a Xilinx ISE 7.1 project with a script > > file or the command line instead of using the "Add Source ..." option > > in the Project menu? > > I don't have an answer. But since I am still annoyed about it...;) Up > through ISE6.3, this was trivial to do, because the project file was > plain text. I frequently added and removed things with a text editor, > which I found to be easier than the "Add Source ..." stuff. Then someone > decided to to change to a binary file for ISE 7.1 :-(
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z