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"Eli Hughes" <emh203@psu.edu> schrieb im Newsbeitrag news:dk5ukn$1cda$1@f04n12.cac.psu.edu... > Antti: > > Any Pre-release information on your solution??? :-) > unless some new silicon solution becomes available: 1) Lattice LFXP3(or 6) 2) documented standard pinout(s) for several packages 3) specialized IP cores to support different boot media 4) pre-compiled bit streams for common scenarios so basically you look up the 'standard' connection for the config interface and boot media and then design in an Flash FPGA. Later you can either use or precombiled solution or modify it for your application. At the first step its just agreeing on 'standard' pin mapping for the Flash FPGA that is used as the config engine. As the configurator itself is upgradeable there is nothing that can go wrong. There is some work todo to support different NV media and some JTAG specific stuff, but thats not so complicated actually. Sure for booting from file system the config chip will have some small specialued microcontroller as well.Article: 91176
langwadt@ieee.org wrote: > Jim Granville skrev: > > >>Marco wrote: >> >>>sorry for my terrible scheme. >>> >>>Please watch the picture at the link: >>> >>>http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif >>> >>>That should be more clear. >>> >>>I thought that I could replace the 1-bit dac using a LVCMOS25 out pin >>>(without dac because it is only 1 bit) and connecting it to the negative >>>input of LVDS25. >>> >>>What do you think about it? >>> >>>Is it possible? >> >>You need to do some simple maths: >>16 bits on 3.3V, is a LSB of ~50uV, so if you want to >>achieve 16 bit ADC performance, your system must be >>able to resolve to <50uV, and generate voltage to better >>than 50uV, in stability/noise. >> >>Now, look in the data sheets, for any units uV ? >> >>FPGAs are NOT designed as voltage-domain devices, they >>are time-domain devices. >> >>You need these voltage-domain components, added to a FPGA >> >>** Precision Voltage reference >>** Analog Switch - GND-VREF toggling >>** Precision resistors - Min of 2 >>** Integrator = Performance OpAmp + Correct Capacitor >>** Stable Clock source >>++ Comparitor >> >>The last item, you just MIGHT be able to use LVDS, if you >>are carefull with common mode range, and integrator amplitude. >> >>Build it first with an external one, then try and remove when >>it is ALL working to > 16 bits. >> >>In operation, think of a SD-ADC as simply a charge balancing system, >>that makes a heap of Go-Up / Go-Down decisions ( one every clock) >>and then totals (average) those over a great many clocks. >> >>It relies on the integrator being good enough, that it really does >>charge balance. >> >>-jg > > > Assuming the threshhold for LVCMOS inputs are close to Vcco/2 with > little hysteresis and LVCMOS outputs are close to 0-Vcco outputs. I > wonder how > well something like this would work? > > | FPGA > R R | /| > Vin >--/\/\/--+--/\/\/--|-| |-- > | | \| > | | > | | |\ > +---------|-| |-- > | | |/ > === | > |C > _|_ > > > If the Vcco for the bank is from a seperate source, how well will it be > isolated from the rest? That will work, but nowhere near 16 bits - this is good for in the region of 5-8 bits. [We have used this for Low res designs ] Problems are Vth is part of the Eqn, and the simple RC lacks the long term memory of a true integrator, so you find that linearity at the extreme ends is quite poor. ie it is not true charge-balancing -jgArticle: 91177
Antti Lukats wrote: <snip> > sneak preview: on my harddisk I have a tool I call 'Logic Assembler' it can > serve as front end for almost any FPGA/PLD for what the vendor fitter/mapper > exists. Hi Antti, Care to post some code examples ? Output format(s) ? -jgArticle: 91178
Falk Brunner wrote: >> fifo_data <= X"AA4F"; > AFAIK this works only if the bus width is a integer multiple of four. Yes, it does, which is *really* annoying!!! Why they dont allow something like... foo(4 downto 0) <= X"1F"; is beyond me!?! Regards, MarkArticle: 91179
"Antti Lukats" <antti@openchip.org> writes: > to my surprise Avnet claimed that they have shipped about 400 s3e kits and That's their own XC3S100E board, not the Xilinx starter board with the XC3S500E.Article: 91180
"Antti Lukats" <antti@openchip.org> writes:
> as the ISE 8.1 is expected this months and EDK 8.1 in December I wonder if
> some pre release info is already available, eg what is improved, etc..
I'm hoping for:
* supported on Red Hat Enterprise Linux 4 (vs. RHEL3)
* Parallel Cable 4 and Platform Cable USB support on Linux 2.6.x
* Parallel Cable 4 and Platform Cable USB support on 64-bit Linux
* ISE Simulator on Linux
But I don't have any information about 8.1i, so I have no idea whether they've
done any of that.
Eric
Article: 91181"Weng Tianxiang" <wtx@umem.com> writes: > Why are there two patents with same title? I haven't looked at those two patents, but it's common for this to happen. A patent application will be split into two or more parts, because the patent examiners think that there are independently patentable concepts involved. I've seen one that was split into many pieces of which more than a dozen were actually issued as patents, all with the same title. If you want to know the difference between the two, you'll have to compare the claims.Article: 91182
Mark McDougall wrote:
> Yes, it does, which is *really* annoying!!!
A dog barking all night or
an IRS audit is *really* annoying.
I can tolerate
foo(4 downto 0) <= "11111"; -- or
foo(4 downto 0) <= "1" & x"F";
to get compile time width checking
on all vectors.
-- Mike Treseler
Article: 91183Hi, I just started to learn FPGA (xilinx) with ISE 7.1 and ModelSim XE III. If I want to use microblaze or other IP cores like the one from opencores.org, do I need EDK? //Article: 91184
For microblaze, yes.Article: 91185
A FPGA which you cant reconfigure ( Not reliably atleast) is "ASIC-like" to me. Anyway i wouldn't to get into a discussion of semantics. I said it would lower unit cost, nothing else. I just showed him the links, he can take it from there. KunalArticle: 91186
Mike Treseler wrote: > I can tolerate > foo(4 downto 0) <= "11111"; -- or > foo(4 downto 0) <= "1" & x"F"; > to get compile time width checking > on all vectors. Warning #1034: X"1F" width 8 truncated to width 5 in assignment. Regards, MarkArticle: 91187
Hi I just got two ML403 boards. 2nd board when turned on with the cf card in the Error 1 LED is displayed. There is no lcd output and VGA output seems scrambled. The 1st board works as it should as described in getting started guide. Does this mean that this 2nd board is bad? regards. -- ---------------------------------------------- Posted with NewsLeecher v3.0 Final * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ----------------------------------------------Article: 91188
"Kunal" <kunal.shenoy@gmail.com> schrieb im Newsbeitrag news:1130816627.203956.47920@o13g2000cwo.googlegroups.com... > For microblaze, yes. > for EDK IP Cores, YES. but there is also a free opensource version of microblaze on opencores as well. AnttiArticle: 91189
Marco wrote: >>Marco, >>I am afraid not. While the input circuit is differential, the rest of a >>LVDS buffer is optimised for digital performance, and not for the >>characteristics we require in a good operational amplifier. >>A LVDS buffer would make a worse integrator than the cheapest op. amp. so >>why bother? >> >>Regards, >>John > > > Hi John, > sorry for my terrible scheme. > > Please watch the picture at the link: > > http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif > > That should be more clear. > > I thought that I could replace the 1-bit dac using a LVCMOS25 out pin > (without dac because it is only 1 bit) and connecting it to the negative > input of LVDS25. > > What do you think about it? > > Is it possible? > > Many Thanks > Marco > > Marco, Unfortunately, the DAC output voltage needs to be very well defined and noise-free, even though it is derived from a one-bit value, and no digital output is able to achieve this. I don't think there is any chance of realising CD-quality (16-bit) audio by trying to make a digital chip perform any analog functions at all. Digital noise on the ground and supply lines for example make it a hopeless job at the quality level you want. If it is essential to use a single chip, you could investigate the Lattice Semiconductor programmable combined analog/digital chips. Regards, JohnArticle: 91190
Thanks everyone for the help! I'll let you know when I get something going =) Ben "Antti Lukats" <antti@openchip.org> wrote in message news:dju0f3$gg9$1@online.de... > "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> > schrieb im Newsbeitrag news:djkmeg$mdo$1@sunnews.cern.ch... >>I know this isn't exactly comp.arch.cpld... >> >> does anyone know of a COTS solution for programming a (Xilinx) CPLD >> without using PC + Windows + Impact etc etc. (a stand alone chunk of >> hardware with a way for me to give it a set of bit files and a Program >> button would be nice) > > small uclinux modules sell for less than 100EUR. > it takes a few hours to get XSVFplayer to work there. > I use it in desing to program the XC9572XL, the mdoule we used was from > www.dilnetpc.com coldfire based, > but the production has not changed to use small fpga linux modules > (microblaze uclinux) > www.hydraxc.com > > antti >Article: 91191
Hi, I've got a problem which has me stumped. We've got a design that actually *runs* in real hardware. I'm in the process of adding the block to an existing testbench that contains other FPGAs. In the new design (Cyclone II) is a PLL, input frequency 24MHz. I'm generating the clock input in the testbench (VHDL). Two output clocks are used, C1 & C2, both 112MHz (slight phase difference). I've imported the .VHO output into the testbench, together with the cycloneii_atoms and cycloneii_components files. I should also add that the altera_mf & 220pack files are also in the project (for other modules). But, when I simulate the design, C1 & C2 are driving 'X'. Looking inside the PLL, it's not locking. According to the doco, it should lock in (IIRC) 2-10 cycles - I'm simulatng for *thousands* of cycles. And the simulation resolution is set to 1ps. I've also tried eliminating the phase offset for C2. Any ideas what I could be doing wrong? Anyone else had problems simulating cycloneii PLLs? FWIW I've had no problems in the past with cycloneii pll simulation, although that project did *not* include altera_mf and 220pack files. Regards, MarkArticle: 91192
"John Monro" <johnmonro@optusnet.com.au> wrote in message news:43671713$0$25854$afc38c87@news.optusnet.com.au... > Marco wrote: >>>Marco, >>>I am afraid not. While the input circuit is differential, the rest of a >>>LVDS buffer is optimised for digital performance, and not for the >>>characteristics we require in a good operational amplifier. >>>A LVDS buffer would make a worse integrator than the cheapest op. amp. so >>>why bother? >>> >>>Regards, >>>John >> >> >> Hi John, >> sorry for my terrible scheme. >> >> Please watch the picture at the link: >> >> http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif >> >> That should be more clear. >> >> I thought that I could replace the 1-bit dac using a LVCMOS25 out pin >> (without dac because it is only 1 bit) and connecting it to the negative >> input of LVDS25. >> >> What do you think about it? >> >> Is it possible? >> >> Many Thanks >> Marco > Marco, > Unfortunately, the DAC output voltage needs to be very well defined and > noise-free, even though it is derived from a one-bit value, and no digital > output is able to achieve this. > > I don't think there is any chance of realising CD-quality (16-bit) audio > by trying to make a digital chip perform any analog functions at all. > Digital noise on the ground and supply lines for example make it a > hopeless job at the quality level you want. > > If it is essential to use a single chip, you could investigate the Lattice > Semiconductor programmable combined analog/digital chips. > > > Regards, > John I understand... so a way to do it could be buying a analog devices ad7400 (isolated sigma delta modulator (1 bit out)) and building the digital filter into the fpga to obtain 16 bit output data. What do you think about it?Article: 91193
On Tue, 01 Nov 2005 17:28:00 +1100, Mark McDougall
<markm@vl.com.au> wrote:
>Warning #1034: X"1F" width 8 truncated to width 5 in assignment.
Here's the deal: The hex notation X"1F" etc was a hack introduced
in VHDL-93 to answer users' concerns that they wanted a simple way
to write hex literals of vector type.
<rant>
The "right" way to do it,
of course, is...
...
use ieee.numeric_std.all;
...
signal vec: std_logic_vector(4 downto 0);
...
vec <= std_logic_vector(to_unsigned(#16#1F#, vec'length));
but that's kinda clumsy, and for some reason no-one ever
gets around to writing this rather trivial procedure:
procedure copy_int_to_slv_signal (
signal v: out std_logic_vector;
n: in natural
) is
begin
v <= std_logic_vector(to_unsigned(n, v'length));
end;
so that I can now write
copy_int_to_slv_signal(vec, #16#1F#);
</rant>
So the VHDL-93 writers gave in to popular opinion, but tried
to do it without adding too much hidden magic. Consequently
they invented a rewriting rule such that the hex literal X"1F"
is simply macro-substituted with the string literal "00011111"
(each hex digit is replaced with four binary digits in the string).
This of course allows type-compatibility of a hex literal with
any vector whose element type includes the literals '0' and '1',
correctly matching BIT, STD_LOGIC_VECTOR and UNSIGNED among others.
But it forces any hex literal to have a multiple of four bits.
Note that std_logic_textio similarly requires all its
std_logic_vector objects to be a multiple of four bits when
reading or writing in hex.
It really isn't a big deal. Program your way around it by
building a sensible set of application-specific utility
functions and procedures.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 91194Thanks for the nice message. No offence taken, I guess I overreacted a bit. Certainly no need to apologize.Article: 91195
If it's any help I just (last week) ordered a S3E evaluation board through avnet, they said it'll be here tomorrow (2.11) It's not the Xilinx one, but if you _really_ want an S3E, you know where to go... =) Ben "Eric Smith" <eric@brouhaha.com> wrote in message news:qhd5lll09x.fsf@ruckus.brouhaha.com... > "Antti Lukats" <antti@openchip.org> writes: >> to my surprise Avnet claimed that they have shipped about 400 s3e kits >> and > > That's their own XC3S100E board, not the Xilinx starter board with the > XC3S500E.Article: 91196
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:4366a1ff$1@clear.net.nz... > Antti Lukats wrote: > > <snip> >> sneak preview: on my harddisk I have a tool I call 'Logic Assembler' it >> can serve as front end for almost any FPGA/PLD for what the vendor >> fitter/mapper exists. > > Hi Antti, > Care to post some code examples ? Output format(s) ? > -jg > > main output format is vendor specific EDIF input formats supported for now are logic assembler text mode or xilinx ISE schematics. also working on netlist imports from CAE tools. below is test code that work on Atmel FPSLIC starterboard. the output is processed with Atmel Figaro. ---------------------- .vendor atmel .family at94k .library at94k input I output O input I1 output O1 ibuf I_IBUF obuf O_OBUF ibuf I_IBUF1 obuf O_OBUF1 O = O_OBUF.PAD I_IBUF.PAD = I O_OBUF.A = I_IBUF.Q O1 = O_OBUF1.PAD I_IBUF1.PAD = I1 O_OBUF1.A = I_IBUF1.Q ---------------------- really simple.Article: 91197
"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> schrieb im Newsbeitrag news:dk7jil$4n$1@sunnews.cern.ch... > If it's any help I just (last week) ordered a S3E evaluation board through > avnet, they said it'll be here tomorrow (2.11) > It's not the Xilinx one, but if you _really_ want an S3E, you know where > to go... =) > Ben > > "Eric Smith" <eric@brouhaha.com> wrote in message > news:qhd5lll09x.fsf@ruckus.brouhaha.com... >> "Antti Lukats" <antti@openchip.org> writes: >>> to my surprise Avnet claimed that they have shipped about 400 s3e kits >>> and >> >> That's their own XC3S100E board, not the Xilinx starter board with the >> XC3S500E. > > yes I know the avnet board,.I wanted to get it the day it was announced, but at work everybody refuses to talk about s3e. and dont think I can order as private person :( So the only way to get this board would be to pay some friend that orders for his company and then ships it to me. AnttiArticle: 91198
Does the err led blink. Mine does if the cf card is not fully seated. Can you look at the compact flash connector, are any pins bent or broke? Did you try powering up the board with the three position position switch in the middle and left position. This boots the system using the Nor flash and platform flash respectively. Does the UART work at 9600 baud? Lastly, have you tried swapping the compact flash cards? There are files on the ml403 xilinx page to help reload the CF card. Hope this helps =NewmanArticle: 91199
Hi Mark,
We would like to verify the condition that you describe. Please create a
mysupport case so the problem gets logged and escalated. Additionally if you
can email me the Quartus archive of your project along with your simulation
setup that would be useful. Please identify the Quartus version, simulator
tool being used (Modelsim, Native Simulator etc), the waveforms or test
bench being used and the time range in the output waveform where the problem
is being seen.
Hope this helps,
Subroto Datta
Altera Corp.
"Mark McDougall" <markm@vl.com.au> wrote in message
news:43671e2e$0$20453$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Hi,
>
> I've got a problem which has me stumped.
>
> We've got a design that actually *runs* in real hardware. I'm in the
> process of adding the block to an existing testbench that contains other
> FPGAs.
>
> In the new design (Cyclone II) is a PLL, input frequency 24MHz. I'm
> generating the clock input in the testbench (VHDL). Two output clocks are
> used, C1 & C2, both 112MHz (slight phase difference).
>
> I've imported the .VHO output into the testbench, together with the
> cycloneii_atoms and cycloneii_components files. I should also add that the
> altera_mf & 220pack files are also in the project (for other modules).
>
> But, when I simulate the design, C1 & C2 are driving 'X'. Looking inside
> the PLL, it's not locking. According to the doco, it should lock in (IIRC)
> 2-10 cycles - I'm simulatng for *thousands* of cycles. And the simulation
> resolution is set to 1ps. I've also tried eliminating the phase offset for
> C2.
>
> Any ideas what I could be doing wrong? Anyone else had problems simulating
> cycloneii PLLs?
>
> FWIW I've had no problems in the past with cycloneii pll simulation,
> although that project did *not* include altera_mf and 220pack files.
>
> Regards,
> Mark
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