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Jerome: Thanks for the prompt advice. > Using NGC files with ISE works perfectly for me (and i guess for > everybody) > The method for integrating an IP in NGC form is however not obvious : I tested the NGC file by creating another project and placing only the NGC file in that directory. I then placed 3 Verilog files - 1 is top level & the other 2 talks to the NGC'd module. ISE 7.1 sees the hierarchy correctly but can't find the NGC'd module. So when I try to run XST or MAP or Generate Bit file, it always give an error message of Can't find module ( the NGC one ). Verilog has no keywords for external modules. You just instantiate a module and as long as 1 of the files has that module, everything is fine. Is there something else I'm missing ? Is there some secret ISE configuration I need to set ? > ( in VERILOG : i dont know verilog, sorry ) > - put the NGC file in the ISE project directory. JimArticle: 91101
"rk" <stellare@nospamplease.comcast.net> wrote in message news:Xns96FE6565322E1rk@216.196.97.136... > Hi, > > Don't happen to have an LVDS specification (EIA-644) handy and couldn't > find a > freebie on the www. So hopefully someone out there has one. > > Here's the question, I was told that section 4.4.2, & 6 have the fail-safe > requirements. The issue is whether cold sparing capability is an LVDS > requirement. I don't recall it being a requirement but I do want to go to > the > documentation to be sure. > > My design does have cold sparing capability, it's the right thing to do > for > this particular application, so that is not an issue. > > It is critical that the intent of the system designers, who state that > they > want cold sparing capability, be properly documented in the requirements > (many > users geographically and organizationally diverse) to avoid an oops. > Having a > specification buried in a third level referenced document that is not easy > to > obtain is a good opportunity for an oops. > > But if cold sparing isn't part of the EIA-644 specification, then the top > level specification that the systems guys are writing needs to be updated. > > Thanks in advance, > > -- > rk, Just an OldEngineer > "These are highly complicated pieces of equipment almost as complicated as > living organisms. In some cases, they've been designed by other computers. > We > don't know exactly how they work." > -- Scientist in Michael Crichton's 1973 movie, Westworld What is "cold sparing"? I've never heard the term. TCArticle: 91102
When you have to pay a bill by a certain day, or when you have to turn in a paper in school, it always means "before the end of the specified period". So "fourth quarter" means, before December 31. Peter AlfkeArticle: 91103
I was playing with the Xilinx ML403 Virtex 4 board, and the PowerPC demonstration has a licensed IIC hardware evaluation core to communicate with an IIC EEPROM. OK, that sounds reasonable. There are also numerous demo programs that show off the board and Virtex 4 capabilities, which sounds reasonable. Further investigation shows that the iic_eeprom demo program bypasses the IIC core in the demo design via muxes buried in some misc logic in the design, and bitbangs data out to the eeprom via gpio, which does not make much sense to me. Anybody got a clue as to why this was done? -NewmanArticle: 91104
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1130600565.433835.241010@z14g2000cwz.googlegroups.com... > When you have to pay a bill by a certain day, or when you have to turn > in a paper in school, it always means "before the end of the specified > period". > So "fourth quarter" means, before December 31. > Peter Alfke > the Xilinx webshop now only says that the s3e kit is 'targetted' DEC 2005. translated: Xilinx makes NO commitment about the actual availability at all. to my surprise Avnet claimed that they have shipped about 400 s3e kits and that they expect the kit to become available ex stock again. At the time i asked (a few weeks ago) Avnet was not able to ship immediatly. I REALLY REALLY wonder what is the reason why Avnet is already shipping S3e based boards, and Xilinx is 'targetting' DEC 2005 ??? Anybody cares to explain? Antti PS I have an immediate project that requires small low cost FPGA production volumes maybe 500/year. I was considering S3e - but I guess I may have to reconsider and use non Xilinx vendor Altera/Lattice as they can ship their low cost FPGAs. I am still looking at S3e,.but unless I will get some confirmation that low volumes will be available within few months, I have to use alternatives.Article: 91105
"Newman" <newman5382@yahoo.com> schrieb im Newsbeitrag news:1130602784.975606.15260@f14g2000cwb.googlegroups.com... >I was playing with the Xilinx ML403 Virtex 4 board, and the PowerPC > demonstration has a licensed IIC hardware evaluation core to > communicate with an IIC EEPROM. OK, that sounds reasonable. There are > also numerous demo programs that show off the board and Virtex 4 > capabilities, which sounds reasonable. Further investigation shows > that the iic_eeprom demo program bypasses the IIC core in the demo > design via muxes buried in some misc logic in the design, and bitbangs > data out to the eeprom via gpio, which does not make much sense to me. > Anybody got a clue as to why this was done? > > -Newman > haha, Xilinx is bypassing its own license? well as of 'easy' it is actually usually easier and simpler to implement i2c and SPI protocols as bit-bang rahter then learn to the interface to some dedicated hardware. I usually always implement the bit-bang version first as temporary/test solution. And as we all know the most permanent are things we did develop as temporary solutions. So if the 'temporary' solution was used its very likely to stay permanent. I think I also have the IIC EDK core license, but I still use the bit bang mostly. AnttiArticle: 91106
Hi as the ISE 8.1 is expected this months and EDK 8.1 in December I wonder if some pre release info is already available, eg what is improved, etc.. specially EDK, if there are new cores added OPBor PLB DDR2 core as example, is it 8.1? AnttiArticle: 91107
TC wrote: > What is "cold sparing"? I've never heard the term. > If the device is powered off, the I/O's appear as high impedance. Then you can hook two devices together, one as a spare, and power off the one not being used at the time. In the application that I am considering, there are several sections of the system, not all of which are powered all the time, and I don't want to load down the source if I (sink) is powered off. There's probably a more formal definition somewhere. But with typical CMOS I/O, you get a diode to the supply rail which can be problematic (also consider PCI systems with clamp diodes). -- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, WestworldArticle: 91108
Using the DFS to multiply a clock leaves some questions for me: The data specifies cycle-to-cycle jitter & period jitter at the input. A period jitter of +-1 ns seems not plausible to me. From what ideal clock edge is the +-1ns specified ? From the clock specified in the clocking wizard ? Is the clock frequency specified there getting into the device configuration ? For a 50ns period input +1ns is +2%. This isn't plausible to me as timing of the device changes more than 2% with temperature and supply voltage. The question is rather: How would the DFS track a changing input frequency (and device temperature variations and device supply voltage variations of course)? Is there a limit on the speed of this change, before the DFS "unlocks" ? +-1ns per input clock period ? For Example a input clock 25ns period, switching to 24ns period in one cycle A "traditional" PLL with Phase comparator, loop filter & vco has a loop bandwidth, determining the speed of tracking. So it's behaviour would be some kind of step response of the output frequency. How would the DFS behave ? Can the DFS be used to multiply a clock coming from a variable source ? What's the tracking speed (loop bandwidth)? Raymund HofmannArticle: 91109
Hi again, Put the NGC file in the same directory than the source file(s) instantiating it Hope that helps "James Bond" <sjjmacls@dacafe.com> wrote in message news:o8M8f.6820$BZ5.4633@newssvr13.news.prodigy.com... > Jerome: > > Thanks for the prompt advice. > >> Using NGC files with ISE works perfectly for me (and i guess for >> everybody) >> The method for integrating an IP in NGC form is however not obvious : > > I tested the NGC file by creating another project and placing only the NGC > file in that > directory. I then placed 3 Verilog files - 1 is top level & the other 2 > talks to the > NGC'd module. > > ISE 7.1 sees the hierarchy correctly but can't find the NGC'd module. > So when I try > to run XST or MAP or Generate Bit file, it always give an error message > of > Can't find module ( the NGC one ). > > Verilog has no keywords for external modules. You just instantiate a > module and > as long as 1 of the files has that module, everything is fine. > > Is there something else I'm missing ? Is there some secret ISE > configuration I need > to set ? > >> ( in VERILOG : i dont know verilog, sorry ) >> - put the NGC file in the ISE project directory. > > Jim >Article: 91110
The answer to your question is NO. The PIPE specification is not part of the PCI Express Base Specification. It is not even governed by the PCI-SIG. It is a "suggestion" from Intel for a logical interface between the MAC and the PHY, in the physical layer of a PCI Express component. I think the idea is to suggest that people designing PHY functions use a common interface, to foster portability between PHY vendors/implementations. As you note, it describes the logical behavior of such an interface and doesn't discuss anything else. At the time it was written, I don't think they were even contemplating external PHY devices like the Philips PX1011a. However, you can imagine that someone wanting to do an external PHY would probably take the PIPE specification as a reasonable starting point for their interface behavior. What electricals to use? Whatever you want, as long as it works and you think your potential customers will be satisfied. Philips used SSTL2, as you point out, which seems to work well with, say, a Spartan3 FPGA from Xilinx. So, then, if you are using an external PHY, you need to evaluate your options and then select one -- and design to the specifications in the vendor's data sheet. Eric Crabill Xilinx, IncorporatedArticle: 91111
Marco, This any good? http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870 Ciao, Syms. "Marco" <marcotoschi@nospam.it> wrote in message news:djtebp$m2k$1@nnrp.ngi.it... > Hallo, > is there anybody who can help me to find out the scheme of a 16-bit > delta-sigma adc? > > I have already made some searches into google but I don't have found > interesting informations. >Article: 91112
My 2 cents: The first two cases are identical. The only difference is that you are naming the nets coming out of the registers in the second case. So no difference in terms of logic resources used. In the third case, the implementation tools have simply optimized away the logic since you didnt use them. Tha can be only the only explaination in the reduction from 51 LUTs to 4!Article: 91113
> in the "XtremeDSP for Virtex-4 FPGAs User Guide", on > Page 56 are in Table 1-13 some interesting functions > mentioned, like AND and XOR and so on. > Does anyone know how these functions are accomplished? AND function: result is 1 when all the input bits are 1, otherwise the result is 0. So if you add 1 to the input, what will you get (hint: carry out)? XOR: a = 0, b = 0, result = 0 a = 0, b = 1, result = 1 a = 1, b = 0, result = 1 a = 1, b = 1, result = 0 if you add a and b, you get a = 0, b = 0, result = 00 a = 0, b = 1, result = 01 a = 1, b = 0, result = 01 a = 1, b = 1, result = 10 result(0) is what you need. HTH, JimArticle: 91114
On Sat, 29 Oct 2005 18:34:14 +0200, "Antti Lukats" <antti@openchip.org> wrote: >"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag >news:1130600565.433835.241010@z14g2000cwz.googlegroups.com... >> When you have to pay a bill by a certain day, or when you have to turn >> in a paper in school, it always means "before the end of the specified >> period". >> So "fourth quarter" means, before December 31. >> Peter Alfke >> > >the Xilinx webshop now only says that the s3e kit is 'targetted' DEC 2005. > >translated: Xilinx makes NO commitment about the actual availability at all. > >to my surprise Avnet claimed that they have shipped about 400 s3e kits and >that they expect the kit to become available ex stock again. At the time i >asked (a few weeks ago) Avnet was not able to ship immediatly. > >I REALLY REALLY wonder what is the reason why Avnet is already shipping S3e >based boards, and Xilinx is 'targetting' DEC 2005 ??? > >Anybody cares to explain? > >Antti > >PS I have an immediate project that requires small low cost FPGA production >volumes maybe 500/year. I was considering S3e - but I guess I may have to >reconsider and use non Xilinx vendor Altera/Lattice as they can ship their >low cost FPGAs. I am still looking at S3e,.but unless I will get some >confirmation that low volumes will be available within few months, I have to >use alternatives. > Well considering the Xilinx webshop doesn't even have any S3 devices in stock, I wouldn't hold my breath waiting for S3e.Article: 91115
Let's straighten this out on Monday! Peter Alfke, Xilinx ApplicationsArticle: 91116
Hi, Why are there two patents with same title? What are their major purposes? For example: Altera patents: 6,859,065 Use of dangling partial lines for interfacing in a PLD 6,653,862 Use of dangling partial lines for interfacing in a PLD In the latest patent, it contains the following statements: This application is a continuation of U.S. patent application Ser. No. 10/140,911 filed on May 6, 2002, now U.S. Pat. No. 6,653,862, which claims priority to U.S. Provisional Application Ser. No. 60/289,346, filed May 6, 2001, and entitled "Use of Dangling Partial lines for Interfacing in a PLD." Thank you. WengArticle: 91117
The first claim in 6,859,065 is: A programmable logic device (PLD), comprising: a plurality of logic elements (LE's) arranged in an array; a signal routing architecture including a plurality of signal routing lines to route signals among the LE's; and a plurality of signal drivers along each of the signal routing lines, wherein for each of the signal routing lines, [*] the drivers along that signal routing line are spaced along that signal routing line; [**] for each of a first set of at least some of the signal routing lines, that signal routing line is substantially interrupted by an interface region such that a partial signal routing line is formed for that signal routing line between the interface region and a driver along that signal routing line from the interface region; and the PLD further comprises an input driver configured to drive from the interface region along the partial signal routing line formed for that signal routing line. In patent 6,653,862 the first claim is the same except it also includes * that signal routing line has an integer N associated with the signal routing line; and ** at an interval of N LE's for that line; So the first claim of the '065 patent is broader than the first claim of the '862 patent.Article: 91118
Hi, Thank you very much. You means if two patents have same titles, usually the later one contains claims broader than ones claimed in the first patent to expand their patent right coverage. 1. Are there any other situations that trigger the repeated patent with same title as previous one? Because I found it is very common to have two patents having the same titles. 2. Is it right that It seems the lawyer who wrote the claims for first patent and missed something is at the fault? May it double the money to support two patents for a long term period? Now I have a question: If a provisional application for patent A that contains patent B partial new material is filed earlier than provisional application for patent B, can I use the continuation-in-part to claim priority data of patent A for patent B? Or I will lose the right for patent B that is disposed earlier in patent A application? What is the best strategy for two provisional patent applications that have overlapped materials to file with the larger one being ready first. WengArticle: 91119
"Symon" <symon_brewer@hotmail.com> wrote in message news:4363c605$0$41142$14726298@news.sunsite.dk... > Marco, > This any good? > http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870 > Ciao, Syms. > "Marco" <marcotoschi@nospam.it> wrote in message > news:djtebp$m2k$1@nnrp.ngi.it... >> Hallo, >> is there anybody who can help me to find out the scheme of a 16-bit >> delta-sigma adc? >> >> I have already made some searches into google but I don't have found >> interesting informations. >> > > Very Good!!! Many Thanks MarcoArticle: 91120
In message <1130638555.303033.171900@g49g2000cwa.googlegroups.com>, Weng Tianxiang wrote: > > What is the best strategy for two provisional patent applications that > have overlapped materials to file with the larger one being ready > first. > Note that the way the US does patents is different from much of the rest of the world so answers may depend on what you want to file and where. -- Dave mail da ve@llondel.org (without the space) http://www.llondel.org/ So many gadgets, so little time...Article: 91121
"Symon" <symon_brewer@hotmail.com> wrote in message
news:4363c605$0$41142$14726298@news.sunsite.dk...
> Marco,
> This any good?
> http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870
> Ciao, Syms.
> "Marco" <marcotoschi@nospam.it> wrote in message
> news:djtebp$m2k$1@nnrp.ngi.it...
>> Hallo,
>> is there anybody who can help me to find out the scheme of a 16-bit
>> delta-sigma adc?
>>
>> I have already made some searches into google but I don't have found
>> interesting informations.
>>
>
>
Now I'm trying to implement the sigma delta a/d.
The range of my analog input will be from 0 to 3.3V
Here the scheme of delta sigma modulator:
_______ ________ __________
Analog In --|diff.amp.|---|Integrator|---|Comparator|----> dig.filter
--| | | | |with gnd |
|
|
|
| ________ |
---------| 1-bit dac|-------------------------
| |
It's not clear the function of 1-bit DAC. If it's only 1 bit it should be as
a switch, so,
in my case, a comparator connected to ground.
And also diff.amp should be a comparator?
I think I'm making a mistake.
Could you explain where is wrong?
Many Thanks
Marco
Article: 91122
Mike wrote:
> Hi all,
>
> I'm trying to put together a picture of how Xilinx FPGAs evolved,
. . .
I have two items which may help, please email ed at my domain if you'd like
to discuss:
The first edition of "The Programmable Gate Array Handbook" (c) 1986 with
prices for XC2064, EP310 & EP320 penciled inside the cover.
A PAL video in which Brad Fawcett gives a full technical introduction to
the FPGA and associated design techniques. The video mentions 2k and 3k
parts, the latest mentioned date is Feb 1988.
When we updated our 3k designs we used 5200 series parts, but I'm not sure
where these fit into the Xilinx development path.
Ed Coombs.
--
murray-microft ltd
Article: 91123Marco skrev: > "Symon" <symon_brewer@hotmail.com> wrote in message > news:4363c605$0$41142$14726298@news.sunsite.dk... > > Marco, > > This any good? > > http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870 > > Ciao, Syms. > > "Marco" <marcotoschi@nospam.it> wrote in message > > news:djtebp$m2k$1@nnrp.ngi.it... > >> Hallo, > >> is there anybody who can help me to find out the scheme of a 16-bit > >> delta-sigma adc? > >> > >> I have already made some searches into google but I don't have found > >> interesting informations. > >> > > > > > > > Now I'm trying to implement the sigma delta a/d. > The range of my analog input will be from 0 to 3.3V > > Here the scheme of delta sigma modulator: > > _______ ________ __________ > Analog In --|diff.amp.|---|Integrator|---|Comparator|----> dig.filter > --| | | | |with gnd | > | > | > | > | ________ | > ---------| 1-bit dac|------------------------- > | | > > It's not clear the function of 1-bit DAC. If it's only 1 bit it should be as > a switch, so, > in my case, a comparator connected to ground. > And also diff.amp should be a comparator? > > I think I'm making a mistake. > > Could you explain where is wrong? > > Many Thanks > Marco your scheme is hard to read, you probably used tabs instead of spaces. the DAC should output 0v and 3.3V, your comparator should have a 3.3/2= 1.65V reference -LasseArticle: 91124
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:43626d62$1@clear.net.nz... > Austin Lesea wrote: > > Antti, > > > > Selling known bad parts is an interesting concept. > > > > No one has figured out how to do that. > > ?! - So Xilinx have no errata, on any devices ? Wow ? > I'd say pretty much everyone sells bad silicon. > > As to selling 'bad by device' [unknown bad parts], > that too has been done in Russia. > > NAND flash that maps bad sectors in the FAT, is also > 'bad by device', so this is not a new, or novel, idea. > > The risk to Xilinx is of the parts being relabeled, and > sold as genuine, plus all the traffic on how to get > these bad xilinx devices to limp along. > ie bad for the brand, plus imagine if someone > (like Antti) actually got really good at this, and found > that a large chunk of sales switched to the low yield > El-Cheapo parts - not good for Xilinx's shareholders > either.... > > So I cannot see it happening, but not for technical reasons. > Easypath is the closest Xilinx will get. > > -jg > Hi Jim your knowledge still amazes me ! to put thing stright I am not from russia and have nothing todo with them. same for my home country that happened to be occupied by russia for some time. But actually I did enjoy that times as it allowed to travel for virutally free all round the russian territories. and yes, the russian fabs did sell bad silicon. namly 16kbit, 64kbit and 256kbit DRAMs chips did have special markings indicating if 1) full array is OK 2) lower or upper half is OK 3) single quarter of array is OK re device re-branding, I guess that is mostly popular in some far east countries that are known to have relabelled intel CPUs at least. the bad devices idea there are many levels of bad. and different used for bad silicon. 1 like testing of the soldering process. 2 boundary scan test 3 power supply testing all those can be done with very badly damaged silicon. large altera Stratix devices cost 9,000 USD a piece, I imagine it would be way reasonable to buy bad silicon to pre test a board that is going to be used for a device that cost almost 10K USD a piece. Antti PS some posts make me smile, thanks Jim :) there isnt a smile on face most of the time specially when I am in thinkmode... what is most of the time, and then I look like: http://www.truedream.org
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