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fpgabuilder wrote: > Its interesting to learn about the disabling the unused inputs - how > are the inputs disabled? I am assuming a FET. In that case wouldn't > there still be some leakage especially in a 90nm process? As far as gate leakage is concerned you worry about a few million sram bits in the FPGA but not about a few hundred inputs. After all that's only nA per Transistor. (BTW: Pulling the inputs to 0 does not with gate leakage either. There are as many input transistors connected to GND as there are conneced to VCC) But it is important that the input gates are not switching because of the random input voltage. Disabling the input gates (e.g. by using a NAND instead of an inverter) reliably fixes that. Kolja SulimmaArticle: 90851
Kolja Sulimma wrote: > fpgabuilder wrote: >> Its interesting to learn about the disabling the unused inputs - how >> are the inputs disabled? I am assuming a FET. In that case wouldn't >> there still be some leakage especially in a 90nm process? > > As far as gate leakage is concerned you worry about a few million sram > bits in the FPGA but not about a few hundred inputs. After all that's > only nA per Transistor. (BTW: Pulling the inputs to 0 does not with gate > leakage either. There are as many input transistors connected to GND as > there are conneced to VCC) > > But it is important that the input gates are not switching because of the > random input voltage. Disabling the input gates (e.g. by using a NAND > instead of an inverter) reliably fixes that. Agree, mostly. For some FPGAs, I've seen non-logic levels on the inputs result in on order of 1 mA/input. For some special pins like global clock pins, there could be on order of 50 mA for a non-logic level. Cheers, -- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, WestworldArticle: 90852
Hi Jim, Xilinx synchronization FIFO problems show in just a few minutes. There used to be a problem with the previous release of their core generator, the latest one works fine in the lab. Just make sure you always have the latest version of the core generator to avoid headaches in the lab that would not show in simulation. RAULArticle: 90853
I work in a large company. Two years ago, most of our FPGA developments were over budget and schedule. Management wanted us to fix this. We've been successful and today only a few FPGA developments have severe problems. As you can imagine, there's more structure and "process" in the development. However, we have tried hard to keep it reasonable and most of the developers adopt the key elements with only a little whining. There are a few things we're still working and one of these is documentation. All of our developments have a good requirement spec and most can pick up anyone's VHDL and figure out the lower level functions. The element we're missing is the middle level documentation. To me this is a detailed block diagram with enough verbiage or whatever to describe the flow of the design and how the major functions work together. This level of documentation is not being captured in our designs and it becomes tough for another developer to pick up a design and fix anything but the most minor items. No one wants to pay for or create a document that's not immediately useful so I'd rather not force that. Rather than defining something new, I'd like some suggestions on what others do. Is there a document that can be created during the development that answers this and benefits the developer as well? Is there another way to approach this problem? SamArticle: 90854
se wrote:
> The element we're missing is the middle level documentation. To me this is
> a detailed block diagram with enough verbiage or whatever to describe the
> flow of the design and how the major functions work together. This level of
> documentation is not being captured in our designs and it becomes tough for
> another developer to pick up a design and fix anything but the most minor
> items.
I use regression testing, code comments and
source control to cover these problems.
One way to capture theory of operation details
is with multiple levels of closed loop testbenches
that are run between builds.
If I write code that breaks the regression
suite, I debug the problem using the simulator
and then add steps to the test to cover the new code.
Running the testbench and looking at waveforms of interest
is always up to date and better than any other type of
technical documentation for me or for another developer.
All other design documentation is done using
text comments right in the code.
I use simple text with block diagrams like this:
--[foo]---[bar]---[bas]--
and timing diagram snippets like this
--foo ___--__-_-__----
--bar ___-____-_-_-___
My most important code comments consist of a plain
English description of what I expect the module to do.
Here I introduce significant variables and structures
by name, and explain what happens to them.
This gives me a starting point and reference
to use while writing and debugging the code.
If all developers maintain such comments in all
modules, then all levels are covered.
In any case, there is at least a regression
suite to watch the waves with.
-- Mike Treseler
Article: 90855
gallen wrote:
> I understand the basic idea. I can see how it solves a lot of problems
> because the time between cycles for an individual thread is long enough
> that you don't have to deal with forwarding or hazards or branch
> prediction or anything like that. Each thread is something of a
> multicycle architecture.
>
Exactly, we do this all the time in DSP to break dependancies.
> Unfortunately it seems that a multi-threaded architecture definitely
> needs a new programming paradigm. I don't think your standard C
> program would map well onto that. (If you were running 4 C programs,
> however, I could see it working quite well). But I suppose that is a
> different sort of problem to face.
>
Typically if a processor is already running some sort of OS with time
sharing of processes, then having to deal with 4 HW threads is not a
big deal except that the threads run at 1/t of clock. But if many of
these PEs are available in each MMU cluster then that is 4N threads. It
gets much more interesting when the MMU introduces its own OS memory
management issues and the language of choice looks like a hybrid of
C/C++ with occam and Verilog.
C gives us structs with data members and usually manipulated by any old
functions, no special logical structure at all.
C/C++ gives us classes to add member functions to member data for
object oriented programming but no concurrency or liveness.
V++ (in development) give us a process which looks just like a class
with added port list and body code that can instance other process
objects ala Verilog.
// monospace
process pname1 (
in .., out ..., // just like Verilog port list, event driven
ints etc ) { // data ports not event driven
data members; // just like C vars in struct
function members; // just like C++ class methods
wires ...; // just like Verilog
process body code; // just like Verilog module body
l1: pname2(.. ); // just like Verilog instance of another
process/module
l2: pname3(.. ); // labels are used to name instances in the
hierarchy
assign ...; // just like Verilog continuous assigns
always { ;;; } // just like Verilog event driven parallel logic
} // usually endmodule
Now a process hierarchy combines C++ class OO structure with an event
driven HDL like structure with some help from processor to support many
threads or processes etc. 1) Data, 2) Objects, 3) Processes.
> Thanks for the info. I may very well look into an architecture like
> this at some point.
>
> -Arlen
regards
John
transputer guy
Article: 90856John, Thank you very much for the insightful description. Is there any chance that you could post some HDL to OpenCores? I am certain that others are as interested as myself in playing with a simple MTA. StephenArticle: 90857
Stephen That will depend on future events. I would like to complete this compiler and finish the remaining opcodes, and MMU first, its a unified compiler + processor project as was the original Transputer. One project makes no sense without the other. I would prefer to make something commercial out of it with some free use for .edu. I am not too worried about time to market since there is lots of work to do and nobody else seems to be interested in doing this. Most seem happy to reinvent the same dead end ST designs and ST languages over and over. If I do put it out in the open, it could be on opencores or whatever, with BSD/MIT license, but it would better for me to exploit this if I can too. Updates here, c.a, c.s.t etc osnews, one day a web home too. John transputer guyArticle: 90858
Hi Pasacco, I take it that you are concerned about the performance degradation of the static timing analysis (STA) results before and after PAR. STA before PAR does not take into account the routing delays within the FPGA which typically account for half or less of the total delay. Pre-PAR STA would only take into account logic delays. So there will be some performace degrdation in post-PAR STA. (source : Constraints Guide > Static Timing Analysis ) To minimize your routing penalty, read Timing Closure - 6.1i 04/07/04 By Rhett Whatcott Senior Course Developer/Trainer Xilinx San Jose available under TechXclusives on xilinx.com. That may help. KunalArticle: 90859
"Rich Grise" <rich@example.net> wrote in message news:pan.2005.10.21.20.44.52.116732@example.net... > On Wed, 19 Oct 2005 09:25:12 -0700, Tim Wescott wrote: > >> Jeorg's question on sci.electronics.design for an under $2 DSP chip got >> me to thinking: >> >> How are 1-cycle multipliers implemented in silicon? > > I don't know how they do it this days, but I do know that with a > whole shitpot load of adders, you could do it in n propagation delays, > where n is the width of whichever operand you arrange to come in > sideways. I almost drew a schematic. You have a set of adders as > wide as operand "A", and its inputs are operand "A" and the "latest" > partial product - and its outputs go to another bank of adders whose > other inputs are either "A" again or 0, and so on - the other operand, > "B", would be presented down the side of the array, deciding which > partial products get added to and which don't. The LSB, of course, > gets sent out as "product", and the carry is the MSB of the next > partial product. They form a parallelogram. > > I just fired up that Xilinx S/W to see what it's got in the way of > symbols, and it already has a 16-bit adder. With 16 of them, and 256 > AND gates, I could build a 16 x 16 multiplier that would have an > answer in about 16 or 17 propagation delays. :-) > <Rich fires up Xilinx ISE...> > > OK, it's gonna be a day or so. Please be gentle, it's my first time. :-) > > Thanks! > Rich There is a app note There are a few fft cores included with ise in logicore http://tinyurl.com/dt68x or <http://www.xilinx.com/xlnx/xebiz/search/searchresult.jsp?searchJSP=/xebiz/search/ipsrch.jsp&_ResultsView=Standard&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&_IPCategory=Digital+Signal+Processing&_IPSubcategory=Transform&_DeviceSupport_2022=virtex4&_DeviceSupport_1127=Spartan-3&_DeviceSupport_1128=CoolRunnerFamily&_DeviceSupport_1967=Virtex-IIProX&_DeviceSupport_1729=Spartan-II-E&_DeviceSupport_1730=XC9500Family&_DeviceSupport_1126=Virtex-IIPro&_DeviceSupport_1728=Virtex-II&_IPProducts_1129=Core&_Vendor_1=Xilinx&_SearchText=&resultNumber=All&Submit+Search.x=72&Submit+Search.y=9> To use the builtin ones (IP cores) new project then add file , select IP(coregen) then wait for it to load the cores. Then configure as required. Depends on which chip family you have selected to which cores are available. Interesting to see that you can get a couple of TI dsps as cores for fpga http://tinyurl.com/8hojt or <http://www.xilinx.com/xlnx/xebiz/search/searchresult.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&category=-1211889&iLanguageID=1&_ResultsView=Standard&_IPSubcategory=DSP+Processor&_IPCategory=Digital+Signal+Processing&_IPProducts=Core> List of xilinx app notes/white papers http://www.xilinx.com/products/design_resources/dsp_central/resource/dsp_resources.htm They claim a 2uS 1024 point fft http://www.xilinx.com/prs_rls/design_win/0254altrabroadband.htm AlexArticle: 90860
Does anyone know if there's a ready-to-use rs232 uart in vhdl for the Virtex-II pro fpga? We have done some designs in ISE, and hope to display results in a terminal window. Thanks.Article: 90861
miniuart project at www.opencores.org is a ready-to use uart which works very well. A more sophisticated one is in uart16550 project but with miniuart is enough for most applications. Javier Castillo On 23 Oct 2005 21:17:06 -0700, "Eric" <dasani8888@hotmail.com> wrote: >Does anyone know if there's a ready-to-use rs232 uart in vhdl for the >Virtex-II pro fpga? We have done some designs in ISE, and hope to >display results in a terminal window. Thanks.Article: 90862
aholtzma@gmail.com wrote: > > For the record, mine sadly came with only win32 binaries. Can anyone > at Xilinx explain why this is? Is it just to save the cost of a few > CDs? BTW: Were can I download the linux binaries? I didnot see the EDK bins for linux Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 90863
Hi Folks, For educational purpose (Von Neumann demo), I am looking for a System On Chip Processor : - very simple - gate level design (no VHDL, only gates AND,NAND, and low level boxes as shifter, ...) - running system (spartan 3 or other low cost xilinx or altera demo board) regards RaphArticle: 90864
"JJ" <johnjakson@gmail.com> writes: > The SDRAM is not actually too slow, it is only 2-3 x slower than RLDRAM > as latency goes, the problem is it has no concurrency so only 1 bank in > flight v 8 so RLDRAM gets 20x more work done. Threaded DRAM goes with > threaded processor. > Hi John, The (fairly boggo) SDRAM I've used has 4 banks open concurrently, so so long as your scatter your thread data across the banks, you can have low-latency access ... or is that not what you mean? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 90865
I have an application where I need to implement 24 or up to 32 PWM outputs (8-bit) and am considering using a small CPLD to handle the PWMs instead of doing it all in software. This does add a CPLD to the design, but frees the micro do to other things. Any recommendations on the CPLD & CPLD size without completing the VHDL first?Article: 90866
"Emtech" <noaddress> schrieb im Newsbeitrag news:435cb632@news.eftel.com... > I have an application where I need to implement 24 or up to 32 PWM outputs > (8-bit) and > am considering using a small CPLD to handle the PWMs instead of doing it all > in software. > This does add a CPLD to the design, but frees the micro do to other things. > > Any recommendations on the CPLD & CPLD size without completing the VHDL > first? > > if you think small PLD is cheap then thing again. for 32 x 8 bit PWM you need 256 flips flops only to hold the PWM values. those you would need 384 MC PLD or larger. now look at the prices. using an low cost FPGA would be cheaper, or possible MAX2 or machXO device. if you have cheap flash memory to hold FPGA config use LatticeEC or small spartan if not then look at MAX2 or MachXO - those are advertized as PLD but are in fact small simple FPGA with nonvolatile config. or LatticeXP what is nonvolatile FPGA anttiArticle: 90867
Hi Martin The modern SDRAM has had 4 banks now forever, but most processor designs and their miserable controllers and cache hierarchy haven't had much use for banking. To feed cache refills, bandwidth has been king, copy big chunk of data from DDR CAS cycles into cache lines and stay away from RAS cycles as much as possible. Even in the old days, banking was always considered as do as little as possible to save power etc. The packaging of DRAMs with muxed address halves and the requirement to access fully random over full address means several pin transactions per full cycle rather than 1. According to the Micron website on the benefits of RLDRAM over SDRAM, they suggest that some SDRAM bank overlap is possible, ie as soon as RAS has delivered data from one bank, another bank open can start while the previous bank can finish up the bank cycle so its like 40,40,40, rather than 40+20,40+20,,, so 1.5 times better. The real benefit comes from unfettered banking apart from bank collisions to start cycles every 2.5ns instead of 40ns. It would have been even better if Micron had had the forsight to use 16,128, or even 64K banks although only 8 or so would ever be simultaneously in flight. The latency of 20ns can be managed by MTA processor design, but the ability to issue every 2.5ns (3.3ns in FPGA with 6 clocks latency) is the charm. 40ns every 40ns just isn't the same. Lots of issue rate means lots of slower PEs can share it. If conventional SDRAM can overlap 2 banks during the RAS time, that would be news to me. regards JohnArticle: 90868
Eric Smith wrote: > "Pete" <padudle@sandia.gov> writes: > > I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC > > (TEMAC) of the Virtex4 FX parts. EDK offers several options for Ethernet MAC > > type but they are all soft MACs. > > EDK 7.1 has a wrapper for the hard MAC. And there's an update for that > wrapper downloadable from the Xilinx web site. Can you get either xilnet or lwIP to work with it though? For xilnet, in the library/OS parameters tab, I can't set the plb_temac as the emac_instname (Only none is listed). For lwIP, when generating libraries and BSPs, I get the error: lwIP library needs at least 1 ethernet or 1 ethernetlite device to work. I definetly have instantiated the plb_temac_0 and hard_temac_0 cores. Any ideas? Cheers, JonArticle: 90869
Hi, We are using CD22M3494(16 X 8 audio switch).Which has 128 switches. Now initially i connect switch X0 to switch Y0 , this particular switch is closed(commected) now. Now if i need to connect X1 to Y0 , should i open(disconnect) the connection between X0 and Y0.What happens if i do not open the switch X0 to Y0. Will the Y0 output be superimposed version of X0 and X1. Plese clarify on this. Thanks in advance. Regards, PravArticle: 90870
On Mon, 24 Oct 2005 20:24:10 +1000, "Emtech" <noaddress> wrote: >I have an application where I need to implement 24 or up to 32 PWM outputs >(8-bit) and >am considering using a small CPLD to handle the PWMs instead of doing it all >in software. >This does add a CPLD to the design, but frees the micro do to other things. > >Any recommendations on the CPLD & CPLD size without completing the VHDL >first? > one or more slave microcontrollers, doing the PWM in software will probably be a lot cheaper than a PLD/FPGA solution if the speed you need isn't excessively high. Something like PIC16F914 or one of the lower end ATMEGA range should do the job. Obviously there will be tradeoffs between PWM rate, resolution, pin-count and cost that will determine the optimum number of micros, but even if you needed 4 MCUs doing 8 channels each it would be a lot cheaper than a CPLD or FPGA solution, Another solution worth thinking about is a hybrid mcu/CPLD solution - if it would be possible to stagger the PWM phase, then the MCU could output the PWM value for each channel at the start of each cycle, then the external logic resources would be reduced to a set of loadable 8-bit down-counters, which would be more amenable to fitting in a cheap CPLDArticle: 90871
Can anyone give me a general idea on pricing and availability for low volumes (~50) of the XC3S4000-5FG900? The only online price I can find is $242 from Avnet, for the -4 part (no -5), no stock, 8 weeks leadtime. Thanks - DomArticle: 90872
cisivakumar wrote: > Hai, > > I want to do the main project as Implementation of 1024 point FFT in > Actel FPGA.I have to find a new frequency identification algorithm > other than Fast Fourier Transform.Please give valuable notes,codes and > suggestions for successully completing this project. > > Thanking you. > I.Sivakumar > Has anyone tried the Goertzel Algorithm?? I read about it in the embedded magazine. http://www.embedded.com/story/OEG20020819S0057 BrijeshArticle: 90873
Peter C. Wallace wrote: > On Mon, 17 Oct 2005 12:32:48 -0700, Dave Pollum wrote: > > > > > > So Peter, what do those of us with lowly Spartan-II FPGA's do if we want > > say, a 16x9 FIFO? > > -Dave > > A very small 16 by N sync FIFO is easy in the SpartanII using N SRL16E's > (and a 5 bit counter) > > Peter Wallace I think the thread was about async FIFO. For this SRL16's are of no use. Your best bet is the COREgen FIFO using distributed memory for shallow (x15 or x31) FIFO's or block memory for deeper ones.Article: 90874
"vssumesh" <vssumesh_asic@yahoo.com> schrieb im Newsbeitrag news:1129382687.709768.136110@g43g2000cwa.googlegroups.com... > Hi all, > Thinking of a 5 stage pipeline risc. > 1. fetch > 2. decode > 3. execute > 4. buffer > 5. write back > The result of execution stage is buffered at the +ve edge of the > buffer cycle. And this works if we enable the data forwarding method. > And the next instruction will get the updated values from the buffer > register at its execution stage. And the buffered data will be placed > to memory ony at the write back stage. > My doubt is if this is true where will we buffer the output of the > execution stage of the second instruction at the +ve edge of its buffer > cycle as the buffer is still holding the result of the previous > instruction. > I am a beginer to these type of things. This is similar to the ARM9 > pipeline. Whats their way of tackling this situation. > If you insist on understanding the DLX stuff, the following link is an excellent in-depth tutorial about memory architecture and pipelining. H & P for homebrew pipeliners... http://www.cs.iastate.edu/~prabhu/Tutorial/title.html MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !
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