Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Apr 23, 3:07 pm, Jhoberg <jrqueve...@gmail.com> wrote: > This it is a message of Richard Staman creator of free softeare > fundation and GNU on an idea to construct free hardware in FPGAs. > > http://lists.duskglow.com/open-graphics/2007-January/008663.html > > http://en.wikipedia.org/wiki/Richard_Stallman > > Some nonfree architectures exist at the moment but it is known as a > processor JAVA and Core of processor ARM work like in which I could > run GNU/Linux in FPGA, like a Spartan3: > > JAVA Processorhttp://www.jopdesign.com/ > > Core ARMhttp://www.opencores.org/cvsweb.shtml/sARM7TM/ > > Microblazehttp://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j...http://en.wikipedia.org/wiki/MicroBlaze > > The concept would be a free architecture in this implemented which > drivers and some functions of DSP of, but for this could be to > constuir a sintetizer with GPL Free Hardware http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/c74bb31e6278d388/f4a26f0abe7ba44b#f4a26f0abe7ba44bArticle: 118326
Hello, Just finished writing an ADC driver which I connected to a PPC via PLB (slave configuration). I have also instantiated a OPB interrupt controller to which I'm trying to register my ADC driver interrupt. However, so far I couldn't manage to register my interrupt handler--- SDK keeps on giving me this weird error message whenever I attempt to register my external interrupt through XExc_RegisterHandler API. The error messages is: "cannot move location counter backwards (from fffff070 to 00000070)" I'm using EDK 9.1. Probably I'm missing something. Though it might be worth posting as one can never be sure in case it turned out to be a known issue or something. Would appreciate any help in this. Regards, -MannyArticle: 118327
On Apr 23, 8:47 am, ddal...@gmail.com wrote: > Hi, > I am having a problem with a design. When DONE cycle is set to 5 or 6 > DONE pin never goes high. I have confirmed that the part is > configuring by scoping the output from the DCM. The part is a 2S300E. > > When I scope out the INIT line I find that after 280mS the INIT line > returns to a High-Z state - I believe that this is interupting the > state machine so causing the DONE pin not to go high. > > If I set the DONE cycle to 1, 2, 3 or 4 - DONE goes high and INIT > stays high. > > Any help would be appreciated > > Dave Dave, I often find this with Spartan 2 designs. I am currently using the Digilent parallel port programmer but have seen identical problems with the Xilinx parallel port programmer. It seems to be pattern dependent in that it depends on the previously programmed configuration of the part. I have always managed to program the FPGA by first erasing the configuration prom, forcing a reconfiguration and then configuring the FPGA. It does not affect programming of the configuration prom and I also haven't seen the problem on Virtex 2 designs. kevinArticle: 118328
Hi all, I m using the Xtreme DSP Development Kit 2 with Viretex 2 XC2V3000-4FG676 FPGA. While doing JTAG cosimulation in Simulink, i got an error message:"Error configuring device: A problem may exist in the hardware configuration. Check that the cable, scan chain and power connections are intact, that the specified scan chain configuration matches the actual hardware,and that the power supply is adequateand delivering the correct voltage." Thanks for the help.Article: 118329
>> Oh btw I have then tried to add on more register levels. >> Have tried some structures, and I deduce this coding should be logical. >> Wonder if there is anything wrong. The lowest I have brought the timing >> down >> is a slack of about 1ns > > There are limits to how many registers XST is able to move around when > using automatic pipelining and it appears to vary from two to four > depending on constructs and tool versions. Yeh Well thanks alot in all for your help. If not for your help, I wouldn't have make so much progress and most of all, know more about some FPGA. Hmm, anyway, currently for my project, I guess pretty stuck already and am not able to lower the timing delay any further. Maybe because probably no one knows exactly whether it is possible to port the design from a Virtex to a Spartan. Maybe it can, maybe it just cannot be done. Hmm more ways I could progress further on about this would be (maybe) to find out more on the sequential tables and coefficients tables and whether I could do something about the wrapper and find out more about this wrapper. Or I could use the DDR SDRAM (shudders...) Lastly, another problem would be the IO ports and how to actually implement this scaler in practical sense. Anyway appreciate your help so far. Many thanks!Article: 118330
Hi everyone! I use Xilinx Core generator to generate DA FIR filter. Right now, I want to take the verilog code for DA FIR filter but I don't know how can I do it. Can you help me?Article: 118331
it is work good!Article: 118332
Hi All, I am trying to add a customized OPB peripheral to the Microblaze system in EDK/Platform Studio 8.1. My peripheral uses a FFT core generated from Core Generator so it only comes with ngc netlist. I instantiate the core in the user_logic.v. And I was able to synthesize the peripheral using generated ISE project file by adding the IP source file (core wizard) to the project. But when I add peripheral to the system and generate the netlist, the XST tool always complains: ERROR:HDLCompilers:87 - "D:\TechDrive\Project\Xilinx\AEC \pcores\coproc_v1_00_a/hdl/verilog/user_logic.v" line 536 Could not find module/primitive 'fft' I did quite a bit search in the help,manual of EDK document,Core Generator, XPS help but I could not find any help for such case. Luckly I was able to find some help from this forum. One of them suggests to add a bbd file and change mpd file in the core's resposiories data folder. I tried exactly same step but it does not work for me. I also tried to import the the peripheral to design through both XST prj file and PAO file but neither of them helps. After spending two nights on this "intergration" issue without any luck, I am pretty upset about the Xilinx tool chain especially the document part! I thought this is very typical case(EDK->Peripheral- >LogiCore) and there should be some sort of help easy for acess for newbie. Maybe I am too blind to find it. But if somebody can point me out where the document is or workaround it through some tricky way, I'll greatly appreciate it! Thanks a lot! WilliamArticle: 118333
Hi Gordon, The core generator only generates the netlist for the IP with Verilog/ VHDL wrapper file functional simulation. If you use ISE, then you can generate the core inside the ISE and you can instantiate the core in your design. Just right click on your project and select "New source" and IP(Coregen & Arch Wizard) and you can generate the same core and ISE will add the necessary files automatically. William On Apr 24, 12:16 am, Gordon Freeman <gordonfreeman1...@gmail.com> wrote: > Hi everyone! > I use Xilinx Core generator to generate DA FIR filter. Right now, I > want to take the verilog code for DA FIR filter but I don't know how > can I do it. > Can you help me?Article: 118334
"lzh08" <cppcpldfpga@gmail.com> wrote in message news:1177403186.593874.148020@r35g2000prh.googlegroups.com... > it is work good! > Well done. However, in future, instead of posting to the newsgroup, I suggest this:- http://photos1.blogger.com/blogger/6295/1280/1600/dilbert.gif HTH, Syms. :-)Article: 118335
Hrishi <sankpalhrishi@gmail.com> posted: "[..]I am facing a problem with the signals defined with the real data type.The navigator indicates that the code (with some signals defined as real ) is syntactically correct but it gives an error during synthesis.It states this feature is not supported." This is because typically by default synthesis tools will not compile numbers with non-zero vulgar fractions because the amount of hardware which would be needed would be much more for whole numbers. If you are certain that you are willing to sacrifice so much hardware, then you could use something like WWW.OpenCores.org/projects.cgi/web/fpu100/overview (I have not used this and you can expect commercial alternatives to be better) for synthesis. " After checkin out for a solution we ended up finding that a math_real package in ieee.std_logic_1164.all is copyright protected.[..]" The reason ISE does not synthesize this is not because of the copyright of the package you have tried.Article: 118336
On Apr 23, 7:58 pm, Gabor <g...@alacron.com> wrote: > On Apr 23, 11:47 am, ddal...@gmail.com wrote: > > > Hi, > > I am having a problem with a design. When DONE cycle is set to 5 or 6 > > DONE pin never goes high. I have confirmed that the part is > > configuring by scoping the output from the DCM. The part is a 2S300E. > > > When I scope out the INIT line I find that after 280mS the INIT line > > returns to a High-Z state - I believe that this is interupting the > > state machine so causing the DONE pin not to go high. > > > If I set the DONE cycle to 1, 2, 3 or 4 - DONE goes high and INIT > > stays high. > > > Any help would be appreciated > > > Dave > > What mode are you using to program the part? Is your configuration > clock > continuing to run at the end of configuration? Often stopping the > clock > too soon is the cause of this sort of problem. > > HTH, > Gabor Hi Gabor, I am using slave Parallel mode and a fre running 33MHz clock DaveArticle: 118337
On Apr 24, 2:33 am, k...@whitedigs.com wrote: > On Apr 23, 8:47 am, ddal...@gmail.com wrote:> Hi, > > I am having a problem with a design. When DONE cycle is set to 5 or 6 > > DONE pin never goes high. I have confirmed that the part is > > configuring by scoping the output from the DCM. The part is a 2S300E. > > > When I scope out the INIT line I find that after 280mS the INIT line > > returns to a High-Z state - I believe that this is interupting the > > state machine so causing the DONE pin not to go high. > > > If I set the DONE cycle to 1, 2, 3 or 4 - DONE goes high and INIT > > stays high. > > > Any help would be appreciated > > > Dave > > Dave, > > I often find this with Spartan 2 designs. I am currently using the > Digilent parallel port programmer but have seen identical problems > with the Xilinx parallel port programmer. It seems to be pattern > dependent in that it depends on the previously programmed > configuration of the part. I have always managed to program the FPGA > by first erasing the configuration prom, forcing a reconfiguration and > then configuring the FPGA. > > It does not affect programming of the configuration prom and I also > haven't seen the problem on Virtex 2 designs. > > kevin Hi Kevin, Thanks for getting back to me - this sounds very promising. Do you have any more detail on the problem? DaveArticle: 118338
In news:1177368991.632815.213970@q75g2000hsh.googlegroups.com timestamped 23 Apr 2007 15:56:31 -0700, Kolja Sulimma <ksulimma@googlemail.com> posted: "[..] I at least find it strange that so much progress is happening in SystemC and other high level synthesis languages while at the same time the VHDL synthesis vendors stick to the same language subset that synopsis defined eons ago." To be fair, VHDL subset synthesis vendors are not literally that restrictive, but may not be far off. You are of course not the only one to deem this to be strange, e.g. a few years ago I wrote in a review of an excellent book by Ben Cohen (currently available on WWW.ACCU.org/index.php/book_reviews?url=view.xqy?review=v003592 ): "[..] [..] it is bewildering that compilers for primitive programming languages had always given full support to features present in VHDL when synthesis tools do not support these features, and the lack of maturation in tools to support VHDL is shocking. [..]" Jim Lewis has claimed a number of times that VHDL subset vendors will provide what paying customers demand. Kolja Sulimma posted: "XST even discourages the use of arrays and records, for gods sake. This is not the 90s anymore." XST is not the most expensive of VHDL subset synthesis tools. However, I remember someone had claimed on a newsgroup that XST supported shared variables in some circumstances, unlike a more expensive front end. Even in the 1990s I would not had deemed discouraging arrays and records to be reasonable, not that I had even heard of VHDL back then. Just about anything can be synthesized, but synthesis tools on the market (as distinct from synthesis tools which do not exist but which are not impossible to produce) will not synthesize just about anything.Article: 118339
> "cannot move location counter backwards (from fffff070 to 00000070)" Unfortunately I can't give you a solution. However, this error is most likely produced by the GNU PPC assembler. The assembler is one- pass and as such requires all ORG statements to be ordered incrementally. Appearently your source code specifies (explicitly or implicitly) sections in reverse order, ie first the code for fffff070 and then the code for 00000070. If you manage to rearrange this in your sources, the error should go away. Good luck, MarcArticle: 118340
On Apr 24, 4:29 pm, FPGA <esp...@gmail.com> wrote: > Hi Gordon, > > The core generator only generates the netlist for the IP with Verilog/ > VHDL wrapper file functional simulation. > If you use ISE, then you can generate the core inside the ISE and you > can instantiate the core in your design. > Just right click on your project and select "New source" and > IP(Coregen & Arch Wizard) and you can generate > the same core and ISE will add the necessary files automatically. > > William > On Apr 24, 12:16 am, Gordon Freeman <gordonfreeman1...@gmail.com> > wrote: > > > Hi everyone! > > I use Xilinx Core generator to generate DA FIR filter. Right now, I > > want to take the verilog code for DA FIR filter but I don't know how > > can I do it. > > Can you help me? Thank you for your reply. But I can't modify it. Can you show me how to take the verilog code for synthesize? I would like to know how they process in this code.Article: 118341
hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm trying a make a sine wave, ramp, triangular and square wave generator which outputs required wave of required amplitude and required frequency The FPGA is connected with DAC thru I2C bus.. The development board (nanoboard) has on- board freq of 20 mhz...now the dac being connected to the I2c bus can work upto max 400 Mhz..so a suitable clock divisor has to be implemented ..thus a low frequency can be used as SCL input to DAC.. a)Now, for the sine and square wave, I'm assuming that we can use the same look-up table(values ranging from 0 to 256)for the output values of DAC.for obtaining different frequencies, only the SCL needs to be changed . i.e.if SCl rate is high, the DAC would output from 0 to 256, then to 0 at a faster rate, if SCL is low, it would output the same values, but with some delay. THus, variable frequency can be obtained by changing SCL rate..am I correct in assuming so? b)If this is correct, can anyone please tell me the relationship between SCL and output wave frequency..if such a formula/well defined relationship does exist c) Also, can anyone tell me about a good link for a simple tutorial on implementing look-up table?I did find some on the web, but they all seemed to be complicated..either because they ARE..or because my mind has gone all-blank right now, with the submission date coming so near.. Any help at this time would be hugely appreciated Kind Regards, Sheetal GandhiArticle: 118342
The target device connected to the Xilinx V5 FPGA does not support 8b/10b. There is a well defined training algorithm for bit and packet alignment. The data rate of V5 transceiver is very attractive so I am trying to see if I can use them in a source synchronous mode even if it involves using external precision delay element with 5 ps resolution at the output of each transceivers. If I do not use the FPGA transceivers then I have to use external high speed mux and demux in conjunction with the parallel FPGA I/O. This increases the board design complexity when delaing with 20 source synchronous channels running at 3.2 Gbps each.Article: 118343
It seems there is problem with OPB in MPMC2 core. PPC will dead when 2 PPC share OPB peripherals in MPMC2 coreArticle: 118344
hello, thank you for answering but i am not able to solve my problem yet. the generic C_BUS_WIDHT has a default of 1, and the upper levels are using the or_gate.vhd file with the same generic. What make me angry is that i cannot modify this files, because they are cores from XILINX, that means that i have not modified them, and it should work. I would like to know if someone was able to use the simulation of designs in Xilinx Platform Studio. And if someone was able to solve my problem. Thank youArticle: 118345
Test01, Sorry, I can't help you. The choices you are making are likely to lead to a system that can not possibly work. Controlling delays to 5ps is a recipe for disaster. The MGTs are designed with a great deal of logic wrapped around the physical layer interface (to make life simple). I suggest you use a separate physical layer only interface, as if you try to use the MGT in V5, you will be trying to pound a square peg into a round hole. AustinArticle: 118346
Jim Granville wrote: > Eli Hughes wrote: >> Here is working (Actually Implement in Silicon) code: > > Any comments on relative Simulate and P&R times, for others that may > follow ? > > -jg > Forgot to mention that the design is now 950000 element shift register. This code snippet was written for the Digilent XUP board. I did not measure the simulation time in any precise way but it was only a few seconds between starting the simulation (ISE simulator) and getting my results. My test bench was simple, clocked in a somewhat random pulse train at starting time 0 and ran the simulation to about 1000000 clock cycles later. The pulse train was delayed as expected..... The total time to Synthesize to generating a bit stream was about 1 minute on a P4 2.4GHZ with 1GB RAM. The bitram implementation is very quick to synthesize and P&R. The code could be cleaned up a bit, but it functions well for its intended purpose ...... i.e. a colleague stops in my office and tells me to build a 1 sec delay generator with 1uS resolution. I can't spend any money on parts and it needs done by the next morning with some BNC connectors hanging from the board.Article: 118347
Excellent product! This is perfect for our needs. We usually make 2-4 layer boards but don't want to deal with BGA. Keep up the great work! What kind of quantities are available? This would be really cool with a Virtex 4 device (one with a power PC built in!) John Adair wrote: > Jim > > What you see on the current photo are the solder joints of a double > ended pin so the pins come out the bottom as currently done. Given we > don't need to meet a specific pinout we could take them out the top if > someone need one that way or even have a socket + pin assembly like we > use in out OVERCOAT arrays. We can also make these with an un- > populated header and this could be a lot cheaper for high numbers used > in production say in a low pin count application. > > The PGA pin header is not cheap either to purchase or even to assemble > so I would recommend anyone with a specific interest that would want a > a few+ should come and talk to us. We can deal with Bill of of > Materials variants for 5-10+ shipping units and can even be economic > on a customised pcb variant of any of our products in fairly small > numbers (say 25+ off on a small product like this). Our development > board products really are only a demo of what we can do and supply > ideas to be used in a mix and match fashion on customer specific > designs. > > John Adair > Enterpoint Ltd. > > On 20 Apr, 20:58, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: >> John Adair wrote: >>> Finally first picture of Darnaw1 our PGA style FPGA board is here here >>> http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on >>> pricing and spec in the next couple of days will appear on the >>> website. Those with eagle eyes can work it out the spec from the >>> picture. >> Are all the components shown - no photo of the rear ? >> >> Does the PGA plug into the side we see, or the other side ? >> [and the side we see is for probing - but not labelled ? ] >> >> -jg > >Article: 118348
On Apr 24, 6:25 am, Sheetal <sheetalgandhi...@gmail.com> wrote: > hi..I'm a university student familiar with the only the basics of VHDL > and FPGA implementation..For my project, I'm trying a make a sine > wave, ramp, triangular and square wave generator which outputs > required wave of required amplitude and required frequency > > The FPGA is connected with DAC thru I2C bus.. That's going to be slow. Are you sure that is the data interface, and not a secondary control interface? > a)Now, for the sine and square wave, I'm assuming that we can use the > same look-up table(values ranging from 0 to 256)for the output values > of DAC.for obtaining different frequencies, only the SCL needs to be > changed . i.e.if SCl rate is high, the DAC would output from 0 to 256, > then to 0 at a faster rate, if SCL is low, it would output the same > values, but with some delay. THus, variable frequency can be obtained > by changing SCL rate..am I correct in assuming so? You could. But your frequency resolution would be limited to only those frequencies which are factors of your clock rate divided by your table lenght. In some applications that is fine, in others it would be unacceptable. For finer frequency resolution, what is typically done is to have a wide phase accumulator register - maybe 40 bits but depending on the application. Each clock cycle, you add a value computed from the frequency to the phase register. At high frequencies it will increment more each step, at low frequencies it will increment less. Then you take only some of the top bits - lets say maybe the 12 most significant bits - and use them as the address into your lookup table. This means that while the phase of the output samples will jitter around a bit, the actual frequency can be adjusted with very high accuracy and fine resolution. If you put an analog low-pass filter on the output of your DAC, you can make some very nice sine waves.Article: 118349
Hi, I have to write a program with threads and when I reserve memory for these threads, an error occurs if this memory is big. I have configure Linker Script to run in Sdram so I have quite a lot memory to use. Could I increase the memory area for this program?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z