Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Guru schrieb: > On May 27, 8:10 am, Rob Barris <rbar...@mac.com> wrote: >> Subject says it all - would like to hear from people using the SUZAKU >> modules, how well they work, what toolchain / development hardware you >> use, etc. >> >> http://www.atmark-techno.com/en/products/suzaku >> >> Especially interested in learning what the workflow is for iterating on >> a design that has an embedded MicroBlaze, does the inclusion of the >> soft-core CPU add a lot of turnaround time during recompilation of a >> design into a bitstream? Or is that part mostly static and unlikely to >> slow down debugging & iteration. >> >> And any pointers to appropriate JTAG interfaces for USB2 or Ethernet >> would be appreciated too. >> >> Rob >> >> -- >> Posted via a free Usenet account fromhttp://www.teranews.com > > I was also looking at that boards, but not purchased yet. I like the > uClinux implementation (japanese are crazy about linux) and VMware > development tools encapsulation. I would also like to hear a response > from the users. > Otherwise for JTAG use Xilinx PlatformCable USB, it is worth 150$. > > Cheers, > > Guru > Hi, we just bought a Suzaku SZ130. One of our students builds a simple power supply and adapter card. As soon as he finishes we will make our first real experience with the SZ130 Board. We are working with ISE & EDK (8.2i) under a debian linux environment. We only have an old Parallel Cable III, so we have to provide our Adapter card with a a 2.5V Level converter for the Suzaku JTAG. Rob already is a member in the Suzaku mailing list. If you want to know more about Suzaku and its users, subscribe to that list via the Suzaku homepages. If you want to use the I/O pins of the Suzakus, you really need the EDK, because they are not available as GPIOs in the standard configuration. I'm already preparing a design modification for our student, but besides that want to build a LPT port later. Anyone has a parport driver for microblaze? :-) best regards EilertArticle: 119901
Hi, I'm finding a linux device driver for FPGA Xilinx Virtex-4, somebody can help me? thanks.Article: 119902
Hi, I'm looking for a Linux device driver for FPGA Xilinx Virtex-4, somebody can help me? Thanks.Article: 119903
Thanks guys for all your comments. I have been away on an urgent business trip, so I have not been able to watch the replies before now. Below are answers for posts that I find I could reply back to and in the same order as the postings. Symon: Yes the impedance is high (if the supplier given numbers for unbalanced and balanced impedance apply). It is a 0.50 pitch flexible flat cable used in the configuration GPNGPNG where P is positive part and N inverted signal. John H: Your solution looks promising and to some degree as my first mock-up trial. The reduced swing should not be a problem, as long as it does not alter the signal to much to my low-speed application. Austin: You are right. But it should also be possible to do without in a low speed LVDS scenario. And we are looking into buying Hyperlynx....But the SI's weak point is that you should know the correct properties of your whole path. Thanks for your comment regarding the transmitter matching. I have requested a Hyperlynx eval license, then it is just the whether I am able to use it straightaway to simulate LVDS pairs:-) And as the others said earlier, I wanted some feedback before trying Hyperlynx, since I would need an idea of what to simulate, since Xilinx only mention the need for Receiver diff termination. Thanks again for all of your.Article: 119904
Yao Sics wrote: > Dear All, > > I just wonder if there is a simple way to calculate IFFT based on FFT > results? > > I was trying to configure xilinx FFT coregen v3.1 to perform IFFT > operation, but no matter how hard I tried, the result is the same as > FFT. Strange! The timing is exactly based on the FFTv3.1 datasheet. > Assert fwd_inv_we ='1', and fwd_inv=' 0', and then de-assert > fwd_inv_we. > > If this problem can not be solved, I have to calculate IFFT based on > the result of FFT. > > Has anyone experienced this before? > > > Cheers, > > > Yao An IFFT is just an FFT of an FFT, perhaps scaled by a factor of 2*pi (or other constant scaling) depending on the Fourier Transform scaling used for the FFT. Plus, the FFT results are based on the input so the input would be the IFFT. What question are you really trying to ask?Article: 119905
On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> maverick schrieb:> Hi there,
> > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > from using ChipScope pro on this board to debug my design. Is it
> > possible somehow to tap the jtag ports internally and route them to
> > GPIOs which are available on th board! In that case, I will insert the
> > ChipScope Pro core in my design in the normal fashion and will put
> > that part of the code in the design that will tap the JTAG ports
> > internally and will map them to other GPIOs?
>
> > Farhan
>
> sure, get it here:
>
> http://code.google.com/p/fpga-tools/downloads/list
>
> Antti
Hi Antti,
Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
file. Unfortunately, I am a Verilog writer and do not have much
exposure to VHDL code. What I have understood from the code is, I have
to instantiate this primitive into my design and map the IO to FPGA
IOs. It will make my life easy if you can demonstrate it by making
required changes in the following simple counter code as it is not
clear to me how would I make the chipscope logic communicate to this
primitive. In the following code, assume that I have to monitor 8-bit
counter reg in chipscope pro.
//----------------------------------------
module my_counter(clk,
rst,
led
);
input clk;
input rst;
output led;
reg [7:0] counter;
always @(posedge clk)
if(rst)
counter <= #1 0;
else
counter <= #1 counter + 1;
assign led = counter[7];
endmodule
//---------------------------------------------------
BTW, do you have the Verilog version of the same primitives?
Thanks and waiting for your help,
Farhan
Article: 119906I've a question concerning BSCAN_SPARTAN3 primitive - since it adds "virtual" cell to the boundary scan register, do I have to include it somehow in the BSDL file, that describes the Boundary Scan Register of my chip? ChrisArticle: 119907
On May 29, 8:17 am, greywol...@hotmail.it wrote: > I'm looking for a Linux device driver for FPGA Xilinx Virtex-4, > somebody can help me? There's no such thing! Your device driver has to know the configuration of the interface that the FPGA is _programmed_ to implement. Since the FPGA is a universal part, there's no universal answer. Or maybe you want to talk to the JTAG or other configuration interface rather than an operational one...Article: 119908
On May 26, 8:25 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > Mind you, all it could do was a 7-step (not 8-step) grayscale. No > colour subcarrier, of course, and no equalizing pulses. > Now if only they had a 4MHz Z80A! They did... my first computer was clocked at 4.77 MHz with a Z80A (well, one online reference claims it wat 4 MHZ, but I think that's wrong)Article: 119909
On May 29, 9:17 am, greywol...@hotmail.it wrote: > Hi, > > I'm looking for a Linux device driver for FPGA Xilinx Virtex-4, > somebody can help me? > > Thanks. link to a Virtex II Pro article http://www.xilinx.com/publications/xcellonline/xcell_48/xc_linux48.htm Your question is too general. Are you thinking about running linux on a PPC in a Virtex4 FX part. You will need to configure and adapt a kernel (OS). -NewmanArticle: 119910
On 29 Mag, 14:14, Newman <newman5...@yahoo.com> wrote: > On May 29, 9:17 am, greywol...@hotmail.it wrote: > > > Hi, > > > I'm looking for a Linux device driver for FPGA Xilinx Virtex-4, > > somebody can help me? > > > Thanks. > > link to a Virtex II Pro articlehttp://www.xilinx.com/publications/xcellonline/xcell_48/xc_linux48.htm > > Your question is too general. Are you thinking about running linux on > a PPC in a Virtex4 FX part. You will need to configure and adapt a > kernel (OS). > > -Newman I'm working with a board MPC8548CDS-like (PowerPC). Connected to processor local bus and with pci express there is a Virtex 4 (xc4vfx60). -MarcoArticle: 119911
On May 29, 12:48 pm, Antti <Antti.Luk...@googlemail.com> wrote: > On 29 Mai, 12:38, "fabien....@gmail.com" <fabien....@gmail.com> wrote: > > > Hi, > > I want to implant a ICD into my Spartan 3 dev board. I need to program > > some Microchip PICs, and I wondered if I could use the FPGA, instead > > of buying an ICD board. > > Has someone already seen that ? > > > Thanks, > > Fabien > > all is possible, but its faster and cheaper to get some ICD2 clone > > Antti Yep thanks you. It was just in case somebody had a ready IP...Article: 119912
Stefan, You are welcome. Out of the box evaluation version may not have all the features, but it will be useful. What is included: some ribbon cables, coax, etc. PCB trace configurations for stripline, micro-strip, etc. Connectors. The linsim package will extract from layout to check that your PCB is OK before you fabricate it. Slow enough speed, and SI is pretty much a "don't care" except for things like SSO (which LVDS has no restrictions on). Austin stefan.elmsted@gmail.com wrote: > Thanks guys for all your comments. > I have been away on an urgent business trip, so I have not been able > to watch the replies before now. > > Below are answers for posts that I find I could reply back to and in > the same order as the postings. > > Symon: > Yes the impedance is high (if the supplier given numbers for > unbalanced and balanced impedance apply). > It is a 0.50 pitch flexible flat cable used in the configuration > GPNGPNG where P is positive part and N inverted signal. > > John H: > Your solution looks promising and to some degree as my first mock-up > trial. > The reduced swing should not be a problem, as long as it does not > alter the signal to much to my low-speed application. > > Austin: > You are right. But it should also be possible to do without in a low > speed LVDS scenario. > And we are looking into buying Hyperlynx....But the SI's weak point is > that you should know the correct properties of your whole path. > Thanks for your comment regarding the transmitter matching. > I have requested a Hyperlynx eval license, then it is just the whether > I am able to use it straightaway to simulate LVDS pairs:-) > And as the others said earlier, I wanted some feedback before trying > Hyperlynx, since I would need an idea of what to simulate, since > Xilinx only mention the need for Receiver diff termination. > > Thanks again for all of your. >Article: 119913
"Rob Barris" <rbarris@mac.com> wrote in message news:rbarris-A99FFE.23104626052007@free.teranews.com... > > Subject says it all - would like to hear from people using the SUZAKU > modules, how well they work, what toolchain / development hardware you > use, etc. > > http://www.atmark-techno.com/en/products/suzaku > > Especially interested in learning what the workflow is for iterating on > a design that has an embedded MicroBlaze, does the inclusion of the > soft-core CPU add a lot of turnaround time during recompilation of a > design into a bitstream? Or is that part mostly static and unlikely to > slow down debugging & iteration. > > And any pointers to appropriate JTAG interfaces for USB2 or Ethernet > would be appreciated too. > > Rob > I bought an SZ010 board for use in a PVR project, thinking the EDK/Linux design would provide a fast development route. In the end this proved impractical, simply because uCLinux running on a Microblaze (which maxes out at about 52MHz in this case) doesn't provide good enough network performance - from memory, an ftp test was clocking in at around 3 mbits/s. Unless you're prepared to rip everything up and start again, which is what I had to do, you may be better off spending a bit more to get a V-series board. These have a hard, 270MHz PPC405 built into the FPGA, which ought to help with the performance issues. That said, being forced to design from the ground up was certainly a learning experience for all things MAC and ethernet related. :-) On the JTAG side, the cheapest/easiest approach is to get a cheap parallel III compatible cable (e.g. the Digilent one) and make an adaptor. There is no connector on the board, so you'll be soldering something on there whatever you do. Interfacing to the FPGA requires 2.5V, as noted elsewhere, but the flash interface is 3.3V, which means you can wire straight up without a level conversion. Cheers, Dave .Article: 119914
On May 29, 10:32 am, greywol...@hotmail.it wrote: > On 29 Mag, 14:14, Newman <newman5...@yahoo.com> wrote: > > > > > > > On May 29, 9:17 am, greywol...@hotmail.it wrote: > > > > Hi, > > > > I'm looking for a Linux device driver for FPGA Xilinx Virtex-4, > > > somebody can help me? > > > > Thanks. > > > link to a Virtex II Pro articlehttp://www.xilinx.com/publications/xcellonline/xcell_48/xc_linux48.htm > > > Your question is too general. Are you thinking about running linux on > > a PPC in a Virtex4 FX part. You will need to configure and adapt a > > kernel (OS). > > > -Newman > > I'm working with a board MPC8548CDS-like (PowerPC). Connected to > processor local bus and with pci express there is a Virtex 4 > (xc4vfx60). > > -Marco- Hide quoted text - > > - Show quoted text - The O'Reilly book Linux Device Drivers is good. I'd guess that the communication to the FPGA is via memory mapped I/O through the local bus You might browse sourceforge.net and see if you can find a similar driver and adapt it. I ended up writing my own simple one. I did the minimal in kernel (driver) space and put most of the end functionality in user space by creating library routines because it was convenient for the needs of my particular interface. It was my first driver. The whole concept I used worked quite well, but initially, I got criticized a lot by the snooty software folks. Good luck and have fun! -NewmanArticle: 119915
On Mon, 28 May 2007 06:37:16 -0700, Test01 <cpandya@yahoo.com> wrote:
>John,
>
>I am all for driving 3.3V pushpull instead of open drain from Spartan3 FPGA but ultimately yhr receiver needs to see 1.8V signal without adding any blue wires to the board. From the FPGA driver I have 150 ohm pull-up to 1.8V and then I have 100 Ohm serial resistor to the receiver. The receiver internally has resistor that varies from 400 Ohm to 700 Ohm. Keeping this termination sceheme in mind, I am trying to figure out how I can drive LVCMOSS33 Pushpull? Since this board is in production I can not add pulldown resistor and such.
>
>Thanks for your feedback.
Is your circuit....
+3.3
|
|
150r
|
|
| 60r trace
fpga----------+==============================================----100r----load
?
John
Article: 119916
All,
I simulated a GTLP IO cell, with an external 50 ohm pullup to 1.8 volts
driving a 60 ohm pcb trace. At the end, I have a split 100 ohm
termination, to 1.8V and ground.
1.8 volts 1.8 volts
| |
50 ohms 100 ohms
IO pin | 60 ohms |
GTLP----|-===============================----Load
|
100 ohms
|
GND
VERY FAST rise and fall times (2 volts/ns). GTLP will be the fastest
possible IO standard you could select for this. It is by the standard,
open drain (uses the 50 ohm external R for pullup). No need to mess
around with trying to control the tristate when pulling high (as GTLP
can't pull high internally).
The above is the recommended (and simulated) solution. An alternative
to the split 100 ohm termination is a single 50 ohms to a 100 pF
capacitor to ground, or 50 ohms to 0.9 V termination supply.
Austin
John Larkin wrote:
> On Mon, 28 May 2007 06:37:16 -0700, Test01 <cpandya@yahoo.com> wrote:
>
>> John,
>>
>> I am all for driving 3.3V pushpull instead of open drain from Spartan3 FPGA but ultimately yhr receiver needs to see 1.8V signal without adding any blue wires to the board. From the FPGA driver I have 150 ohm pull-up to 1.8V and then I have 100 Ohm serial resistor to the receiver. The receiver internally has resistor that varies from 400 Ohm to 700 Ohm. Keeping this termination sceheme in mind, I am trying to figure out how I can drive LVCMOSS33 Pushpull? Since this board is in production I can not add pulldown resistor and such.
>>
>> Thanks for your feedback.
>
> Is your circuit....
>
>
> +3.3
> |
> |
> 150r
> |
> |
> | 60r trace
> fpga----------+==============================================----100r----load
>
>
> ?
>
>
>
> John
>
>
>
>
Article: 119917On May 28, 9:48 am, Test01 <cpan...@yahoo.com> wrote: > Newman, > > Unfortunately, I do not have liberty to use the VRP and VRN pins. From the S3 FPGA output pin, I have 150 Ohm pull-up and then ohm series resistor close to the receiver. I can change the values of these resistors. I was thinking about driving the FPGA output pin 3.3V push-pull and then remove the 1.8V pull-up but increase the series terminatination value. Test01, I'm no expert, but series termination values are typically located close to the source and are used in point to point connections. End terminations are parallel and terminated to the characteristic impedance of the transmission line. The case under discussion now is one that I have never encountered. I saw the hyperlynx demo do an AC termination. That was cool. If the connection from the FPGA is a transmission line and it is not terminated properly, you can expect reflections that manifest themselves as more ringing. Do you see lots of ringing going from high to low? Some IC's have an input clamp diode to VCC IO that can clamp the voltage if the input current is limited by a series resistor to a safe value. That hyperlynx tool is cool. I wish I had it. Maybe you can talk your boss into getting it. Thanks Symon for the link. I am really out of my environment on this topic, so take my observations with a grain of salt. Sometimes it is best to change the design even if it is in production. Many boards have different rev levels. It's a tough call. - NewmanArticle: 119918
On 29 mai, 05:08, Guru <ales.gor...@email.si> wrote: > Hi Patrick, > > I am working with a FX12 MiniModule and MPMC2. I have tried lots of > variations for FLASH booting. I have not implemented OPB_EMC in my > latest design (under EDK 9.1) since I have not enough logic resources. > My experience from EDK 8.2: > in core connect architecture (no MPMC2) Flashwriter and booting works > with OPB_EMC and PLB_EMC (uses more logic resources). The > Flashwriter.tcl had to be modified from 8.1 to 8.2 because some of the > functions changed. In MPMC2 architecture the Flashwriter fails but I > was able to boot from flash if programmed from other HW (i.e. > CoreConnect). > If you find any more detail please let me know. > > Cheers, > > Guru I should have been more precise, it is indeed the Flashwriter that fails. Your idea of using a different architecture for the Flashwriter part is very good, I should have thought of that. I just tried an architecture without MPMC2 (the ref design from Avnet mentionned above actually) and not surprinsingly, Flashwriter works. Now going back to the MPMC2 design however, the bootloader fails in a strange way. It successfully loads the whole program into DDR but fails at the very last memcpy. This is the memcpy that copies the address of the beginning of the program to 0xFFFFFFFC. For some strange reason, the program never returns from that call to memcpy. I verified with a memory dump that the MPMC2 architecture can succesfully read without error the whole program in flash. The dump is exactly the same as my .srec file. I am puzzled by this. PatrickArticle: 119919
Hello, If you are looking for a plain RTL logic "hello world" design for an FPGA (in Verilog) please see: http://www.engr.sjsu.edu/~crabill This is based on the Spartan-3E Starter Kit but can be easily adpated to any other board you have. Eric "Antti" <Antti.Lukats@googlemail.com> wrote in message news:1180431143.324920.278980@g4g2000hsf.googlegroups.com... >> Is there anything like a HELLO WORLD program for FPGAs ? I know it >> depends on my board layout, but I do have the UCF file that has the pin >> assignments. But putting this together in the project is starting to >> confuse me. >> >> any help would be really appreciated ! >> >> Thamks, Claire. > > hello world (VHDL) > > LED <= '1'; > > /// > > NET LED = "xxx"; # please lookup ucf or manual > > > are you looking for this? > > Antti > > > > > > > > >Article: 119920
Hi, We are using FIFO in our design. The FIFO has been generated using CoreGenerator 2.3. The programmable flags have been enabled. The threshold values have been kept within the depth limit. However, when we try to synthesize on Xilinx, we get warnings: WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<9>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<8>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<7>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<6>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<5>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<4>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<3>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<2>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<1>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<0>' has no driver Similar warnings are got for 'prog_empty_thresh_assert', 'prog_full_thresh_negate', 'prog_full_thresh', 'prog_empty_thresh_negate', 'prog_empty_thresh', Secondly, our top level entity of the FIFO generated by Coregen does not have signals labeled rd_clk and wr_clk. Still we got the following errors :Article: 119921
On May 29, 3:17 pm, Vijayant <vijayant.bhatna...@gmail.com> wrote: Hi, We are using FIFO in our design. The FIFO has been generated using CoreGenerator 2.3. The programmable flags have been enabled. The threshold values have been kept within the depth limit. However, when we try to synthesize on Xilinx, we get warnings: WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<9>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<8>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<7>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<6>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<5>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<4>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<3>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<2>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<1>' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert<0>' has no driver Similar warnings are got for 'prog_empty_thresh_assert', 'prog_full_thresh_negate', 'prog_full_thresh', 'prog_empty_thresh_negate', 'prog_empty_thresh', Secondly, our top level entity of the FIFO generated by Coregen does not have signals labeled rd_clk and wr_clk. Still we got the following errors : NgdBuild:452 - logical net 'fifo1/fifo1/BU2/rd_clk' has no driver NgdBuild:452 - logical net 'fifo1/fifo1/BU2/wr_clk' has no driver Pls help. Regards, VijayantArticle: 119922
Austin, yes. from FPGA LVCMOSS33 Open drain output, I have 60 Ohm tranmission line and then to 150 Ohm pull-up to 1.8V and then from there to 100 Ohm series resistor to the load. By looking at the waveform, we are seeing some ledges (steps) on the rising edge. My solution to acheive better slew rate will be to lower the pull-up resistor value down to 60 Ohms and lower the series termination down to 22 Ohms. 60 Ohm pull-up termination will be close to the tranmsmission line impedance of 60 Ohms. By looking at the V-I curve the bottom transistor voltage drop is about 200mV at 15.6 mA. This translates to only 12.8 Ohms of ON resistance. Thus I can afford to lower the pull-up resistor down to 60 Ohms. This will still give me 400mV low swing. Is that correct?Article: 119923
On May 29, 4:40 am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Pablo Bleyer Kocik wrote: > > Dear group: > > > PacoBlaze 2.2 has been released. This version solves some bugs that > > were still lurking in the stack and interrupt manipulation. The cores > > have also received more testing, and more debug information has been > > added to simulations enabled with the HAS_DEBUG macro. Instructions > > also have now a one-hot encoding format that is used when > > USE_ONEHOT_ENCODING is defined. Unfortunately, the compatibility with > > Icarus Verilog is broken but I am still working on it. > > > The KCAsm assembler has been tweaked a bit to accept constructs in > > the form of the original KCPSM assembler, so that most PSM files > > should be accepted with little or no modification. > > > The PacoBlaze web site is athttp://bleyer.org/pacoblaze, where you > > can find more information and links to the source distribution. > > Hi Pablo, > Can you add a simple table of Options/Resource, along the lines of > the one here ? > > http://www.latticesemi.com/Mico8 > > -jg Jim, the link is broken. What kind of table are you referring to? PacoBlaze has been written from scratch following Xilinx's documentation of their PicoBlaze processor, so any resource configuration (registers, instructions, scratchpad memory) applies to PacoBlaze. The only exception are my own extensions for PacoBlaze3m (16-bit ALU with multiplier). Regards.Article: 119924
Hi all linux users there, I was wondering if the ISE/EDK linux installation scripts are supposed to create desktop icons and/or create appropriate entries in the program menu? I have installed both tools on a Kubuntu system and none of these were created... Thanks, /Mikhail
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z