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On 29 mai, 17:31, Guru <ales.gor...@email.si> wrote:
> Patrick,
>
> I think I know what the problem is ! Did you specify in bootloader's
> linker script where to boot after reading from flash?
> It looks like his:
> .boot0 :
> {
> *(.boot0)
> _end = .;
> } > ddr
>
> .boot : { *(.boot) } > ddr
>
> I hope it will boot properly :)
>
> Cheers,
>
> Guru
Thanks for the suggestion, I'll have to try that out. I think you
meant to say to modify the linker script of the _application_ loaded
from flash, not the bootloader?
I found an interresting note in the Embedded System Tools Reference
Manual:
"If your application is going to be loaded from a bootloader, you
might not want to
overwrite the bootloader's processor reset vector with that of your
application. This reexecutes
the bootloader on a processor reset instead of your application. To
achieve this,
your application must not bring in boot.o as a startup file. Unlike
other compiler startup
files, boot.o is not explicitly linked in by the compiler. Instead,
the default linker scripts
and the tools for generating the linker scripts specify boot.o as a
startup file. You must
remove the STARTUP directive in such linker scripts. You must also
modify the ENTRY
directive to be _start instead of _boot."
I tried that this morning and it works without modifications to the
bootloader code. The drawback is that one needs a different linker
script for loading directly in ram or for loading from flash.
Yesterday however I was also able to modify the bootloader code to
avoid the last memcpy to FFFFFFFC, along with a few other
modifications, and it works fine. The advantage is that now I can
avoid the modifications to the linker script mentionned above.
So I finally have a working solution, although it requires loading
another design to program the flash. Not a big deal since programming
the flash shouldn't happen often.
Anyway, all that to say problem solved. Thanks for your help.
Patrick
Article: 119976Does anyone know if the Xilinx CIC core will work in the Spartan 3? It's not listed as a target (only Spartan IIE) but then the data sheet is dated 2002, wheras S3 apparently was announced in 2003...Article: 119977
Yes, You may have to hand edit the ucf file, and check that the VHDL or verilog is not instantiating any input. The Vref pin is only used if you have a standard that uses an input comparator in that bank. Austin Test01 wrote: > Austin, > > So those VREF pins can still be used as user I/O pins if I use GTL output? If so that will be great. I tried using one GTL output and the constraint editor assigned the output as GTLP and the I/O Pin corresponding to VREF was assigned as VREF PIN. This is why I am asking. > > THanks.Article: 119978
On May 30, 5:39 am, Gabor <g...@alacron.com> wrote: > On May 29, 8:10 pm, jon...@gmail.com wrote: > > > I recently built a prototype using a xilinx spartan-iie specifically > > the xc2s150e-fgg456 which is programmed with an xcf02s prom. I have > > the prom connected first in the jtag chain. I am unable to detect the > > fpga. If i "tap" the tdo of the prom i can detect and program it fine, > > but the tdo of the fpga is always floating. I found an error in my > > design where the program pin, which is connected to the cf pin on the > > prom, is pulled high with a 4k7 resistor. I have tried pulling it low > > to no avail. > > The Program pin is active low, so pulling it high is the right > thing to do. > > > I am able to access the tdo solderball from the side, so > > i know it is not a bad connection. Also, while programming the prom, > > the fpga seems to randomly pull outputs high/low about once every > > second. I'm not sure how this is possible, but it would indicate to me > > that the data stream is able to cause a reset of the chip. Does anyone > > know how i can get further information on the problem, or have any > > ideas what the problem could be? Thanks in advance for any help. > > Make sure you have all of the JTAG connections to the FPGA. A > bad TMS connection for instance could cause the FPGA to enter > a boudary scan test mode rather than program mode. This could > also explain why you can't initialize the chain with the FPGA > in place. It is hard to tell if things are connected to the bga. I'm thinking about setting up a fast rise time clock signal with a large series resistor to each jtag pin. Then i can try to detect the gate capacitance on a scope. Afaik unconnected balls are pretty unlikely, but shorts are more likely. In my design tms and tck are only next to gnd and nc pins. They are definately not shorted to ground. Somewhere i read that any assertion of tms should make tdo come out of highz. Is that true? > > Also check all of the power supplies to the FPGA. You need > core power and also Vcco for the appropriate banks. Look > at the data sheet to see which supply runs the TDO pin. > All vcco are powered with 3.3 and vccc is 1.8. The rails measure correctly. The chip seems to be working as it is ever so slightly warm while running and some things work. Like done is actively pulled low. Also, when the chip does it;s restting while writing the prom, it is able to source and sink current. > And double check the PROG_B pin connection to be sure it is > on the CF output of the prom. Make sure the mode pins of the > FPGA are set for master serial or JTAG mode (master serial > if you want it to boot up from the PROM, JTAG mode really > just disables other modes so you can debug the JTAG problem > easier). > It would be really hard to change the mode pins. My next board might have this as an option. Instead, i removed the prom and am now feading the fpga's tdi directly from my programmer. > HTH, > Gabor Is it possible that my programmer was supplying a clean enough tck/tms for the prom but not for the fpga? It seems like even dirty signals would cause tdo to be asserted in some way. Thanks, Jon PryArticle: 119979
Hi, I recently got a nexys -1000 board for a project i'm working on and would like to put a xilinx EDK design on the board, however Digilent don't provide a .xbd (board description file) for this board. Rather than re-invent the wheel i was wondering if anyone out there had found one or had already compiled one? Any help would be greatly appreciated.Article: 119980
Hi, I wonder if someone know where I can buy the "Spartan-3E DIG-3E1600 Development Board Kit" http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DIG-3E1600&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS but not from xilinx (says to buy from digilent) and not from digilent (says board not currently available). Some month ago I contacted Digilent and their answer was "We will not be selling this board in the foreseeable future" thanks SandroArticle: 119981
"Sandro" <sdroamt@netscape.net> wrote in message news:1180543116.694676.24010@o5g2000hsb.googlegroups.com... > Hi, > I wonder if someone know where I can buy the "Spartan-3E DIG-3E1600 > Development Board Kit" > > > http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable > > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DIG-3E1600&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS > > but not from xilinx (says to buy from digilent) and not from digilent > (says board not currently available). > > Some month ago I contacted Digilent and their answer was > "We will not be selling this board in the foreseeable future" > > thanks > Sandro I thought the only reason the board was currently unavailable for sale directly by Digilent was because the more costly bundled version http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-SP3E1600E-DK-UNI-G used that same board. If Xilinx has the raw board as "Buy from Digilent" it may be that Digilent can now sell the board even though the web page says "Not surrently available for sale." Please try calling the folks at Digilent - they're pretty responsive but sometimes get a backlog in their email. Phone calls can go more quickly! If you can use the EDK bundle, you should be able to get that through distribution per the Xilinx page referenced above. - John_HArticle: 119982
Hi Gurus, I need help desperately. Please help. Regards, Vijayant On May 29, 3:19 pm, Vijayant <vijayant.bhatna...@gmail.com> wrote: > On May 29, 3:17 pm, Vijayant <vijayant.bhatna...@gmail.com> wrote: > Hi, > We are using FIFO in our design. The FIFO has been generated using > CoreGenerator 2.3. The programmable flags have been enabled. The > threshold values have been kept within the depth limit. However, when > we try to synthesize on Xilinx, we get warnings: > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<9>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<8>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<7>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<6>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<5>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<4>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<3>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<2>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<1>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<0>' has no driver > > Similar warnings are got for 'prog_empty_thresh_assert', > 'prog_full_thresh_negate', 'prog_full_thresh', > 'prog_empty_thresh_negate', 'prog_empty_thresh', > > Secondly, our top level entity of the FIFO generated by Coregen does > not have signals labeled rd_clk and wr_clk. Still we got the > following > errors : > NgdBuild:452 - logical net 'fifo1/fifo1/BU2/rd_clk' has no driver > NgdBuild:452 - logical net 'fifo1/fifo1/BU2/wr_clk' has no driver > > Pls help. > > Regards, > VijayantArticle: 119983
"Vijayant" <vijayant.bhatnagar@gmail.com> wrote in message news:1180466343.252183.170500@p77g2000hsh.googlegroups.com... > On May 29, 3:17 pm, Vijayant <vijayant.bhatna...@gmail.com> wrote: > Hi, > We are using FIFO in our design. The FIFO has been generated using > CoreGenerator 2.3. The programmable flags have been enabled. The > threshold values have been kept within the depth limit. However, when > we try to synthesize on Xilinx, we get warnings: > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<9>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<8>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<7>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<6>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<5>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<4>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<3>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<2>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<1>' has no driver > WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ > prog_empty_thresh_assert<0>' has no driver > > Similar warnings are got for 'prog_empty_thresh_assert', > 'prog_full_thresh_negate', 'prog_full_thresh', > 'prog_empty_thresh_negate', 'prog_empty_thresh', > > Secondly, our top level entity of the FIFO generated by Coregen does > not have signals labeled rd_clk and wr_clk. Still we got the > following > errors : > NgdBuild:452 - logical net 'fifo1/fifo1/BU2/rd_clk' has no driver > NgdBuild:452 - logical net 'fifo1/fifo1/BU2/wr_clk' has no driver > > Pls help. > > Regards, > Vijayant Can you find the instantiation of BU2 in your code? You'll need to have ports on BU2 of rd_clk, wr_clk, and prog_empty_thresh_assert. I can't comment on why this aren't connected in the coregen output according to your flow, only that there are ports (according to the software) and they don't appear to be connected (in BU2, according to the software). Good luck on this very basic level of "looking at your code."Article: 119984
On May 30, 11:28 am, mozilla <godzilla...@gmail.com> wrote: > Hi, > > I recently got a nexys -1000 board for a project i'm working on and > would like to put a xilinx EDK design on the board, however Digilent > don't provide a .xbd (board description file) for this board. Rather > than re-invent the wheel i was wondering if anyone out there had found > one or had already compiled one? Haven't done anything with the EDK, but so far I've found very little indication that many people have bought the board at all. Suprising as it's an interesting one... perhaps because it's an independent digilent product and not one made for Xilinx?Article: 119985
On 2007-05-30, raxpeter@gmail.com <raxpeter@gmail.com> wrote:
> Dear Folks !
>
> I'm hvin a rather outdated XS40 board, which I'm planning to start
> experiment with. Unfortunately, I don't have the Parallel Download
> cable for it.
>
> Is there any circuitry inside the cable or is it just pin-to-pin
> connection ?? Can anybody clarify this for me ?
From what I remember [1] it is just a straight pin-to-pin connection.
www.xess.com do have old manuals available, you could always take
a look there if in doubt.
BTW, do you have software available which can handle the FPGA
on it? There hasn't been any support for the XC4K fpga for quite a
long time now in ISE...
Good luck with your experimentation!
/Andreas
[1] I have rather fond memories of this board since it was the
prototype board which introduced me to FPGAs a number of years
ago.
Article: 119986In article <1180507013.553103.267690@a26g2000pre.googlegroups.com>, Venkat <venkat.japan@gmail.com> wrote: >Hi all, >Can anyone suggest simple algorithms for implementation of finding the >inverse of a matrix (4 X 4)? Even information of IP Cores for such >functionality will be greatly appreciated. How long have you got? Gaussian elimination in software on an implemented microprocessor will work, relatively slowly; if you've got enormous amounts of hardware, each entry of the inverse is of the form [some sum of six products of three entries from the matrix] divided by the determinant, which is a sum of 24 products each of four entries from the matrix, and you can compute everything in parallel and do the whole thing in a few cycles limited by the number of multipliers and by the depth of your addition trees. Perhaps a good trade-off is Gaussian elimination in hardware; build a circuit which takes inputs A0..A7, B0..B7 and K, and outputs A0-B0*K, A1-B1*K ... Then start off with m00 m01 m02 m03 1 0 0 0 m10 m11 m12 m13 0 1 0 0 m20 m21 m22 m23 0 0 1 0 m30 m31 m32 m33 0 0 0 1 in four eight-wide registers, and do successively row0 -> row0 * 1/m00 row1 -> row1 - m10 * row0 row2 -> row2 - m20 * row0 row3 -> row3 - m30 * row0 row1 -> row1 * 1/m11 row0 -> row0 - m01 * row1 row2 -> row2 - m21 * row1 row3 -> row3 - m31 * row1 and similarly scaling row2 and row3 to have a 1 in the diagonal element then subtracting them from the other rows to kill off the off-diagonal entries. Or perhaps there are cleverer FPGA-appropriate methods; I'm a mathematician not a hardware person. TomArticle: 119987
bngguy <bngguy@gmail.com> wrote: >Hi, > I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), >here's what i want to accomplish --> > >The FIR Filter coefficients are generated on a host system using >LabView, these coefficients are written to a RAM / PROM on a DSP >card , the number of taps is constant but other parameters like >sampling frequency and cut off frequencies can change according to >requirements. > >The FPGA reads these coefficients from the RAM / PROM and implements >the FIR Filter.There should be a single bit file that is downloaded to >configure the FPGA. > >Any pointers in the right direction would be appreciated. It is (probably) easy to have the DSP download the coefficients into the fpga through some serial (SPI-like) interface. An SPI interface can consist of a counter generating the bit addres (BRAM in 1 bit mode on the configuration side). The SPI clock can be the clock for the counter and the memory, the SPI select resets the counter and disables writing to the memory when low. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 119988
Peter Alfke <peter@xilinx.com> wrote: >X-Fest is a very successful and highly technical seminar series, given >in 92 cities worldwide. >For the June 5, 12, and 14 seminars in three German locations, I will >give the keynote address. >Come and learn for a full day, “auf deutsch” >For details, and to register, click on: > >http://eetimes.eu/design/199500991 >http://www.em.avnet.com/xfest/xlx > >Peter Alfke, Xilinx Applications, with apologies for this commercial >message. Hmm, so many locations in Germany... Amsterdam is a much better choice :-) -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 119989
cs, Heck, we (APD FPGA Lab) have purchased Digilent boards for use here at Xilinx in the past! A lot cheaper than fiddling with making something ourselves. Once a board exists from a vendor, no reason to re-invent the wheel. I bought a Digilent Spartan 3E board personally to teach a class, using class materials from San Jose University, and my co-worker Eric Crabill. I am so very pleased that there are enough students using Xilinx chips that Digilent can make a successful business out of making and selling the boards. The concept is simple: buy one board, and it lasts through a number of EE and CS courses (introduction to logic, HDL programming, machine architectures, embedded systems, IO/Memory/Interfacing, etc...). The cost is less than one engineering textbook, the student owns it (so they take care of it), and it is useful even after they graduate. That and the ubiquitous student laptop pc, and they are "in business." AustinArticle: 119990
On May 30, 11:09 am, n...@puntnl.niks (Nico Coesel) wrote: > Peter Alfke <p...@xilinx.com> wrote: > >X-Fest is a very successful and highly technical seminar series, given > >in 92 cities worldwide. > >For the June 5, 12, and 14 seminars in three German locations, I will > >give the keynote address. > >Come and learn for a full day, "auf deutsch" > >For details, and to register, click on: > > >http://eetimes.eu/design/199500991 > >http://www.em.avnet.com/xfest/xlx > > >Peter Alfke, Xilinx Applications, with apologies for this commercial > >message. > > Hmm, so many locations in Germany... Amsterdam is a much better choice > :-) > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nlArticle: 119991
"Nico Coesel" <nico@puntnl.niks> wrote in message news:465dbd7f.165182269@news.planet.nl... > Peter Alfke <peter@xilinx.com> wrote: > >>X-Fest is a very successful and highly technical seminar series, given >>in 92 cities worldwide. >>For the June 5, 12, and 14 seminars in three German locations, I will >>give the keynote address. >>Come and learn for a full day, "auf deutsch" >>For details, and to register, click on: >> >>http://eetimes.eu/design/199500991 >>http://www.em.avnet.com/xfest/xlx >> >>Peter Alfke, Xilinx Applications, with apologies for this commercial >>message. > > Hmm, so many locations in Germany... Amsterdam is a much better choice > :-) Sigh......I remember my students days in Amsterdam.....actually I can't, not sure what I was doing during those years.... must have been the many happy mushrooms I eat or was it the daily morning space cake?.... :-) Hans www.ht-lab.com > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 119992
Avnet picked Eindhoven as the preferred site in the Netherlands. But the X-Fest seminar there was a month ago... But the traditional European FPGA conference will be in Amsterdam in August. PeterArticle: 119993
Peter Alfke schrieb: > X-Fest is a very successful and highly technical seminar series, given > in 92 cities worldwide. > For the June 5, 12, and 14 seminars in three German locations, I will > give the keynote address. > Come and learn for a full day, “auf deutsch” > For details, and to register, click on: > > http://eetimes.eu/design/199500991 > http://www.em.avnet.com/xfest/xlx > Has anyone success to register on the avnet site? It didn't work for me. Tried IE and Firefox. ThomasArticle: 119994
Hans,
Like the joke here about attending UC Berkeley in the late 1960's
("summer of love"): "if you can remember it, you weren't here."
By the way, I was (for a short time) a counselor for the BCIPD (Berkeley
Committee for Information on Psychedelic Drugs): one of the great
crimes, and wastes of good minds was the abuse of both legal, and
illegal drugs by the youth of that time. These poor souls are now
cluttering up the mental hospitals, or wandering the streets, and have
become a burden to society.
Not that I have any solution to this (continuing) problem, but I at
least had the chance to talk to people and try to convince them not to
turn their brains into soup.
I am also fortunate I survived.
Austin
Article: 119995Hello, I'm trying to use a slightly unconventional way of configuring a Xilinx Virtex4 FPGA that as far as I can tell should work, but doesn't. The plan involves using a microcontroller to place an atmel serial flash into continuous read mode, and then relinquish control of the flash's clock and data output lines to the FPGA, and finally release INIT. The FPGA, set to Master Serial mode, then begins clocking the data out of the flash as if it were clocking out of a xilinx PROM. It all seems to work the way it should -- the right data appears on the data line -- but DONE never goes high, it just keeps clocking as if it's not getting any data. The one difference between the flash and a xilinx PROM is that the flash outputs data on the falling edge of the clock, while the PROM outputs on the rising edge. And indeed, if I place an inverter in line with CCLK, the configuration works fine. I don't understand why the clock polarity is causing a problem given that the FPGA supposedly samples on the rise of CCLK. On the rise of CCLK, the data out of the flash has been stable for a full cycle, having changed on the fall of CCLK. Anyone know what I'm missing? Mike.Article: 119996
Hello, I'm trying to use a slightly unconventional way of configuring a Xilinx Virtex4 FPGA that as far as I can tell should work, but doesn't. The plan involves using a microcontroller to place an atmel serial flash into continuous read mode, and then relinquish control of the flash's clock and data output lines to the FPGA, and finally release INIT. The FPGA, set to Master Serial mode, then begins clocking the data out of the flash as if it were clocking out of a xilinx PROM. It all seems to work the way it should -- the right data appears on the data line -- but DONE never goes high, it just keeps clocking as if it's not getting any data. The one difference between the flash and a xilinx PROM is that the flash outputs data on the falling edge of the clock, while the PROM outputs on the rising edge. And indeed, if I place an inverter in line with CCLK, the configuration works fine. I don't understand why the clock polarity is causing a problem given that the FPGA supposedly samples on the rise of CCLK. On the rise of CCLK, the data out of the flash has been stable for a full cycle, having changed on the fall of CCLK. Anyone know what I'm missing? Mike.Article: 119997
Dear Folks ! I'm hvin a rather outdated XS40 board, which I'm planning to start experiment with. Unfortunately, I don't have the Parallel Download cable for it. Is there any circuitry inside the cable or is it just pin-to-pin connection ?? Can anybody clarify this for me ? Regards, RakeshArticle: 119998
On May 30, 2:36 am, Venkat <venkat.ja...@gmail.com> wrote: > Hi all, > Can anyone suggest simple algorithms for implementation of finding the > inverse of a matrix (4 X 4)? Even information of IP Cores for such > functionality will be greatly appreciated. > > Thanks in advance, > Venkat. If you are trying to solve the equation Ax = y x = 1/A*y Then there are simpler methods than finding the inverse and multiplying. Otherwise, a long time ago, I used a symbolical math package that would symbolically give you the inverse of a matrix. That might give you an idea of the complexity. I'm sure that some of the newer ones will do it too. NewmanArticle: 119999
On May 29, 3:37 am, Pablo Bleyer Kocik <pabloble...@hotmail.com>
wrote:
> Dear group:
>
> PacoBlaze 2.2 has been released. This version solves some bugs that
> were still lurking in the stack and interrupt manipulation. The cores
> have also received more testing, and more debug information has been
> added to simulations enabled with the HAS_DEBUG macro. Instructions
> also have now a one-hot encoding format that is used when
> USE_ONEHOT_ENCODING is defined. Unfortunately, the compatibility with
> Icarus Verilog is broken but I am still working on it.
>
> The KCAsm assembler has been tweaked a bit to accept constructs in
> the form of the original KCPSM assembler, so that most PSM files
> should be accepted with little or no modification.
>
> The PacoBlaze web site is athttp://bleyer.org/pacoblaze, where you
> can find more information and links to the source distribution.
>
> I can't end this post without referring to the tragic and unexpected
> loss of Rodney Smith. My deepest condolences to his family and
> friends. He was one of the pioneers and pillars of this industry that
> has vamped digital design in a new era. He will be really missed.
>
> Warmest regards.
>
> --
> PabloBleyerKocik / "I wish I could sleep in a warm sleeping bag.
> pablo / No matter what happens I am going to climb
> McKinley."
> @bleyer.org / -- Naomi Uemura, 1984
Pablo,
I was also wondering if you fixed the issues with the assembler that I
wrote to you about last June?
>From email sent to you.
Pablo,
I encountered the follow error:
java -Dkcpsm=3 -Dbram=18 -Dmodule=isp -jar c:/clcfpga2/pacoblaze-2.1b1/
KCAsm.jar isp.psm isp.rmh Exception in thread "main" TokenMgrError:
Lexical error at line 668, column 23. Encountered:
"(" (40), after : ""
at KCAsmTokenManager.getNextToken(KCAsmTokenManager.java:539)
at KCAsm.jj_scan_token(KCAsm.java:629)
at KCAsm.jj_3_15(KCAsm.java:479)
at KCAsm.jj_3R_9(KCAsm.java:466)
at KCAsm.jj_3_17(KCAsm.java:381)
at KCAsm.jj_2_17(KCAsm.java:340)
at KCAsm.Arguments(KCAsm.java:213)
at KCAsm.CommandExpression(KCAsm.java:152)
at KCAsm.Expression(KCAsm.java:100)
at KCAsm.Start(KCAsm.java:84)
at KCAsm.main(KCAsm.java:41)
The line of code that cause this error is pointed to below.
load Areg, seedata0 ; pointer to eeprom parameters
fetch accm, fpwmminus0 ; pwmminus0
--> store accm, (Areg) ;
add Areg, 01 ;
I also noticed that there is a compatibility issue with the Xilinx
kcpsm assembler. It defaults to hex format for numbers while yours
defaults to decimal. This caused some of my constant definitions that
were hex values to give an errors
thanks for you help.
Dave Colson
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